[kmac] Remove entropy refresh timer
This commit removes the entropy refresh timer. The timer introduces
complex modeling in the KMAC scoreboard and does not help the security
model much.
The design is changed to:
- Remove the entropy timer entirely
- Introduce SW triggered EDN refresh request
- Increase EDN wait timer to support more than 5ms wait, which is the
maximum wait time to be expected.
- Add CSR for SW to check the number of Hashing op run
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/hw/ip/kmac/data/kmac.hjson b/hw/ip/kmac/data/kmac.hjson
index 216e164..a0e3e2b 100644
--- a/hw/ip/kmac/data/kmac.hjson
+++ b/hw/ip/kmac/data/kmac.hjson
@@ -67,6 +67,12 @@
desc: "Number of words for Encoded NsPrefix."
local: "true"
}
+ { name: "HashCntW"
+ type: "int unsigned"
+ default: "10"
+ desc: "Width of the hash counter in the entropy"
+ local: "true"
+ }
]
inter_signal_list: [
{ struct: "hw_key_req"
@@ -357,6 +363,17 @@
} // e: done
] // enum
} // f: cmd
+ { bits: "8"
+ name: "entropy_req"
+ desc: '''SW triggered Entropy Request
+
+ If writes 1 to this field
+ '''
+ } // f: entropy_req
+ { bits: "9"
+ name: "hash_cnt_clr"
+ desc: "If writes 1, it clears the hash (KMAC) counter in the entropy module"
+ }
]
} // R: CMD
{ name: "STATUS"
@@ -402,22 +419,20 @@
hwaccess: "hro"
regwen: "CFG_REGWEN"
fields: [
- { bits: "15:0"
- name: "entropy_timer"
- desc: '''Entropy period in clock cycles This register determines
- the refresh period. The value is the number of clock cycles. In
- every entropy period, the entropy generation logic in KMAC requests
- new entropy to EDN and feed the value into LFSR seed.
+ { bits: "9:0"
+ name: "prescaler"
+ desc: '''EDN Wait timer prescaler.
- If 0, the entropy generation logic does not refresh its seed. The
- software manually updates the seed by writing into "ENTROPY_SEED"
- registers. '''
+ EDN Wait timer has 16 bit value. The timer value is increased when the timer pulse is generated. Timer pulse is raises when the number of the clock cycles hit this prescaler value.
+
+ The exact period of the timer pulse is unknown as the KMAC input clock may contain jitters.
+ '''
}
{ bits: "31:16"
name: "wait_timer"
desc: '''EDN request wait timer.
- The entropy module in KMAC waits up to this field in clock cycles
+ The entropy module in KMAC waits up to this field in the timer pulse
after it sends request to EDN module. If the timer expires, the
entropy module moves to an error state and notifies to the system.
@@ -430,6 +445,34 @@
}
]
} // R: ENTROPY_PERIOD
+ {
+ name: "ENTROPY_REFRESH"
+ desc: '''Entropy Refresh Threshold and Counter
+
+ KMAC entropy can be refreshed after the given threshold KMAC operations
+ run. If the KMAC hash counter hits (GTE) the configured threshold, the
+ entropy module in the KMAC IP requests new seed to EDN and reset the KMAC
+ hash counter.
+
+ If the threshold is 0, the refresh by the counter does not work. And the
+ counter is only reset by the CMD.hash_cnt_clr CSR bit.
+ '''
+ swaccess: "rw"
+ hwaccess: "hro"
+ regwen: "CFG_REGWEN"
+ fields: [
+ { bits: "HashCntW-1:0"
+ name: "threshold"
+ desc: "Hash Threshold"
+ }
+ { bits: "HashCntW+15:16"
+ name: "hash_cnt"
+ desc: "Hash (KMAC) counter"
+ swaccess: "ro"
+ hwaccess: "hwo"
+ }
+ ]
+ } // R: ENTROPY_REFRESH
{ name: "ENTROPY_SEED_LOWER"
desc: '''Entropy Seed [31:0].
diff --git a/hw/ip/kmac/dv/env/kmac_scoreboard.sv b/hw/ip/kmac/dv/env/kmac_scoreboard.sv
index 62ad4da..7bbc08a 100644
--- a/hw/ip/kmac/dv/env/kmac_scoreboard.sv
+++ b/hw/ip/kmac/dv/env/kmac_scoreboard.sv
@@ -2166,13 +2166,6 @@
//cfg.clk_rst_vif.wait_clks(1);
//sha3_idle = 1;
- // if using EDN, KMAC will refresh entropy after finishing a hash operation
- if (entropy_mode == EntropyModeEdn) begin
- cfg.clk_rst_vif.wait_clks(1);
- in_edn_fetch = cfg.enable_masking;
- refresh_entropy = cfg.enable_masking;
- `uvm_info(`gfn, "refreshing entropy from EDN", UVM_HIGH)
- end
end else begin // SW sent wrong command
kmac_err.valid = 1;
diff --git a/hw/ip/kmac/kmac.core b/hw/ip/kmac/kmac.core
index fd43b01..9859077 100644
--- a/hw/ip/kmac/kmac.core
+++ b/hw/ip/kmac/kmac.core
@@ -19,14 +19,14 @@
- lowrisc:prim:edn_req
- lowrisc:ip:kmac_pkg
files:
+ - rtl/kmac_reg_pkg.sv
+ - rtl/kmac_reg_top.sv
- rtl/kmac_core.sv
- rtl/kmac_msgfifo.sv
- rtl/kmac_staterd.sv
- rtl/kmac_app.sv
- rtl/kmac_entropy.sv
- rtl/kmac_errchk.sv
- - rtl/kmac_reg_pkg.sv
- - rtl/kmac_reg_top.sv
- rtl/kmac.sv
file_type: systemVerilogSource
diff --git a/hw/ip/kmac/rtl/kmac.sv b/hw/ip/kmac/rtl/kmac.sv
index bdf5373..49ce25b 100644
--- a/hw/ip/kmac/rtl/kmac.sv
+++ b/hw/ip/kmac/rtl/kmac.sv
@@ -112,7 +112,7 @@
logic sha3_block_processed;
// EStatus for entropy
- logic entropy_in_progress, entropy_in_keyblock;
+ logic entropy_in_keyblock;
// KeyMgr interface logic generates event_absorbed from sha3_absorbed.
// It is active only if SW initiates the hashing engine.
@@ -224,11 +224,16 @@
kmac_cmd_e sw_cmd, checked_sw_cmd, kmac_cmd;
// Entropy configurations
- logic [15:0] entropy_timer_limit;
+ logic [9:0] wait_timer_prescaler;
logic [15:0] wait_timer_limit;
logic entropy_seed_update;
logic unused_entropy_seed_upper_qe;
logic [63:0] entropy_seed_data;
+ logic entropy_refresh_req;
+
+ logic [HashCntW-1:0] entropy_hash_threshold;
+ logic [HashCntW-1:0] entropy_hash_cnt;
+ logic entropy_hash_clr;
logic entropy_ready;
entropy_mode_e entropy_mode;
@@ -261,7 +266,7 @@
// Command signals
// TODO: Make the entire logic to use enum rather than signal
- assign sw_cmd = (reg2hw.cmd.qe) ? kmac_cmd_e'(reg2hw.cmd.q) : CmdNone;
+ assign sw_cmd = (reg2hw.cmd.cmd.qe) ? kmac_cmd_e'(reg2hw.cmd.cmd.q) : CmdNone;
`ASSERT_KNOWN(KmacCmd_A, sw_cmd)
always_comb begin
sha3_start = 1'b 0;
@@ -354,14 +359,23 @@
assign sw_key_len = key_len_e'(reg2hw.key_len.q);
// Entropy configurations
- assign entropy_timer_limit = reg2hw.entropy_period.entropy_timer.q;
- assign wait_timer_limit = reg2hw.entropy_period.wait_timer.q;
+ assign wait_timer_prescaler = reg2hw.entropy_period.prescaler.q;
+ assign wait_timer_limit = reg2hw.entropy_period.wait_timer.q;
// Seed updated when the software writes Entropy Seed [31:0]
assign unused_entropy_seed_upper_qe = reg2hw.entropy_seed_upper.qe;
assign entropy_seed_update = reg2hw.entropy_seed_lower.qe ;
assign entropy_seed_data = { reg2hw.entropy_seed_lower.q,
reg2hw.entropy_seed_upper.q};
+ assign entropy_refresh_req = reg2hw.cmd.entropy_req.q
+ && reg2hw.cmd.entropy_req.qe;
+
+ assign entropy_hash_threshold = reg2hw.entropy_refresh.threshold.q;
+ assign hw2reg.entropy_refresh.hash_cnt.de = 1'b 1;
+ assign hw2reg.entropy_refresh.hash_cnt.d = entropy_hash_cnt;
+
+ assign entropy_hash_clr = reg2hw.cmd.hash_cnt_clr.qe
+ && reg2hw.cmd.hash_cnt_clr.q;
// Entropy config
assign entropy_ready = reg2hw.cfg.entropy_ready.q;
@@ -508,7 +522,6 @@
// Default value
kmac_st_d = KmacIdle;
- entropy_in_progress = 1'b 0;
entropy_in_keyblock = 1'b 0;
unique case (kmac_st)
@@ -527,17 +540,15 @@
end
KmacPrefix: begin
- entropy_in_progress =1'b 1;
// Wait until SHA3 processes one block
if (sha3_block_processed) begin
- kmac_st_d = (reg2hw.cfg.kmac_en.q) ? KmacKeyBlock : KmacMsgFeed ;
+ kmac_st_d = (app_kmac_en) ? KmacKeyBlock : KmacMsgFeed ;
end else begin
kmac_st_d = KmacPrefix;
end
end
KmacKeyBlock: begin
- entropy_in_progress = 1'b 1;
entropy_in_keyblock = 1'b 1;
if (sha3_block_processed) begin
kmac_st_d = KmacMsgFeed;
@@ -547,7 +558,6 @@
end
KmacMsgFeed: begin
- entropy_in_progress = 1'b 1;
// If absorbed, move to Digest
if (sha3_absorbed && sha3_done) begin
// absorbed and done can be asserted at a cycle if Applications have
@@ -562,7 +572,6 @@
end
KmacDigest: begin
- entropy_in_progress = 1'b 1;
// SW can manually run it, wait till done
if (sha3_done) begin
kmac_st_d = KmacIdle;
@@ -901,8 +910,6 @@
.rand_consumed_i (sha3_rand_consumed),
// Status from internal logic
- //// SHA3 engine run indicator
- .in_progress_i (entropy_in_progress),
//// KMAC secret block handling indicator
.in_keyblock_i (entropy_in_keyblock),
@@ -912,15 +919,21 @@
.fast_process_i (entropy_fast_process),
//// Entropy refresh period in clk cycles
- .entropy_timer_limit_i (entropy_timer_limit),
- .wait_timer_limit_i (wait_timer_limit),
+ .wait_timer_prescaler_i (wait_timer_prescaler),
+ .wait_timer_limit_i (wait_timer_limit),
//// SW update of seed
- .seed_update_i (entropy_seed_update),
- .seed_data_i (entropy_seed_data),
+ .seed_update_i (entropy_seed_update),
+ .seed_data_i (entropy_seed_data),
+ .entropy_refresh_req_i (entropy_refresh_req),
+
+ // Status
+ .hash_cnt_o (entropy_hash_cnt),
+ .hash_cnt_clr_i (entropy_hash_clr),
+ .hash_threshold_i (entropy_hash_threshold),
// Error
- .err_o (entropy_err),
+ .err_o (entropy_err),
.err_processed_i (err_processed)
);
end else begin : gen_empty_entropy
@@ -943,14 +956,20 @@
logic unused_seed_update;
logic [63:0] unused_seed_data;
logic [31:0] unused_refresh_period;
+ logic unused_entropy_refresh_req;
assign unused_seed_data = entropy_seed_data;
assign unused_seed_update = entropy_seed_update;
- assign unused_refresh_period = {wait_timer_limit, entropy_timer_limit};
+ assign unused_refresh_period = ^{wait_timer_limit, wait_timer_prescaler};
+ assign unused_entropy_refresh_req = entropy_refresh_req;
+
+ logic unused_entropy_hash;
+ assign unused_entropy_hash = ^{entropy_hash_clr, entropy_hash_threshold};
+ assign entropy_hash_cnt = '0;
assign entropy_err = '{valid: 1'b 0, code: ErrNone, info: '0};
logic [1:0] unused_entropy_status;
- assign unused_entropy_status = {entropy_in_keyblock, entropy_in_progress};
+ assign unused_entropy_status = entropy_in_keyblock;
end
// Register top
@@ -1009,5 +1028,5 @@
`ASSERT_INIT(SecretKeyDivideBy32_A, (kmac_pkg::MaxKeyLen % 32) == 0)
// Command input should be onehot0
- `ASSUME(CmdOneHot0_M, reg2hw.cmd.qe |-> $onehot0(reg2hw.cmd.q))
+ `ASSUME(CmdOneHot0_M, reg2hw.cmd.cmd.qe |-> $onehot0(reg2hw.cmd.cmd.q))
endmodule
diff --git a/hw/ip/kmac/rtl/kmac_entropy.sv b/hw/ip/kmac/rtl/kmac_entropy.sv
index 8da19ab..461b86d 100644
--- a/hw/ip/kmac/rtl/kmac_entropy.sv
+++ b/hw/ip/kmac/rtl/kmac_entropy.sv
@@ -23,7 +23,6 @@
input rand_consumed_i,
// Status
- input in_progress_i,
input in_keyblock_i,
// Configurations
@@ -41,10 +40,20 @@
input seed_update_i,
input [63:0] seed_data_i,
+ //// SW may initiate manual EDN seed refresh
+ input entropy_refresh_req_i,
+
//// Timer limit value
//// If value is 0, timer is disabled
- input [EntropyTimerW-1:0] entropy_timer_limit_i,
- input [EdnWaitTimerW-1:0] wait_timer_limit_i,
+ input [TimerPrescalerW-1:0] wait_timer_prescaler_i,
+ input [EdnWaitTimerW-1:0] wait_timer_limit_i,
+
+ // Status out
+ //// Hash Ops counter. Count how many hashing ops (KMAC) have run
+ //// after the clear request from SW
+ output logic [kmac_reg_pkg::HashCntW-1:0] hash_cnt_o,
+ input hash_cnt_clr_i,
+ input [kmac_reg_pkg::HashCntW-1:0] hash_threshold_i,
// Error output
output err_t err_o,
@@ -159,26 +168,18 @@
/////////////
// Timers
- // "Entropy Timer": While in operation, if this entropy timer is enabled, FSM
- // fetches new entropy from LFSR when the timer is expired.
- //
// "Wait Timer": This timer is in active when FSM sends entropy request to EDN
// If EDN does not return the entropy data until the timer expired, FSM
// moves to error state and report the error to the system.
- typedef enum logic [1:0] {
- NoTimer = 2'h 0,
- EntropyTimer = 2'h 1,
- EdnWaitTimer = 2'h 2
- } timer_sel_e;
- timer_sel_e timer_sel;
-
- localparam int unsigned TimerW = (EntropyTimerW > EdnWaitTimerW)
- ? EntropyTimerW : EdnWaitTimerW;
- logic timer_enable, timer_update, timer_expired;
+ localparam int unsigned TimerW = EdnWaitTimerW;
+ logic timer_enable, timer_update, timer_expired, timer_pulse;
logic [TimerW-1:0] timer_limit;
logic [TimerW-1:0] timer_value;
+ localparam int unsigned PrescalerW = TimerPrescalerW;
+ logic [PrescalerW-1:0] prescaler_cnt;
+
// LFSR
//// SW configures to use EDN or SEED register as a LFSR seed
logic lfsr_seed_en;
@@ -191,13 +192,6 @@
logic storage_idx_clear;
logic storage_filled;
- // in_progress: check if in_progress de-asserted. It means hashing operation
- // is completed. Entropy logic refreshes seed and prepare new entropy.
- // de-asserting in_progress sets in_progress_deasserted, then when FSM moves
- // to StRandEdn, it clears the de-assertion. This is to not miss the
- // deassertion event.
- logic in_progress_deasserted, in_progress_clear, in_progress_d;
-
// Entropy valid signal
// FSM set and clear the valid signal, rand_consume signal clear the valid
// signal. Split the set, clear to make entropy valid while FSM is processing
@@ -216,20 +210,12 @@
timer_value <= timer_limit;
end else if (timer_expired) begin
timer_value <= '0; // keep the value
- end else if (timer_enable && |timer_value) begin // if non-zero timer v
+ end else if (timer_enable && timer_pulse && |timer_value) begin // if non-zero timer v
timer_value <= timer_value - 1'b 1;
end
end
- // select timer
- always_comb begin
- timer_limit = '0;
- unique case (timer_sel)
- EntropyTimer: timer_limit = TimerW'(entropy_timer_limit_i);
- EdnWaitTimer: timer_limit = TimerW'(wait_timer_limit_i);
- default: timer_limit = '0; // NoTimer
- endcase
- end
+ assign timer_limit = TimerW'(wait_timer_limit_i);
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
@@ -240,8 +226,52 @@
timer_expired <= 1'b 1;
end
end
+
+ // Prescaler
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ prescaler_cnt <= '0;
+ end else if (timer_update) begin
+ prescaler_cnt <= wait_timer_prescaler_i;
+ end else if (timer_enable && prescaler_cnt == '0) begin
+ prescaler_cnt <= wait_timer_prescaler_i;
+ end else if (timer_enable) begin
+ prescaler_cnt <= prescaler_cnt - 1'b 1;
+ end
+ end
+
+ assign timer_pulse = (timer_enable && prescaler_cnt == '0);
// Timers -------------------------------------------------------------------
+ // Hash Counter
+ logic threshold_hit;
+ logic threshold_hit_q, threshold_hit_clr; // latched hit
+
+ logic hash_progress_d, hash_progress_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) hash_progress_q <= 1'b 0;
+ else hash_progress_q <= hash_progress_d;
+ end
+
+ assign hash_progress_d = in_keyblock_i;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ hash_cnt_o <= '0;
+ end else if (hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i) begin
+ hash_cnt_o <= '0;
+ end else if (hash_progress_q && !hash_progress_d) begin
+ hash_cnt_o <= hash_cnt_o + 1'b 1;
+ end
+ end
+
+ assign threshold_hit = |hash_threshold_i && (hash_threshold_i <= hash_cnt_o);
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) threshold_hit_q <= 1'b 0;
+ else if (threshold_hit_clr) threshold_hit_q <= 1'b 0;
+ else if (threshold_hit) threshold_hit_q <= 1'b 1;
+ end
// LFSR =====================================================================
//// FSM controls the seed enable signal `lfsr_seed_en`.
@@ -325,26 +355,6 @@
// Storage expands to StateW ------------------------------------------------
- // In Process Logic =========================================================
- always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) begin
- in_progress_d <= 1'b 0;
- end else begin
- in_progress_d <= in_progress_i;
- end
- end
-
- always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) begin
- in_progress_deasserted <= 1'b 0;
- end else if (in_progress_d && !in_progress_i && (mode_i == EntropyModeEdn)) begin
- in_progress_deasserted <= 1'b 1;
- end else if (in_progress_clear) begin
- in_progress_deasserted <= 1'b 0;
- end
- end
- // In Process Logic ---------------------------------------------------------
-
///////////////////
// State Machine //
///////////////////
@@ -371,7 +381,8 @@
// Default Timer values
timer_enable = 1'b 0;
timer_update = 1'b 0;
- timer_sel = NoTimer;
+
+ threshold_hit_clr = 1'b 0;
// EDN request
entropy_req_o = 1'b 0;
@@ -399,8 +410,6 @@
storage_idx_clear = 1'b 0;
storage_update = 1'b 0;
- in_progress_clear = 1'b 0;
-
// Error
err_o = '{valid: 1'b 0, code: ErrNone, info: '0};
@@ -421,7 +430,6 @@
st_d = StRandEdn;
// Timer reset
- timer_sel = EdnWaitTimer;
timer_update = 1'b 1;
end
@@ -456,25 +464,14 @@
storage_idx_clear = 1'b 1;
rand_valid_clear = 1'b 1;
- end else if (mode_i == EntropyModeEdn) begin
- if (in_keyblock_i && timer_expired && |entropy_timer_limit_i) begin
- // Timer count is non-zero and timer expired
- st_d = StRandEdn;
+ end else if (entropy_refresh_req_i || threshold_hit_q) begin
+ st_d = StRandEdn;
- timer_update = 1'b 1;
- timer_sel = EdnWaitTimer;
+ // Timer reset
+ timer_update = 1'b 1;
- end else if (in_progress_deasserted) begin
- // hashing operation is completed, refresh the entropy and stop
- st_d = StRandEdn;
-
- in_progress_clear = 1'b 1;
-
- timer_update = 1'b 1;
- timer_sel = EdnWaitTimer;
- end else begin
- st_d = StRandReady;
- end
+ // Clear the threshold as it refreshes the hash
+ threshold_hit_clr = 1'b 1;
end else begin
st_d = StRandReady;
end
@@ -539,11 +536,6 @@
rand_valid_set = 1'b 1;
- // Based on the timer value, either reset the timer or just move
- if (mode_i == EntropyModeEdn && |entropy_timer_limit_i) begin
- timer_sel = EntropyTimer;
- timer_update = 1'b 1;
- end
end else begin
st_d = StRandExpand;
diff --git a/hw/ip/kmac/rtl/kmac_pkg.sv b/hw/ip/kmac/rtl/kmac_pkg.sv
index 7085c55..1e50841 100644
--- a/hw/ip/kmac/rtl/kmac_pkg.sv
+++ b/hw/ip/kmac/rtl/kmac_pkg.sv
@@ -80,8 +80,8 @@
} kmac_cmd_e;
// Timer
- parameter int unsigned EntropyTimerW = 16;
- parameter int unsigned EdnWaitTimerW = 16;
+ parameter int unsigned TimerPrescalerW = 10;
+ parameter int unsigned EdnWaitTimerW = 16;
// Entropy Mode Selection : Should be matched to register package Enum value
typedef enum logic [1:0] {
diff --git a/hw/ip/kmac/rtl/kmac_reg_pkg.sv b/hw/ip/kmac/rtl/kmac_reg_pkg.sv
index 6abed5b..e136ff7 100644
--- a/hw/ip/kmac/rtl/kmac_reg_pkg.sv
+++ b/hw/ip/kmac/rtl/kmac_reg_pkg.sv
@@ -9,6 +9,7 @@
// Param list
parameter int NumWordsKey = 16;
parameter int NumWordsPrefix = 11;
+ parameter int unsigned HashCntW = 10;
parameter int NumAlerts = 1;
// Address widths within the block
@@ -96,20 +97,36 @@
} kmac_reg2hw_cfg_reg_t;
typedef struct packed {
- logic [3:0] q;
- logic qe;
+ struct packed {
+ logic [3:0] q;
+ logic qe;
+ } cmd;
+ struct packed {
+ logic q;
+ logic qe;
+ } entropy_req;
+ struct packed {
+ logic q;
+ logic qe;
+ } hash_cnt_clr;
} kmac_reg2hw_cmd_reg_t;
typedef struct packed {
struct packed {
- logic [15:0] q;
- } entropy_timer;
+ logic [9:0] q;
+ } prescaler;
struct packed {
logic [15:0] q;
} wait_timer;
} kmac_reg2hw_entropy_period_reg_t;
typedef struct packed {
+ struct packed {
+ logic [9:0] q;
+ } threshold;
+ } kmac_reg2hw_entropy_refresh_reg_t;
+
+ typedef struct packed {
logic [31:0] q;
logic qe;
} kmac_reg2hw_entropy_seed_lower_reg_t;
@@ -189,19 +206,27 @@
} kmac_hw2reg_status_reg_t;
typedef struct packed {
+ struct packed {
+ logic [9:0] d;
+ logic de;
+ } hash_cnt;
+ } kmac_hw2reg_entropy_refresh_reg_t;
+
+ typedef struct packed {
logic [31:0] d;
logic de;
} kmac_hw2reg_err_code_reg_t;
// Register -> HW type
typedef struct packed {
- kmac_reg2hw_intr_state_reg_t intr_state; // [1541:1539]
- kmac_reg2hw_intr_enable_reg_t intr_enable; // [1538:1536]
- kmac_reg2hw_intr_test_reg_t intr_test; // [1535:1530]
- kmac_reg2hw_alert_test_reg_t alert_test; // [1529:1528]
- kmac_reg2hw_cfg_reg_t cfg; // [1527:1514]
- kmac_reg2hw_cmd_reg_t cmd; // [1513:1509]
- kmac_reg2hw_entropy_period_reg_t entropy_period; // [1508:1477]
+ kmac_reg2hw_intr_state_reg_t intr_state; // [1549:1547]
+ kmac_reg2hw_intr_enable_reg_t intr_enable; // [1546:1544]
+ kmac_reg2hw_intr_test_reg_t intr_test; // [1543:1538]
+ kmac_reg2hw_alert_test_reg_t alert_test; // [1537:1536]
+ kmac_reg2hw_cfg_reg_t cfg; // [1535:1522]
+ kmac_reg2hw_cmd_reg_t cmd; // [1521:1513]
+ kmac_reg2hw_entropy_period_reg_t entropy_period; // [1512:1487]
+ kmac_reg2hw_entropy_refresh_reg_t entropy_refresh; // [1486:1477]
kmac_reg2hw_entropy_seed_lower_reg_t entropy_seed_lower; // [1476:1444]
kmac_reg2hw_entropy_seed_upper_reg_t entropy_seed_upper; // [1443:1411]
kmac_reg2hw_key_share0_mreg_t [15:0] key_share0; // [1410:883]
@@ -212,10 +237,11 @@
// HW -> register type
typedef struct packed {
- kmac_hw2reg_intr_state_reg_t intr_state; // [53:48]
- kmac_hw2reg_cfg_regwen_reg_t cfg_regwen; // [47:47]
- kmac_hw2reg_cfg_reg_t cfg; // [46:43]
- kmac_hw2reg_status_reg_t status; // [42:33]
+ kmac_hw2reg_intr_state_reg_t intr_state; // [64:59]
+ kmac_hw2reg_cfg_regwen_reg_t cfg_regwen; // [58:58]
+ kmac_hw2reg_cfg_reg_t cfg; // [57:54]
+ kmac_hw2reg_status_reg_t status; // [53:44]
+ kmac_hw2reg_entropy_refresh_reg_t entropy_refresh; // [43:33]
kmac_hw2reg_err_code_reg_t err_code; // [32:0]
} kmac_hw2reg_t;
@@ -229,53 +255,54 @@
parameter logic [BlockAw-1:0] KMAC_CMD_OFFSET = 12'h 18;
parameter logic [BlockAw-1:0] KMAC_STATUS_OFFSET = 12'h 1c;
parameter logic [BlockAw-1:0] KMAC_ENTROPY_PERIOD_OFFSET = 12'h 20;
- parameter logic [BlockAw-1:0] KMAC_ENTROPY_SEED_LOWER_OFFSET = 12'h 24;
- parameter logic [BlockAw-1:0] KMAC_ENTROPY_SEED_UPPER_OFFSET = 12'h 28;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_0_OFFSET = 12'h 2c;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_1_OFFSET = 12'h 30;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_2_OFFSET = 12'h 34;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_3_OFFSET = 12'h 38;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_4_OFFSET = 12'h 3c;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_5_OFFSET = 12'h 40;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_6_OFFSET = 12'h 44;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_7_OFFSET = 12'h 48;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_8_OFFSET = 12'h 4c;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_9_OFFSET = 12'h 50;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_10_OFFSET = 12'h 54;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_11_OFFSET = 12'h 58;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_12_OFFSET = 12'h 5c;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_13_OFFSET = 12'h 60;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_14_OFFSET = 12'h 64;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_15_OFFSET = 12'h 68;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_0_OFFSET = 12'h 6c;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_1_OFFSET = 12'h 70;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_2_OFFSET = 12'h 74;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_3_OFFSET = 12'h 78;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_4_OFFSET = 12'h 7c;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_5_OFFSET = 12'h 80;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_6_OFFSET = 12'h 84;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_7_OFFSET = 12'h 88;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_8_OFFSET = 12'h 8c;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_9_OFFSET = 12'h 90;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_10_OFFSET = 12'h 94;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_11_OFFSET = 12'h 98;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_12_OFFSET = 12'h 9c;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_13_OFFSET = 12'h a0;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_14_OFFSET = 12'h a4;
- parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_15_OFFSET = 12'h a8;
- parameter logic [BlockAw-1:0] KMAC_KEY_LEN_OFFSET = 12'h ac;
- parameter logic [BlockAw-1:0] KMAC_PREFIX_0_OFFSET = 12'h b0;
- parameter logic [BlockAw-1:0] KMAC_PREFIX_1_OFFSET = 12'h b4;
- parameter logic [BlockAw-1:0] KMAC_PREFIX_2_OFFSET = 12'h b8;
- parameter logic [BlockAw-1:0] KMAC_PREFIX_3_OFFSET = 12'h bc;
- parameter logic [BlockAw-1:0] KMAC_PREFIX_4_OFFSET = 12'h c0;
- parameter logic [BlockAw-1:0] KMAC_PREFIX_5_OFFSET = 12'h c4;
- parameter logic [BlockAw-1:0] KMAC_PREFIX_6_OFFSET = 12'h c8;
- parameter logic [BlockAw-1:0] KMAC_PREFIX_7_OFFSET = 12'h cc;
- parameter logic [BlockAw-1:0] KMAC_PREFIX_8_OFFSET = 12'h d0;
- parameter logic [BlockAw-1:0] KMAC_PREFIX_9_OFFSET = 12'h d4;
- parameter logic [BlockAw-1:0] KMAC_PREFIX_10_OFFSET = 12'h d8;
- parameter logic [BlockAw-1:0] KMAC_ERR_CODE_OFFSET = 12'h dc;
+ parameter logic [BlockAw-1:0] KMAC_ENTROPY_REFRESH_OFFSET = 12'h 24;
+ parameter logic [BlockAw-1:0] KMAC_ENTROPY_SEED_LOWER_OFFSET = 12'h 28;
+ parameter logic [BlockAw-1:0] KMAC_ENTROPY_SEED_UPPER_OFFSET = 12'h 2c;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_0_OFFSET = 12'h 30;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_1_OFFSET = 12'h 34;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_2_OFFSET = 12'h 38;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_3_OFFSET = 12'h 3c;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_4_OFFSET = 12'h 40;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_5_OFFSET = 12'h 44;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_6_OFFSET = 12'h 48;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_7_OFFSET = 12'h 4c;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_8_OFFSET = 12'h 50;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_9_OFFSET = 12'h 54;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_10_OFFSET = 12'h 58;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_11_OFFSET = 12'h 5c;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_12_OFFSET = 12'h 60;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_13_OFFSET = 12'h 64;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_14_OFFSET = 12'h 68;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE0_15_OFFSET = 12'h 6c;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_0_OFFSET = 12'h 70;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_1_OFFSET = 12'h 74;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_2_OFFSET = 12'h 78;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_3_OFFSET = 12'h 7c;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_4_OFFSET = 12'h 80;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_5_OFFSET = 12'h 84;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_6_OFFSET = 12'h 88;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_7_OFFSET = 12'h 8c;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_8_OFFSET = 12'h 90;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_9_OFFSET = 12'h 94;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_10_OFFSET = 12'h 98;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_11_OFFSET = 12'h 9c;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_12_OFFSET = 12'h a0;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_13_OFFSET = 12'h a4;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_14_OFFSET = 12'h a8;
+ parameter logic [BlockAw-1:0] KMAC_KEY_SHARE1_15_OFFSET = 12'h ac;
+ parameter logic [BlockAw-1:0] KMAC_KEY_LEN_OFFSET = 12'h b0;
+ parameter logic [BlockAw-1:0] KMAC_PREFIX_0_OFFSET = 12'h b4;
+ parameter logic [BlockAw-1:0] KMAC_PREFIX_1_OFFSET = 12'h b8;
+ parameter logic [BlockAw-1:0] KMAC_PREFIX_2_OFFSET = 12'h bc;
+ parameter logic [BlockAw-1:0] KMAC_PREFIX_3_OFFSET = 12'h c0;
+ parameter logic [BlockAw-1:0] KMAC_PREFIX_4_OFFSET = 12'h c4;
+ parameter logic [BlockAw-1:0] KMAC_PREFIX_5_OFFSET = 12'h c8;
+ parameter logic [BlockAw-1:0] KMAC_PREFIX_6_OFFSET = 12'h cc;
+ parameter logic [BlockAw-1:0] KMAC_PREFIX_7_OFFSET = 12'h d0;
+ parameter logic [BlockAw-1:0] KMAC_PREFIX_8_OFFSET = 12'h d4;
+ parameter logic [BlockAw-1:0] KMAC_PREFIX_9_OFFSET = 12'h d8;
+ parameter logic [BlockAw-1:0] KMAC_PREFIX_10_OFFSET = 12'h dc;
+ parameter logic [BlockAw-1:0] KMAC_ERR_CODE_OFFSET = 12'h e0;
// Reset values for hwext registers and their fields
parameter logic [2:0] KMAC_INTR_TEST_RESVAL = 3'h 0;
@@ -286,7 +313,7 @@
parameter logic [0:0] KMAC_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
parameter logic [0:0] KMAC_CFG_REGWEN_RESVAL = 1'h 1;
parameter logic [0:0] KMAC_CFG_REGWEN_EN_RESVAL = 1'h 1;
- parameter logic [3:0] KMAC_CMD_RESVAL = 4'h 0;
+ parameter logic [9:0] KMAC_CMD_RESVAL = 10'h 0;
parameter logic [15:0] KMAC_STATUS_RESVAL = 16'h 4001;
parameter logic [0:0] KMAC_STATUS_SHA3_IDLE_RESVAL = 1'h 1;
parameter logic [0:0] KMAC_STATUS_FIFO_EMPTY_RESVAL = 1'h 1;
@@ -340,6 +367,7 @@
KMAC_CMD,
KMAC_STATUS,
KMAC_ENTROPY_PERIOD,
+ KMAC_ENTROPY_REFRESH,
KMAC_ENTROPY_SEED_LOWER,
KMAC_ENTROPY_SEED_UPPER,
KMAC_KEY_SHARE0_0,
@@ -390,63 +418,64 @@
} kmac_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] KMAC_PERMIT [56] = '{
+ parameter logic [3:0] KMAC_PERMIT [57] = '{
4'b 0001, // index[ 0] KMAC_INTR_STATE
4'b 0001, // index[ 1] KMAC_INTR_ENABLE
4'b 0001, // index[ 2] KMAC_INTR_TEST
4'b 0001, // index[ 3] KMAC_ALERT_TEST
4'b 0001, // index[ 4] KMAC_CFG_REGWEN
4'b 1111, // index[ 5] KMAC_CFG
- 4'b 0001, // index[ 6] KMAC_CMD
+ 4'b 0011, // index[ 6] KMAC_CMD
4'b 0011, // index[ 7] KMAC_STATUS
4'b 1111, // index[ 8] KMAC_ENTROPY_PERIOD
- 4'b 1111, // index[ 9] KMAC_ENTROPY_SEED_LOWER
- 4'b 1111, // index[10] KMAC_ENTROPY_SEED_UPPER
- 4'b 1111, // index[11] KMAC_KEY_SHARE0_0
- 4'b 1111, // index[12] KMAC_KEY_SHARE0_1
- 4'b 1111, // index[13] KMAC_KEY_SHARE0_2
- 4'b 1111, // index[14] KMAC_KEY_SHARE0_3
- 4'b 1111, // index[15] KMAC_KEY_SHARE0_4
- 4'b 1111, // index[16] KMAC_KEY_SHARE0_5
- 4'b 1111, // index[17] KMAC_KEY_SHARE0_6
- 4'b 1111, // index[18] KMAC_KEY_SHARE0_7
- 4'b 1111, // index[19] KMAC_KEY_SHARE0_8
- 4'b 1111, // index[20] KMAC_KEY_SHARE0_9
- 4'b 1111, // index[21] KMAC_KEY_SHARE0_10
- 4'b 1111, // index[22] KMAC_KEY_SHARE0_11
- 4'b 1111, // index[23] KMAC_KEY_SHARE0_12
- 4'b 1111, // index[24] KMAC_KEY_SHARE0_13
- 4'b 1111, // index[25] KMAC_KEY_SHARE0_14
- 4'b 1111, // index[26] KMAC_KEY_SHARE0_15
- 4'b 1111, // index[27] KMAC_KEY_SHARE1_0
- 4'b 1111, // index[28] KMAC_KEY_SHARE1_1
- 4'b 1111, // index[29] KMAC_KEY_SHARE1_2
- 4'b 1111, // index[30] KMAC_KEY_SHARE1_3
- 4'b 1111, // index[31] KMAC_KEY_SHARE1_4
- 4'b 1111, // index[32] KMAC_KEY_SHARE1_5
- 4'b 1111, // index[33] KMAC_KEY_SHARE1_6
- 4'b 1111, // index[34] KMAC_KEY_SHARE1_7
- 4'b 1111, // index[35] KMAC_KEY_SHARE1_8
- 4'b 1111, // index[36] KMAC_KEY_SHARE1_9
- 4'b 1111, // index[37] KMAC_KEY_SHARE1_10
- 4'b 1111, // index[38] KMAC_KEY_SHARE1_11
- 4'b 1111, // index[39] KMAC_KEY_SHARE1_12
- 4'b 1111, // index[40] KMAC_KEY_SHARE1_13
- 4'b 1111, // index[41] KMAC_KEY_SHARE1_14
- 4'b 1111, // index[42] KMAC_KEY_SHARE1_15
- 4'b 0001, // index[43] KMAC_KEY_LEN
- 4'b 1111, // index[44] KMAC_PREFIX_0
- 4'b 1111, // index[45] KMAC_PREFIX_1
- 4'b 1111, // index[46] KMAC_PREFIX_2
- 4'b 1111, // index[47] KMAC_PREFIX_3
- 4'b 1111, // index[48] KMAC_PREFIX_4
- 4'b 1111, // index[49] KMAC_PREFIX_5
- 4'b 1111, // index[50] KMAC_PREFIX_6
- 4'b 1111, // index[51] KMAC_PREFIX_7
- 4'b 1111, // index[52] KMAC_PREFIX_8
- 4'b 1111, // index[53] KMAC_PREFIX_9
- 4'b 1111, // index[54] KMAC_PREFIX_10
- 4'b 1111 // index[55] KMAC_ERR_CODE
+ 4'b 1111, // index[ 9] KMAC_ENTROPY_REFRESH
+ 4'b 1111, // index[10] KMAC_ENTROPY_SEED_LOWER
+ 4'b 1111, // index[11] KMAC_ENTROPY_SEED_UPPER
+ 4'b 1111, // index[12] KMAC_KEY_SHARE0_0
+ 4'b 1111, // index[13] KMAC_KEY_SHARE0_1
+ 4'b 1111, // index[14] KMAC_KEY_SHARE0_2
+ 4'b 1111, // index[15] KMAC_KEY_SHARE0_3
+ 4'b 1111, // index[16] KMAC_KEY_SHARE0_4
+ 4'b 1111, // index[17] KMAC_KEY_SHARE0_5
+ 4'b 1111, // index[18] KMAC_KEY_SHARE0_6
+ 4'b 1111, // index[19] KMAC_KEY_SHARE0_7
+ 4'b 1111, // index[20] KMAC_KEY_SHARE0_8
+ 4'b 1111, // index[21] KMAC_KEY_SHARE0_9
+ 4'b 1111, // index[22] KMAC_KEY_SHARE0_10
+ 4'b 1111, // index[23] KMAC_KEY_SHARE0_11
+ 4'b 1111, // index[24] KMAC_KEY_SHARE0_12
+ 4'b 1111, // index[25] KMAC_KEY_SHARE0_13
+ 4'b 1111, // index[26] KMAC_KEY_SHARE0_14
+ 4'b 1111, // index[27] KMAC_KEY_SHARE0_15
+ 4'b 1111, // index[28] KMAC_KEY_SHARE1_0
+ 4'b 1111, // index[29] KMAC_KEY_SHARE1_1
+ 4'b 1111, // index[30] KMAC_KEY_SHARE1_2
+ 4'b 1111, // index[31] KMAC_KEY_SHARE1_3
+ 4'b 1111, // index[32] KMAC_KEY_SHARE1_4
+ 4'b 1111, // index[33] KMAC_KEY_SHARE1_5
+ 4'b 1111, // index[34] KMAC_KEY_SHARE1_6
+ 4'b 1111, // index[35] KMAC_KEY_SHARE1_7
+ 4'b 1111, // index[36] KMAC_KEY_SHARE1_8
+ 4'b 1111, // index[37] KMAC_KEY_SHARE1_9
+ 4'b 1111, // index[38] KMAC_KEY_SHARE1_10
+ 4'b 1111, // index[39] KMAC_KEY_SHARE1_11
+ 4'b 1111, // index[40] KMAC_KEY_SHARE1_12
+ 4'b 1111, // index[41] KMAC_KEY_SHARE1_13
+ 4'b 1111, // index[42] KMAC_KEY_SHARE1_14
+ 4'b 1111, // index[43] KMAC_KEY_SHARE1_15
+ 4'b 0001, // index[44] KMAC_KEY_LEN
+ 4'b 1111, // index[45] KMAC_PREFIX_0
+ 4'b 1111, // index[46] KMAC_PREFIX_1
+ 4'b 1111, // index[47] KMAC_PREFIX_2
+ 4'b 1111, // index[48] KMAC_PREFIX_3
+ 4'b 1111, // index[49] KMAC_PREFIX_4
+ 4'b 1111, // index[50] KMAC_PREFIX_5
+ 4'b 1111, // index[51] KMAC_PREFIX_6
+ 4'b 1111, // index[52] KMAC_PREFIX_7
+ 4'b 1111, // index[53] KMAC_PREFIX_8
+ 4'b 1111, // index[54] KMAC_PREFIX_9
+ 4'b 1111, // index[55] KMAC_PREFIX_10
+ 4'b 1111 // index[56] KMAC_ERR_CODE
};
endpackage
diff --git a/hw/ip/kmac/rtl/kmac_reg_top.sv b/hw/ip/kmac/rtl/kmac_reg_top.sv
index a1f6f8c..780c5fd 100644
--- a/hw/ip/kmac/rtl/kmac_reg_top.sv
+++ b/hw/ip/kmac/rtl/kmac_reg_top.sv
@@ -201,7 +201,9 @@
logic cfg_err_processed_qs;
logic cfg_err_processed_wd;
logic cmd_we;
- logic [3:0] cmd_wd;
+ logic [3:0] cmd_cmd_wd;
+ logic cmd_entropy_req_wd;
+ logic cmd_hash_cnt_clr_wd;
logic status_re;
logic status_sha3_idle_qs;
logic status_sha3_absorb_qs;
@@ -210,10 +212,14 @@
logic status_fifo_empty_qs;
logic status_fifo_full_qs;
logic entropy_period_we;
- logic [15:0] entropy_period_entropy_timer_qs;
- logic [15:0] entropy_period_entropy_timer_wd;
+ logic [9:0] entropy_period_prescaler_qs;
+ logic [9:0] entropy_period_prescaler_wd;
logic [15:0] entropy_period_wait_timer_qs;
logic [15:0] entropy_period_wait_timer_wd;
+ logic entropy_refresh_we;
+ logic [9:0] entropy_refresh_threshold_qs;
+ logic [9:0] entropy_refresh_threshold_wd;
+ logic [9:0] entropy_refresh_hash_cnt_qs;
logic entropy_seed_lower_we;
logic [31:0] entropy_seed_lower_qs;
logic [31:0] entropy_seed_lower_wd;
@@ -825,16 +831,47 @@
// R[cmd]: V(True)
+ // F[cmd]: 3:0
prim_subreg_ext #(
.DW (4)
- ) u_cmd (
+ ) u_cmd_cmd (
.re (1'b0),
.we (cmd_we),
- .wd (cmd_wd),
+ .wd (cmd_cmd_wd),
.d ('0),
.qre (),
- .qe (reg2hw.cmd.qe),
- .q (reg2hw.cmd.q),
+ .qe (reg2hw.cmd.cmd.qe),
+ .q (reg2hw.cmd.cmd.q),
+ .qs ()
+ );
+
+
+ // F[entropy_req]: 8:8
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cmd_entropy_req (
+ .re (1'b0),
+ .we (cmd_we),
+ .wd (cmd_entropy_req_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.cmd.entropy_req.qe),
+ .q (reg2hw.cmd.entropy_req.q),
+ .qs ()
+ );
+
+
+ // F[hash_cnt_clr]: 9:9
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_cmd_hash_cnt_clr (
+ .re (1'b0),
+ .we (cmd_we),
+ .wd (cmd_hash_cnt_clr_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.cmd.hash_cnt_clr.qe),
+ .q (reg2hw.cmd.hash_cnt_clr.q),
.qs ()
);
@@ -933,18 +970,18 @@
// R[entropy_period]: V(False)
- // F[entropy_timer]: 15:0
+ // F[prescaler]: 9:0
prim_subreg #(
- .DW (16),
+ .DW (10),
.SWACCESS("RW"),
- .RESVAL (16'h0)
- ) u_entropy_period_entropy_timer (
+ .RESVAL (10'h0)
+ ) u_entropy_period_prescaler (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (entropy_period_we & cfg_regwen_qs),
- .wd (entropy_period_entropy_timer_wd),
+ .wd (entropy_period_prescaler_wd),
// from internal hardware
.de (1'b0),
@@ -952,10 +989,10 @@
// to internal hardware
.qe (),
- .q (reg2hw.entropy_period.entropy_timer.q),
+ .q (reg2hw.entropy_period.prescaler.q),
// to register interface (read)
- .qs (entropy_period_entropy_timer_qs)
+ .qs (entropy_period_prescaler_qs)
);
@@ -985,6 +1022,60 @@
);
+ // R[entropy_refresh]: V(False)
+
+ // F[threshold]: 9:0
+ prim_subreg #(
+ .DW (10),
+ .SWACCESS("RW"),
+ .RESVAL (10'h0)
+ ) u_entropy_refresh_threshold (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (entropy_refresh_we & cfg_regwen_qs),
+ .wd (entropy_refresh_threshold_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.entropy_refresh.threshold.q),
+
+ // to register interface (read)
+ .qs (entropy_refresh_threshold_qs)
+ );
+
+
+ // F[hash_cnt]: 25:16
+ prim_subreg #(
+ .DW (10),
+ .SWACCESS("RO"),
+ .RESVAL (10'h0)
+ ) u_entropy_refresh_hash_cnt (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.entropy_refresh.hash_cnt.de),
+ .d (hw2reg.entropy_refresh.hash_cnt.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (entropy_refresh_hash_cnt_qs)
+ );
+
+
// R[entropy_seed_lower]: V(False)
prim_subreg #(
@@ -1910,7 +2001,7 @@
- logic [55:0] addr_hit;
+ logic [56:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == KMAC_INTR_STATE_OFFSET);
@@ -1922,53 +2013,54 @@
addr_hit[ 6] = (reg_addr == KMAC_CMD_OFFSET);
addr_hit[ 7] = (reg_addr == KMAC_STATUS_OFFSET);
addr_hit[ 8] = (reg_addr == KMAC_ENTROPY_PERIOD_OFFSET);
- addr_hit[ 9] = (reg_addr == KMAC_ENTROPY_SEED_LOWER_OFFSET);
- addr_hit[10] = (reg_addr == KMAC_ENTROPY_SEED_UPPER_OFFSET);
- addr_hit[11] = (reg_addr == KMAC_KEY_SHARE0_0_OFFSET);
- addr_hit[12] = (reg_addr == KMAC_KEY_SHARE0_1_OFFSET);
- addr_hit[13] = (reg_addr == KMAC_KEY_SHARE0_2_OFFSET);
- addr_hit[14] = (reg_addr == KMAC_KEY_SHARE0_3_OFFSET);
- addr_hit[15] = (reg_addr == KMAC_KEY_SHARE0_4_OFFSET);
- addr_hit[16] = (reg_addr == KMAC_KEY_SHARE0_5_OFFSET);
- addr_hit[17] = (reg_addr == KMAC_KEY_SHARE0_6_OFFSET);
- addr_hit[18] = (reg_addr == KMAC_KEY_SHARE0_7_OFFSET);
- addr_hit[19] = (reg_addr == KMAC_KEY_SHARE0_8_OFFSET);
- addr_hit[20] = (reg_addr == KMAC_KEY_SHARE0_9_OFFSET);
- addr_hit[21] = (reg_addr == KMAC_KEY_SHARE0_10_OFFSET);
- addr_hit[22] = (reg_addr == KMAC_KEY_SHARE0_11_OFFSET);
- addr_hit[23] = (reg_addr == KMAC_KEY_SHARE0_12_OFFSET);
- addr_hit[24] = (reg_addr == KMAC_KEY_SHARE0_13_OFFSET);
- addr_hit[25] = (reg_addr == KMAC_KEY_SHARE0_14_OFFSET);
- addr_hit[26] = (reg_addr == KMAC_KEY_SHARE0_15_OFFSET);
- addr_hit[27] = (reg_addr == KMAC_KEY_SHARE1_0_OFFSET);
- addr_hit[28] = (reg_addr == KMAC_KEY_SHARE1_1_OFFSET);
- addr_hit[29] = (reg_addr == KMAC_KEY_SHARE1_2_OFFSET);
- addr_hit[30] = (reg_addr == KMAC_KEY_SHARE1_3_OFFSET);
- addr_hit[31] = (reg_addr == KMAC_KEY_SHARE1_4_OFFSET);
- addr_hit[32] = (reg_addr == KMAC_KEY_SHARE1_5_OFFSET);
- addr_hit[33] = (reg_addr == KMAC_KEY_SHARE1_6_OFFSET);
- addr_hit[34] = (reg_addr == KMAC_KEY_SHARE1_7_OFFSET);
- addr_hit[35] = (reg_addr == KMAC_KEY_SHARE1_8_OFFSET);
- addr_hit[36] = (reg_addr == KMAC_KEY_SHARE1_9_OFFSET);
- addr_hit[37] = (reg_addr == KMAC_KEY_SHARE1_10_OFFSET);
- addr_hit[38] = (reg_addr == KMAC_KEY_SHARE1_11_OFFSET);
- addr_hit[39] = (reg_addr == KMAC_KEY_SHARE1_12_OFFSET);
- addr_hit[40] = (reg_addr == KMAC_KEY_SHARE1_13_OFFSET);
- addr_hit[41] = (reg_addr == KMAC_KEY_SHARE1_14_OFFSET);
- addr_hit[42] = (reg_addr == KMAC_KEY_SHARE1_15_OFFSET);
- addr_hit[43] = (reg_addr == KMAC_KEY_LEN_OFFSET);
- addr_hit[44] = (reg_addr == KMAC_PREFIX_0_OFFSET);
- addr_hit[45] = (reg_addr == KMAC_PREFIX_1_OFFSET);
- addr_hit[46] = (reg_addr == KMAC_PREFIX_2_OFFSET);
- addr_hit[47] = (reg_addr == KMAC_PREFIX_3_OFFSET);
- addr_hit[48] = (reg_addr == KMAC_PREFIX_4_OFFSET);
- addr_hit[49] = (reg_addr == KMAC_PREFIX_5_OFFSET);
- addr_hit[50] = (reg_addr == KMAC_PREFIX_6_OFFSET);
- addr_hit[51] = (reg_addr == KMAC_PREFIX_7_OFFSET);
- addr_hit[52] = (reg_addr == KMAC_PREFIX_8_OFFSET);
- addr_hit[53] = (reg_addr == KMAC_PREFIX_9_OFFSET);
- addr_hit[54] = (reg_addr == KMAC_PREFIX_10_OFFSET);
- addr_hit[55] = (reg_addr == KMAC_ERR_CODE_OFFSET);
+ addr_hit[ 9] = (reg_addr == KMAC_ENTROPY_REFRESH_OFFSET);
+ addr_hit[10] = (reg_addr == KMAC_ENTROPY_SEED_LOWER_OFFSET);
+ addr_hit[11] = (reg_addr == KMAC_ENTROPY_SEED_UPPER_OFFSET);
+ addr_hit[12] = (reg_addr == KMAC_KEY_SHARE0_0_OFFSET);
+ addr_hit[13] = (reg_addr == KMAC_KEY_SHARE0_1_OFFSET);
+ addr_hit[14] = (reg_addr == KMAC_KEY_SHARE0_2_OFFSET);
+ addr_hit[15] = (reg_addr == KMAC_KEY_SHARE0_3_OFFSET);
+ addr_hit[16] = (reg_addr == KMAC_KEY_SHARE0_4_OFFSET);
+ addr_hit[17] = (reg_addr == KMAC_KEY_SHARE0_5_OFFSET);
+ addr_hit[18] = (reg_addr == KMAC_KEY_SHARE0_6_OFFSET);
+ addr_hit[19] = (reg_addr == KMAC_KEY_SHARE0_7_OFFSET);
+ addr_hit[20] = (reg_addr == KMAC_KEY_SHARE0_8_OFFSET);
+ addr_hit[21] = (reg_addr == KMAC_KEY_SHARE0_9_OFFSET);
+ addr_hit[22] = (reg_addr == KMAC_KEY_SHARE0_10_OFFSET);
+ addr_hit[23] = (reg_addr == KMAC_KEY_SHARE0_11_OFFSET);
+ addr_hit[24] = (reg_addr == KMAC_KEY_SHARE0_12_OFFSET);
+ addr_hit[25] = (reg_addr == KMAC_KEY_SHARE0_13_OFFSET);
+ addr_hit[26] = (reg_addr == KMAC_KEY_SHARE0_14_OFFSET);
+ addr_hit[27] = (reg_addr == KMAC_KEY_SHARE0_15_OFFSET);
+ addr_hit[28] = (reg_addr == KMAC_KEY_SHARE1_0_OFFSET);
+ addr_hit[29] = (reg_addr == KMAC_KEY_SHARE1_1_OFFSET);
+ addr_hit[30] = (reg_addr == KMAC_KEY_SHARE1_2_OFFSET);
+ addr_hit[31] = (reg_addr == KMAC_KEY_SHARE1_3_OFFSET);
+ addr_hit[32] = (reg_addr == KMAC_KEY_SHARE1_4_OFFSET);
+ addr_hit[33] = (reg_addr == KMAC_KEY_SHARE1_5_OFFSET);
+ addr_hit[34] = (reg_addr == KMAC_KEY_SHARE1_6_OFFSET);
+ addr_hit[35] = (reg_addr == KMAC_KEY_SHARE1_7_OFFSET);
+ addr_hit[36] = (reg_addr == KMAC_KEY_SHARE1_8_OFFSET);
+ addr_hit[37] = (reg_addr == KMAC_KEY_SHARE1_9_OFFSET);
+ addr_hit[38] = (reg_addr == KMAC_KEY_SHARE1_10_OFFSET);
+ addr_hit[39] = (reg_addr == KMAC_KEY_SHARE1_11_OFFSET);
+ addr_hit[40] = (reg_addr == KMAC_KEY_SHARE1_12_OFFSET);
+ addr_hit[41] = (reg_addr == KMAC_KEY_SHARE1_13_OFFSET);
+ addr_hit[42] = (reg_addr == KMAC_KEY_SHARE1_14_OFFSET);
+ addr_hit[43] = (reg_addr == KMAC_KEY_SHARE1_15_OFFSET);
+ addr_hit[44] = (reg_addr == KMAC_KEY_LEN_OFFSET);
+ addr_hit[45] = (reg_addr == KMAC_PREFIX_0_OFFSET);
+ addr_hit[46] = (reg_addr == KMAC_PREFIX_1_OFFSET);
+ addr_hit[47] = (reg_addr == KMAC_PREFIX_2_OFFSET);
+ addr_hit[48] = (reg_addr == KMAC_PREFIX_3_OFFSET);
+ addr_hit[49] = (reg_addr == KMAC_PREFIX_4_OFFSET);
+ addr_hit[50] = (reg_addr == KMAC_PREFIX_5_OFFSET);
+ addr_hit[51] = (reg_addr == KMAC_PREFIX_6_OFFSET);
+ addr_hit[52] = (reg_addr == KMAC_PREFIX_7_OFFSET);
+ addr_hit[53] = (reg_addr == KMAC_PREFIX_8_OFFSET);
+ addr_hit[54] = (reg_addr == KMAC_PREFIX_9_OFFSET);
+ addr_hit[55] = (reg_addr == KMAC_PREFIX_10_OFFSET);
+ addr_hit[56] = (reg_addr == KMAC_ERR_CODE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -2031,7 +2123,8 @@
(addr_hit[52] & (|(KMAC_PERMIT[52] & ~reg_be))) |
(addr_hit[53] & (|(KMAC_PERMIT[53] & ~reg_be))) |
(addr_hit[54] & (|(KMAC_PERMIT[54] & ~reg_be))) |
- (addr_hit[55] & (|(KMAC_PERMIT[55] & ~reg_be)))));
+ (addr_hit[55] & (|(KMAC_PERMIT[55] & ~reg_be))) |
+ (addr_hit[56] & (|(KMAC_PERMIT[56] & ~reg_be)))));
end
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
@@ -2081,149 +2174,156 @@
assign cfg_err_processed_wd = reg_wdata[25];
assign cmd_we = addr_hit[6] & reg_we & !reg_error;
- assign cmd_wd = reg_wdata[3:0];
+ assign cmd_cmd_wd = reg_wdata[3:0];
+
+ assign cmd_entropy_req_wd = reg_wdata[8];
+
+ assign cmd_hash_cnt_clr_wd = reg_wdata[9];
assign status_re = addr_hit[7] & reg_re & !reg_error;
assign entropy_period_we = addr_hit[8] & reg_we & !reg_error;
- assign entropy_period_entropy_timer_wd = reg_wdata[15:0];
+ assign entropy_period_prescaler_wd = reg_wdata[9:0];
assign entropy_period_wait_timer_wd = reg_wdata[31:16];
- assign entropy_seed_lower_we = addr_hit[9] & reg_we & !reg_error;
+ assign entropy_refresh_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign entropy_refresh_threshold_wd = reg_wdata[9:0];
+ assign entropy_seed_lower_we = addr_hit[10] & reg_we & !reg_error;
assign entropy_seed_lower_wd = reg_wdata[31:0];
- assign entropy_seed_upper_we = addr_hit[10] & reg_we & !reg_error;
+ assign entropy_seed_upper_we = addr_hit[11] & reg_we & !reg_error;
assign entropy_seed_upper_wd = reg_wdata[31:0];
- assign key_share0_0_we = addr_hit[11] & reg_we & !reg_error;
+ assign key_share0_0_we = addr_hit[12] & reg_we & !reg_error;
assign key_share0_0_wd = reg_wdata[31:0];
- assign key_share0_1_we = addr_hit[12] & reg_we & !reg_error;
+ assign key_share0_1_we = addr_hit[13] & reg_we & !reg_error;
assign key_share0_1_wd = reg_wdata[31:0];
- assign key_share0_2_we = addr_hit[13] & reg_we & !reg_error;
+ assign key_share0_2_we = addr_hit[14] & reg_we & !reg_error;
assign key_share0_2_wd = reg_wdata[31:0];
- assign key_share0_3_we = addr_hit[14] & reg_we & !reg_error;
+ assign key_share0_3_we = addr_hit[15] & reg_we & !reg_error;
assign key_share0_3_wd = reg_wdata[31:0];
- assign key_share0_4_we = addr_hit[15] & reg_we & !reg_error;
+ assign key_share0_4_we = addr_hit[16] & reg_we & !reg_error;
assign key_share0_4_wd = reg_wdata[31:0];
- assign key_share0_5_we = addr_hit[16] & reg_we & !reg_error;
+ assign key_share0_5_we = addr_hit[17] & reg_we & !reg_error;
assign key_share0_5_wd = reg_wdata[31:0];
- assign key_share0_6_we = addr_hit[17] & reg_we & !reg_error;
+ assign key_share0_6_we = addr_hit[18] & reg_we & !reg_error;
assign key_share0_6_wd = reg_wdata[31:0];
- assign key_share0_7_we = addr_hit[18] & reg_we & !reg_error;
+ assign key_share0_7_we = addr_hit[19] & reg_we & !reg_error;
assign key_share0_7_wd = reg_wdata[31:0];
- assign key_share0_8_we = addr_hit[19] & reg_we & !reg_error;
+ assign key_share0_8_we = addr_hit[20] & reg_we & !reg_error;
assign key_share0_8_wd = reg_wdata[31:0];
- assign key_share0_9_we = addr_hit[20] & reg_we & !reg_error;
+ assign key_share0_9_we = addr_hit[21] & reg_we & !reg_error;
assign key_share0_9_wd = reg_wdata[31:0];
- assign key_share0_10_we = addr_hit[21] & reg_we & !reg_error;
+ assign key_share0_10_we = addr_hit[22] & reg_we & !reg_error;
assign key_share0_10_wd = reg_wdata[31:0];
- assign key_share0_11_we = addr_hit[22] & reg_we & !reg_error;
+ assign key_share0_11_we = addr_hit[23] & reg_we & !reg_error;
assign key_share0_11_wd = reg_wdata[31:0];
- assign key_share0_12_we = addr_hit[23] & reg_we & !reg_error;
+ assign key_share0_12_we = addr_hit[24] & reg_we & !reg_error;
assign key_share0_12_wd = reg_wdata[31:0];
- assign key_share0_13_we = addr_hit[24] & reg_we & !reg_error;
+ assign key_share0_13_we = addr_hit[25] & reg_we & !reg_error;
assign key_share0_13_wd = reg_wdata[31:0];
- assign key_share0_14_we = addr_hit[25] & reg_we & !reg_error;
+ assign key_share0_14_we = addr_hit[26] & reg_we & !reg_error;
assign key_share0_14_wd = reg_wdata[31:0];
- assign key_share0_15_we = addr_hit[26] & reg_we & !reg_error;
+ assign key_share0_15_we = addr_hit[27] & reg_we & !reg_error;
assign key_share0_15_wd = reg_wdata[31:0];
- assign key_share1_0_we = addr_hit[27] & reg_we & !reg_error;
+ assign key_share1_0_we = addr_hit[28] & reg_we & !reg_error;
assign key_share1_0_wd = reg_wdata[31:0];
- assign key_share1_1_we = addr_hit[28] & reg_we & !reg_error;
+ assign key_share1_1_we = addr_hit[29] & reg_we & !reg_error;
assign key_share1_1_wd = reg_wdata[31:0];
- assign key_share1_2_we = addr_hit[29] & reg_we & !reg_error;
+ assign key_share1_2_we = addr_hit[30] & reg_we & !reg_error;
assign key_share1_2_wd = reg_wdata[31:0];
- assign key_share1_3_we = addr_hit[30] & reg_we & !reg_error;
+ assign key_share1_3_we = addr_hit[31] & reg_we & !reg_error;
assign key_share1_3_wd = reg_wdata[31:0];
- assign key_share1_4_we = addr_hit[31] & reg_we & !reg_error;
+ assign key_share1_4_we = addr_hit[32] & reg_we & !reg_error;
assign key_share1_4_wd = reg_wdata[31:0];
- assign key_share1_5_we = addr_hit[32] & reg_we & !reg_error;
+ assign key_share1_5_we = addr_hit[33] & reg_we & !reg_error;
assign key_share1_5_wd = reg_wdata[31:0];
- assign key_share1_6_we = addr_hit[33] & reg_we & !reg_error;
+ assign key_share1_6_we = addr_hit[34] & reg_we & !reg_error;
assign key_share1_6_wd = reg_wdata[31:0];
- assign key_share1_7_we = addr_hit[34] & reg_we & !reg_error;
+ assign key_share1_7_we = addr_hit[35] & reg_we & !reg_error;
assign key_share1_7_wd = reg_wdata[31:0];
- assign key_share1_8_we = addr_hit[35] & reg_we & !reg_error;
+ assign key_share1_8_we = addr_hit[36] & reg_we & !reg_error;
assign key_share1_8_wd = reg_wdata[31:0];
- assign key_share1_9_we = addr_hit[36] & reg_we & !reg_error;
+ assign key_share1_9_we = addr_hit[37] & reg_we & !reg_error;
assign key_share1_9_wd = reg_wdata[31:0];
- assign key_share1_10_we = addr_hit[37] & reg_we & !reg_error;
+ assign key_share1_10_we = addr_hit[38] & reg_we & !reg_error;
assign key_share1_10_wd = reg_wdata[31:0];
- assign key_share1_11_we = addr_hit[38] & reg_we & !reg_error;
+ assign key_share1_11_we = addr_hit[39] & reg_we & !reg_error;
assign key_share1_11_wd = reg_wdata[31:0];
- assign key_share1_12_we = addr_hit[39] & reg_we & !reg_error;
+ assign key_share1_12_we = addr_hit[40] & reg_we & !reg_error;
assign key_share1_12_wd = reg_wdata[31:0];
- assign key_share1_13_we = addr_hit[40] & reg_we & !reg_error;
+ assign key_share1_13_we = addr_hit[41] & reg_we & !reg_error;
assign key_share1_13_wd = reg_wdata[31:0];
- assign key_share1_14_we = addr_hit[41] & reg_we & !reg_error;
+ assign key_share1_14_we = addr_hit[42] & reg_we & !reg_error;
assign key_share1_14_wd = reg_wdata[31:0];
- assign key_share1_15_we = addr_hit[42] & reg_we & !reg_error;
+ assign key_share1_15_we = addr_hit[43] & reg_we & !reg_error;
assign key_share1_15_wd = reg_wdata[31:0];
- assign key_len_we = addr_hit[43] & reg_we & !reg_error;
+ assign key_len_we = addr_hit[44] & reg_we & !reg_error;
assign key_len_wd = reg_wdata[2:0];
- assign prefix_0_we = addr_hit[44] & reg_we & !reg_error;
+ assign prefix_0_we = addr_hit[45] & reg_we & !reg_error;
assign prefix_0_wd = reg_wdata[31:0];
- assign prefix_1_we = addr_hit[45] & reg_we & !reg_error;
+ assign prefix_1_we = addr_hit[46] & reg_we & !reg_error;
assign prefix_1_wd = reg_wdata[31:0];
- assign prefix_2_we = addr_hit[46] & reg_we & !reg_error;
+ assign prefix_2_we = addr_hit[47] & reg_we & !reg_error;
assign prefix_2_wd = reg_wdata[31:0];
- assign prefix_3_we = addr_hit[47] & reg_we & !reg_error;
+ assign prefix_3_we = addr_hit[48] & reg_we & !reg_error;
assign prefix_3_wd = reg_wdata[31:0];
- assign prefix_4_we = addr_hit[48] & reg_we & !reg_error;
+ assign prefix_4_we = addr_hit[49] & reg_we & !reg_error;
assign prefix_4_wd = reg_wdata[31:0];
- assign prefix_5_we = addr_hit[49] & reg_we & !reg_error;
+ assign prefix_5_we = addr_hit[50] & reg_we & !reg_error;
assign prefix_5_wd = reg_wdata[31:0];
- assign prefix_6_we = addr_hit[50] & reg_we & !reg_error;
+ assign prefix_6_we = addr_hit[51] & reg_we & !reg_error;
assign prefix_6_wd = reg_wdata[31:0];
- assign prefix_7_we = addr_hit[51] & reg_we & !reg_error;
+ assign prefix_7_we = addr_hit[52] & reg_we & !reg_error;
assign prefix_7_wd = reg_wdata[31:0];
- assign prefix_8_we = addr_hit[52] & reg_we & !reg_error;
+ assign prefix_8_we = addr_hit[53] & reg_we & !reg_error;
assign prefix_8_wd = reg_wdata[31:0];
- assign prefix_9_we = addr_hit[53] & reg_we & !reg_error;
+ assign prefix_9_we = addr_hit[54] & reg_we & !reg_error;
assign prefix_9_wd = reg_wdata[31:0];
- assign prefix_10_we = addr_hit[54] & reg_we & !reg_error;
+ assign prefix_10_we = addr_hit[55] & reg_we & !reg_error;
assign prefix_10_wd = reg_wdata[31:0];
@@ -2272,6 +2372,8 @@
addr_hit[6]: begin
reg_rdata_next[3:0] = '0;
+ reg_rdata_next[8] = '0;
+ reg_rdata_next[9] = '0;
end
addr_hit[7]: begin
@@ -2284,20 +2386,21 @@
end
addr_hit[8]: begin
- reg_rdata_next[15:0] = entropy_period_entropy_timer_qs;
+ reg_rdata_next[9:0] = entropy_period_prescaler_qs;
reg_rdata_next[31:16] = entropy_period_wait_timer_qs;
end
addr_hit[9]: begin
- reg_rdata_next[31:0] = entropy_seed_lower_qs;
+ reg_rdata_next[9:0] = entropy_refresh_threshold_qs;
+ reg_rdata_next[25:16] = entropy_refresh_hash_cnt_qs;
end
addr_hit[10]: begin
- reg_rdata_next[31:0] = entropy_seed_upper_qs;
+ reg_rdata_next[31:0] = entropy_seed_lower_qs;
end
addr_hit[11]: begin
- reg_rdata_next[31:0] = '0;
+ reg_rdata_next[31:0] = entropy_seed_upper_qs;
end
addr_hit[12]: begin
@@ -2425,54 +2528,58 @@
end
addr_hit[43]: begin
- reg_rdata_next[2:0] = '0;
+ reg_rdata_next[31:0] = '0;
end
addr_hit[44]: begin
- reg_rdata_next[31:0] = prefix_0_qs;
+ reg_rdata_next[2:0] = '0;
end
addr_hit[45]: begin
- reg_rdata_next[31:0] = prefix_1_qs;
+ reg_rdata_next[31:0] = prefix_0_qs;
end
addr_hit[46]: begin
- reg_rdata_next[31:0] = prefix_2_qs;
+ reg_rdata_next[31:0] = prefix_1_qs;
end
addr_hit[47]: begin
- reg_rdata_next[31:0] = prefix_3_qs;
+ reg_rdata_next[31:0] = prefix_2_qs;
end
addr_hit[48]: begin
- reg_rdata_next[31:0] = prefix_4_qs;
+ reg_rdata_next[31:0] = prefix_3_qs;
end
addr_hit[49]: begin
- reg_rdata_next[31:0] = prefix_5_qs;
+ reg_rdata_next[31:0] = prefix_4_qs;
end
addr_hit[50]: begin
- reg_rdata_next[31:0] = prefix_6_qs;
+ reg_rdata_next[31:0] = prefix_5_qs;
end
addr_hit[51]: begin
- reg_rdata_next[31:0] = prefix_7_qs;
+ reg_rdata_next[31:0] = prefix_6_qs;
end
addr_hit[52]: begin
- reg_rdata_next[31:0] = prefix_8_qs;
+ reg_rdata_next[31:0] = prefix_7_qs;
end
addr_hit[53]: begin
- reg_rdata_next[31:0] = prefix_9_qs;
+ reg_rdata_next[31:0] = prefix_8_qs;
end
addr_hit[54]: begin
- reg_rdata_next[31:0] = prefix_10_qs;
+ reg_rdata_next[31:0] = prefix_9_qs;
end
addr_hit[55]: begin
+ reg_rdata_next[31:0] = prefix_10_qs;
+ end
+
+ addr_hit[56]: begin
reg_rdata_next[31:0] = err_code_qs;
end
diff --git a/sw/device/lib/dif/dif_kmac.c b/sw/device/lib/dif/dif_kmac.c
index 420fc92..271e1d1 100644
--- a/sw/device/lib/dif/dif_kmac.c
+++ b/sw/device/lib/dif/dif_kmac.c
@@ -195,9 +195,6 @@
// Write entropy period register.
uint32_t entropy_period_reg = 0;
entropy_period_reg = bitfield_field32_write(
- entropy_period_reg, KMAC_ENTROPY_PERIOD_ENTROPY_TIMER_FIELD,
- config.entropy_reseed_interval);
- entropy_period_reg = bitfield_field32_write(
entropy_period_reg, KMAC_ENTROPY_PERIOD_WAIT_TIMER_FIELD,
config.entropy_wait_timer);
mmio_region_write32(kmac->params.base_addr, KMAC_ENTROPY_PERIOD_REG_OFFSET,
