| commit | f0f26143919c164df14f7f0f38f8aa28d182dbf6 | [log] [tgz] |
|---|---|---|
| author | Weicai Yang <weicai@google.com> | Wed Dec 08 16:49:13 2021 -0800 |
| committer | weicaiyang <49293026+weicaiyang@users.noreply.github.com> | Thu Dec 09 12:23:04 2021 -0800 |
| tree | 131393a07525c137d1b07cd3e4af1db2c0d07049 | |
| parent | febe0be9a5e87f390d3d5a0cfd9ed3210cebca9c [diff] |
[sram/dv] Better support partial write in scb 1. after design removes the temporary workaround, the write timing can be more compact. We may see write_start -> write_start -> write_finish -> write_finish. Use a queue to process write_finsh one by one 2. add address decrypt function and once comparing the write data with backdoor value, also decode the internal address and check it matches to the item address. 3. Enable scb for mem_walk and mem_partial_access Signed-off-by: Weicai Yang <weicai@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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