commit f0a3019decf9163ee81d5f7fbdbad2520aaf03ca
author Greg Chadwick <gac@lowrisc.org> Thu Aug 19 09:33:25 2021 +0100
committer Greg Chadwick <mail@gregchadwick.co.uk> Mon Aug 23 15:00:53 2021 +0100
tree 18c2dd1089bf542f13b92aa0e3c67c453b4d797a
parent e8620dc24cbaaaeb413a79793e1167c4af62905e

[otbn] Implement illegal bus access error & alert

Any time the bus tries to access the OTBN memories whilst OTBN is active
a fatal alert is triggered and OTBN halts immediately indicating an
error.

Fixes #7470
Fixes #2696

Signed-off-by: Greg Chadwick <gac@lowrisc.org>

hw/ip/otbn/rtl/otbn_controller.sv

diff --git a/hw/ip/otbn/rtl/otbn_controller.sv b/hw/ip/otbn/rtl/otbn_controller.sv
index 4a82992..f5ee02a 100644
--- a/hw/ip/otbn/rtl/otbn_controller.sv
+++ b/hw/ip/otbn/rtl/otbn_controller.sv
@@ -124,7 +124,8 @@
   input  logic rnd_valid_i,
 
   input  logic        state_reset_i,
-  output logic [31:0] insn_cnt_o
+  output logic [31:0] insn_cnt_o,
+  input  logic        illegal_bus_access_i
 );
   otbn_state_e state_q, state_d, state_raw;
 
@@ -326,7 +327,7 @@
     end
   end
 
-  assign err_bits_o.fatal_illegal_bus_access = 1'b0; // TODO: implement
+  assign err_bits_o.fatal_illegal_bus_access = illegal_bus_access_i;
   assign err_bits_o.fatal_reg                = rf_base_rd_data_err_i | rf_bignum_rd_data_err_i;
   assign err_bits_o.fatal_imem               = insn_fetch_err_i;
   assign err_bits_o.fatal_dmem               = lsu_rdata_err_i;