| commit | 48731249776f9493ade0bc65653d91201afaf775 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Tue Sep 07 16:58:07 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Fri Sep 10 15:59:50 2021 +0100 |
| tree | b16cc087a339691e9937ce209edabc2138418bfa | |
| parent | cb8a47e5265a8ce771617041f8ecdfb88d4b570b [diff] |
[otbn] Make termination on underflowing x1 more explicit in ISS This will cause slight changes to instruction behaviour in cases where we might have seen multiple errors. Until now, we haven't been testing this against the RTL, so we can probably assume we're switching one set of mismatches for another(!). But now we are more explicit about what's going on, which is probably helpful in the documentation. What's more, we can now model things like "if I do an LW that loads from x1 and underflows, I shouldn't see an error caused by an invalid address" Note that, while we handle CALL_STACK errors on underflow in insn.py, we still need the GPRs.err_bits() method in order to handle overflow properly. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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