[otp_ctrl] Provision power sequencing signals
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv
index 3975921..8f35715 100644
--- a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv
+++ b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv
@@ -27,9 +27,13 @@
32'd16, 32'd14, 32'd23, 32'd07, 32'd30, 32'd09, 32'd18, 32'd36
}
) (
+ // TODO: implement clock muxing for initial programming.
+ // TODO: check whether interfaces need asynchronous transitions.
input clk_i,
input rst_ni,
- // TODO: signals to AST
+ // Macro-specific power sequencing signals to/from AST.
+ output otp_ast_req_t otp_ast_pwr_seq_o,
+ input otp_ast_rsp_t otp_ast_pwr_seq_i,
// Bus Interface (device)
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
@@ -388,12 +392,13 @@
prim_otp #(
.Width(OtpWidth),
- .Depth(OtpDepth),
- .CmdWidth(OtpCmdWidth),
- .ErrWidth(OtpErrWidth)
+ .Depth(OtpDepth)
) u_otp (
.clk_i,
.rst_ni,
+ // Power sequencing signals to/from AST
+ .pwr_seq_o ( otp_ast_pwr_seq_o.pwr_seq ),
+ .pwr_seq_h_i ( otp_ast_pwr_seq_i.pwr_seq_h ),
// Test interface
.test_tl_i ( tl_win_h2d_gated ),
.test_tl_o ( tl_win_d2h_gated ),
diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl_pkg.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl_pkg.sv
index 1a71054..facc70e 100644
--- a/hw/ip/otp_ctrl/rtl/otp_ctrl_pkg.sv
+++ b/hw/ip/otp_ctrl/rtl/otp_ctrl_pkg.sv
@@ -50,6 +50,7 @@
parameter int OtpCmdWidth = 2;
parameter int OtpSizeWidth = 2; // Allows to transfer up to 4 native OTP words at once.
parameter int OtpErrWidth = 4;
+ parameter int OtpPwrSeqWidth = 2;
parameter int OtpIfWidth = 2**OtpSizeWidth*OtpWidth;
// Number of Byte address bits to cut off in order to get the native OTP word address.
parameter int OtpAddrShift = OtpByteAddrWidth - OtpAddrWidth;
@@ -350,9 +351,6 @@
} otbn_otp_key_rsp_t;
-
-
-
////////////////////////////////
// Power/Reset Ctrl Interface //
////////////////////////////////
@@ -369,6 +367,19 @@
logic idle;
} otp_pwr_state_t;
+
+ ///////////////////
+ // AST Interface //
+ ///////////////////
+
+ typedef struct packed {
+ logic [OtpPwrSeqWidth-1:0] pwr_seq;
+ } otp_ast_req_t;
+
+ typedef struct packed {
+ logic [OtpPwrSeqWidth-1:0] pwr_seq_h;
+ } otp_ast_rsp_t;
+
endpackage : otp_ctrl_pkg
diff --git a/hw/ip/prim_generic/rtl/prim_generic_otp.sv b/hw/ip/prim_generic/rtl/prim_generic_otp.sv
index aef12db..1eeb8b5 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_otp.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_otp.sv
@@ -9,30 +9,35 @@
parameter int CmdWidth = otp_ctrl_pkg::OtpCmdWidth,
// This determines the maximum number of native words that
// can be transferred accross the interface in one cycle.
- parameter int SizeWidth = 2,
+ parameter int SizeWidth = otp_ctrl_pkg::OtpSizeWidth,
parameter int ErrWidth = otp_ctrl_pkg::OtpErrWidth,
+ // Width of the power sequencing signal.
+ parameter int PwrSeqWidth = otp_ctrl_pkg::OtpPwrSeqWidth,
+ // Derived parameters
localparam int AddrWidth = prim_util_pkg::vbits(Depth),
localparam int IfWidth = 2**SizeWidth*Width,
// VMEM file to initialize the memory with
parameter MemInitFile = ""
) (
- input clk_i,
- input rst_ni,
- // TODO: power sequencing signals from/to AST
+ input clk_i,
+ input rst_ni,
+ // Macro-specific power sequencing signals to/from AST
+ output logic [PwrSeqWidth-1:0] pwr_seq_o,
+ input [PwrSeqWidth-1:0] pwr_seq_h_i,
// Test interface
- input tlul_pkg::tl_h2d_t test_tl_i,
- output tlul_pkg::tl_d2h_t test_tl_o,
+ input tlul_pkg::tl_h2d_t test_tl_i,
+ output tlul_pkg::tl_d2h_t test_tl_o,
// Ready valid handshake for read/write command
- output logic ready_o,
- input valid_i,
- input [SizeWidth-1:0] size_i, // #(Native words)-1, e.g. size == 0 for 1 native word.
- input [CmdWidth-1:0] cmd_i, // 00: read command, 01: write command, 11: init command
- input [AddrWidth-1:0] addr_i,
- input [IfWidth-1:0] wdata_i,
+ output logic ready_o,
+ input valid_i,
+ input [SizeWidth-1:0] size_i, // #(Native words)-1, e.g. size == 0 for 1 native word.
+ input [CmdWidth-1:0] cmd_i, // 00: read command, 01: write command, 11: init command
+ input [AddrWidth-1:0] addr_i,
+ input [IfWidth-1:0] wdata_i,
// Response channel
- output logic valid_o,
- output logic [IfWidth-1:0] rdata_o,
- output logic [ErrWidth-1:0] err_o
+ output logic valid_o,
+ output logic [IfWidth-1:0] rdata_o,
+ output logic [ErrWidth-1:0] err_o
);
// TODO: need a randomized LFSR timer to add some reasonable, non-deterministic response delays.
@@ -42,6 +47,11 @@
assign unused_test_tl = test_tl_i;
assign test_tl_o = '0;
+ // Not supported in open-source emulation model.
+ logic [PwrSeqWidth-1:0] unused_pwr_seq_h;
+ assign unused_pwr_seq_h = pwr_seq_h_i;
+ assign pwr_seq_o = '0;
+
///////////////////
// Control logic //
///////////////////
