[dv] Add support for multiple ral models
- This commit adds support for running the common CSR suite of tests
with multiple RAL models in the testbench
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/dv/sv/cip_lib/cip_base_vseq.sv b/hw/dv/sv/cip_lib/cip_base_vseq.sv
index 8554428..ecf2708 100644
--- a/hw/dv/sv/cip_lib/cip_base_vseq.sv
+++ b/hw/dv/sv/cip_lib/cip_base_vseq.sv
@@ -78,14 +78,15 @@
input bit [TL_DW-1:0] exp_data = 0,
input bit check_exp_data = 1'b0,
input bit [TL_DW-1:0] compare_mask = '1,
- input bit blocking = csr_utils_pkg::default_csr_blocking);
+ input bit blocking = csr_utils_pkg::default_csr_blocking,
+ tl_sequencer tl_sequencer_h = p_sequencer.tl_sequencer_h);
if (blocking) begin
tl_access_sub(addr, write, data, mask, check_rsp, exp_err_rsp, exp_data,
- compare_mask, check_exp_data);
+ compare_mask, check_exp_data, tl_sequencer_h);
end else begin
fork
tl_access_sub(addr, write, data, mask, check_rsp, exp_err_rsp, exp_data,
- compare_mask, check_exp_data);
+ compare_mask, check_exp_data, tl_sequencer_h);
join_none
// Add #0 to ensure that this thread starts executing before any subsequent call
#0;
@@ -100,11 +101,12 @@
input bit exp_err_rsp = 1'b0,
input bit [TL_DW-1:0] exp_data = 0,
input bit [TL_DW-1:0] compare_mask = '1,
- input bit check_exp_data = 1'b0);
+ input bit check_exp_data = 1'b0,
+ tl_sequencer tl_sequencer_h = p_sequencer.tl_sequencer_h);
`DV_SPINWAIT(
// thread to read/write tlul
tl_host_single_seq tl_seq;
- `uvm_create_on(tl_seq, p_sequencer.tl_sequencer_h)
+ `uvm_create_on(tl_seq, tl_sequencer_h)
if (cfg.zero_delays) begin
tl_seq.min_req_delay = 0;
tl_seq.max_req_delay = 0;
@@ -423,8 +425,9 @@
virtual task run_same_csr_outstanding_vseq(int num_times);
csr_excl_item csr_excl = add_and_return_csr_excl("csr_excl");
csr_test_type_e csr_test_type = CsrRwTest; // share the same exclusion as csr_rw_test
- uvm_reg test_csrs[$];
- ral.get_registers(test_csrs);
+ uvm_reg test_csrs[$];
+
+ foreach (cfg.ral_models[i]) cfg.ral_models[i].get_registers(test_csrs);
for (int trans = 1; trans <= num_times; trans++) begin
`uvm_info(`gfn, $sformatf("Running same CSR outstanding test iteration %0d/%0d",
diff --git a/hw/dv/sv/dv_lib/dv_base_env_cfg.sv b/hw/dv/sv/dv_lib/dv_base_env_cfg.sv
index 1360ff6..0512e1e 100644
--- a/hw/dv/sv/dv_lib/dv_base_env_cfg.sv
+++ b/hw/dv/sv/dv_lib/dv_base_env_cfg.sv
@@ -15,6 +15,7 @@
// reg model & q of valid csr addresses
RAL_T ral;
+ dv_base_reg_block ral_models[$];
bit [TL_AW-1:0] csr_addrs[$];
addr_range_t mem_ranges[$];
@@ -64,6 +65,7 @@
ral = RAL_T::type_id::create("ral");
ral.build(this.csr_base_addr, null);
apply_ral_fixes();
+ ral_models.push_back(ral);
end
endfunction
diff --git a/hw/dv/sv/dv_lib/dv_base_vseq.sv b/hw/dv/sv/dv_lib/dv_base_vseq.sv
index 6b0e8c5..7cade3b 100644
--- a/hw/dv/sv/dv_lib/dv_base_vseq.sv
+++ b/hw/dv/sv/dv_lib/dv_base_vseq.sv
@@ -71,7 +71,9 @@
cfg.clk_rst_vif.apply_reset();
csr_utils_pkg::reset_deasserted();
end
- if (cfg.has_ral) ral.reset(kind);
+ if (cfg.has_ral) begin
+ foreach (cfg.ral_models[i]) cfg.ral_models[i].reset(kind);
+ end
endtask
virtual task wait_for_reset(string reset_kind = "HARD",
@@ -167,7 +169,7 @@
// run write-only sequence to randomize the csr values
m_csr_write_seq = csr_write_seq::type_id::create("m_csr_write_seq");
- m_csr_write_seq.models.push_back(ral);
+ m_csr_write_seq.models = cfg.ral_models;
m_csr_write_seq.set_csr_excl_item(csr_excl);
m_csr_write_seq.external_checker = cfg.en_scb;
if (!enable_asserts_in_hw_reset_rand_wr) $assertoff;
@@ -184,7 +186,7 @@
// create base csr seq and pass our ral
m_csr_seq = csr_base_seq::type_id::create("m_csr_seq");
m_csr_seq.num_test_csrs = num_test_csrs;
- m_csr_seq.models.push_back(ral);
+ m_csr_seq.models = cfg.ral_models;
m_csr_seq.set_csr_excl_item(csr_excl);
m_csr_seq.external_checker = cfg.en_scb;
m_csr_seq.start(null);
