[dv/rstmgr] Add alert and cpu_info_attr assertions
Also do make minor fixes to docs.
Remove common CSR test exclusion from sw_rst_regwen.
Signed-off-by: Guillermo Maturana <maturana@google.com>
diff --git a/hw/ip/rstmgr/data/rstmgr.hjson b/hw/ip/rstmgr/data/rstmgr.hjson
index 92330a2..58990ff 100644
--- a/hw/ip/rstmgr/data/rstmgr.hjson
+++ b/hw/ip/rstmgr/data/rstmgr.hjson
@@ -219,7 +219,7 @@
{ multireg: {
cname: "RSTMGR_SW_RST",
- name: "SW_RST_REGEN",
+ name: "SW_RST_REGWEN",
desc: '''
Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed.
@@ -236,8 +236,6 @@
resval: "1",
},
],
- tags: [// Don't reset other IPs as it will affect CSR access on these IPs
- "excl:CsrAllTests:CsrExclWrite"]
}
}
@@ -267,6 +265,4 @@
}
}
]
-
-
}
diff --git a/hw/ip/rstmgr/data/rstmgr.hjson.tpl b/hw/ip/rstmgr/data/rstmgr.hjson.tpl
index 8d341b9..d6ae353 100644
--- a/hw/ip/rstmgr/data/rstmgr.hjson.tpl
+++ b/hw/ip/rstmgr/data/rstmgr.hjson.tpl
@@ -278,8 +278,6 @@
resval: "1",
},
],
- tags: [// Don't reset other IPs as it will affect CSR access on these IPs
- "excl:CsrAllTests:CsrExclWrite"]
}
}
@@ -309,6 +307,4 @@
}
}
]
-
-
}
diff --git a/hw/ip/rstmgr/data/rstmgr_testplan.hjson b/hw/ip/rstmgr/data/rstmgr_testplan.hjson
index 9d1afdd..4bcc083 100644
--- a/hw/ip/rstmgr/data/rstmgr_testplan.hjson
+++ b/hw/ip/rstmgr/data/rstmgr_testplan.hjson
@@ -52,38 +52,26 @@
tests: ["rstmgr_por_stretcher"]
}
{
- name: sw_rst_regen_clear_once
- desc: '''Test that `sw_rst_regen` cannot change a bit to 1.
-
- Once a bit in `sw_rst_regen` is set to 0 there is no way to change
- it back to 1.
-
- This should be tested in the common CSR tests.
- '''
- milestone: V2
- tests: []
- }
- {
name: sw_rst
desc: '''Test the sw_rst functionality.
- The `sw_rst_regen` and `sw_rst_ctrl_n` CSRs control the specific
+ The `sw_rst_regwen` and `sw_rst_ctrl_n` CSRs control the specific
reset outputs to peripherals in the following sequence:
- - Test all `sw_rst_ctrl_n` bits when `sw_rst_regen` is all 1's.
- - Clear each `sw_rst_regen` bit to verify the corresponding resets
+ - Test all `sw_rst_ctrl_n` bits when `sw_rst_regwen` is all 1's.
+ - Clear each `sw_rst_regwen` bit to verify the corresponding resets
are masked.
**Stimulus**:
- - Write `sw_rst_ctrl_n` CSR with random values when regen is all 1's.
- - Clear each `sw_rst_regen` bit and write `sw_rst_ctrl_n` CSR with
+ - Write `sw_rst_ctrl_n` CSR with random values when regwen is all 1's.
+ - Clear each `sw_rst_regwen` bit and write `sw_rst_ctrl_n` CSR with
all 0's.
- - After each regen bit check set `sw_rst_ctrl_n` to all 1's.
+ - After each regwen bit check set `sw_rst_ctrl_n` to all 1's.
**Checks**:
- Check that the zero bits in `sw_rst_ctrl_n` enabled by
- `sw_rst_regen` cause the respective resets to become active.
+ `sw_rst_regwen` cause the respective resets to become active.
- Check that the zero bits in `sw_rst_ctrl_n` disabled by
- `sw_rst_regen` have no effect on resets.
+ `sw_rst_regwen` have no effect on resets.
- Check the `reset_info`, `cpu_info`, and `alert_info` CSRs are not modified.
'''
milestone: V2
@@ -213,7 +201,7 @@
name: sw_rst_cg
desc: '''Collects coverage on the software reset functionality.
- Each bit of the pair `sw_rst_regen` and `sw_rst_ctrl_n` CSRs
+ Each bit of the pair `sw_rst_regwen` and `sw_rst_ctrl_n` CSRs
independently control if the corresponding output reset is
asserted (active low).
This collects one coverpoint for each, and their cross.
diff --git a/hw/ip/rstmgr/doc/dv/index.md b/hw/ip/rstmgr/doc/dv/index.md
index 84439af..35bbde1 100644
--- a/hw/ip/rstmgr/doc/dv/index.md
+++ b/hw/ip/rstmgr/doc/dv/index.md
@@ -82,8 +82,7 @@
Other sequences follow:
* `rstmgr_smoke_vseq` tests the rstmgr through software initiated low power, peripheral reset, ndm reset, and software initiated resets.
* `rstmgr_reset_stretcher_vseq` tests the `resets_o.rst_por_aon_n[0]` output is asserted after 32 stable cycles of `ast_i.aon_pok`.
-* `rstmgr_sw_rst_regen_clear_once_vseq` tests that the `sw_rst_regen` CSR is such that a bit cannot be flipped back to 1.
-* `rstmgr_sw_rst_vseq` tests the functionality provided by the `sw_rst_regen` and `sw_rst_ctrl_n`.
+* `rstmgr_sw_rst_vseq` tests the functionality provided by the `sw_rst_regwen` and `sw_rst_ctrl_n`.
* `rstmgr_reset_info_vseq` tests the `reset_info` CSR contents correspond to the different resets.
* `rstmgr_cpu_info_vseq` tests the `cpu_info` CSR contents capture to the `cpu_dump_i` present at the time of a reset.
* `rstmgr_alert_info_vseq` tests the `alert_info` CSR contents capture to the `alert_dump_i` present at the time of a reset.
@@ -102,7 +101,7 @@
#### Scoreboard
The `rstmgr_scoreboard` is primarily used for end to end checking.
The following checks are performed:
-* The software controlled peripheral resets are asserted based on both `sw_rst_regen` and `sw_rst_ctrl_n` CSRs when not set by `rst_lc_reg`, `rst_sys_req`, or por.
+* The software controlled peripheral resets are asserted based on both `sw_rst_regwen` and `sw_rst_ctrl_n` CSRs when not set by `rst_lc_reg`, `rst_sys_req`, or por.
* The `cpu_info` CSRs record the expected values based on the inputs on a system reset.
* The `alert_info` CSRs record the expected values based on the inputs on a system reset.
* The `reset_info` CSR records the expected reset cause.
@@ -120,6 +119,8 @@
Checked via SVA in `hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`.
* The scan reset `scan_rst_ni` qualified by `scanmode_i` triggers all cascaded resets that `por_n_i` does.
Checked via SVA in `hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`.
+* The `alert` and `cpu_info_attr` indicate the number of 32-bit words needed to capture their inputs.
+ Checked via SVA in `hw/ip/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv`.
## Building and running tests
We are using our in-house developed [regression tool]({{< relref "hw/dv/tools/README.md" >}}) for building and running our tests and regressions.
diff --git a/hw/ip/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv b/hw/ip/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv
new file mode 100644
index 0000000..a79274d
--- /dev/null
+++ b/hw/ip/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv
@@ -0,0 +1,19 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This has assertions that check the read-only value of the alert and cpu_info_attr.
+interface rstmgr_attrs_sva_if (
+ input logic rst_ni,
+ input int actual_alert_info_attr,
+ input int actual_cpu_info_attr,
+ input int expected_alert_info_attr,
+ input int expected_cpu_info_attr
+);
+
+ initial
+ @(posedge rst_ni) begin
+ `ASSERT_I(AlertInfoAttr_A, actual_alert_info_attr == expected_alert_info_attr)
+ `ASSERT_I(CpuInfoAttr_A, actual_cpu_info_attr == expected_cpu_info_attr)
+ end
+endinterface
diff --git a/hw/ip/rstmgr/dv/sva/rstmgr_bind.sv b/hw/ip/rstmgr/dv/sva/rstmgr_bind.sv
index b6b70cc..c582946 100644
--- a/hw/ip/rstmgr/dv/sva/rstmgr_bind.sv
+++ b/hw/ip/rstmgr/dv/sva/rstmgr_bind.sv
@@ -41,5 +41,12 @@
.scanmode_i
);
+ bind rstmgr rstmgr_attrs_sva_if rstmgr_attrs_sva_if (
+ .rst_ni,
+ .actual_alert_info_attr(hw2reg.alert_info_attr),
+ .actual_cpu_info_attr(hw2reg.cpu_info_attr),
+ .expected_alert_info_attr(($bits(alert_dump_i) + 31) / 32),
+ .expected_cpu_info_attr(($bits(cpu_dump_i) + 31) / 32)
+ );
endmodule
diff --git a/hw/ip/rstmgr/dv/sva/rstmgr_sva.core b/hw/ip/rstmgr/dv/sva/rstmgr_sva.core
index 7ba9a3f..2468483 100644
--- a/hw/ip/rstmgr/dv/sva/rstmgr_sva.core
+++ b/hw/ip/rstmgr/dv/sva/rstmgr_sva.core
@@ -10,7 +10,7 @@
- lowrisc:tlul:headers
- lowrisc:fpv:csr_assert_gen
- lowrisc:dv:pwrmgr_rstmgr_sva_if
- - lowrisc:dv:rstmgr_cascading_sva_if
+ - lowrisc:dv:rstmgr_sva_ifs
files:
- rstmgr_bind.sv
diff --git a/hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.core b/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core
similarity index 86%
rename from hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.core
rename to hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core
index 14f6d71..f2aac25 100644
--- a/hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.core
+++ b/hw/ip/rstmgr/dv/sva/rstmgr_sva_ifs.core
@@ -2,7 +2,7 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:dv:rstmgr_cascading_sva_if:0.1"
+name: "lowrisc:dv:rstmgr_sva_ifs:0.1"
description: "RSTMGR cascading resets assertion interface."
filesets:
files_dv:
@@ -13,6 +13,7 @@
files:
- rstmgr_cascading_sva_if.sv
+ - rstmgr_attrs_sva_if.sv
file_type: systemVerilogSource
targets:
diff --git a/hw/ip/rstmgr/rtl/rstmgr_reg_pkg.sv b/hw/ip/rstmgr/rtl/rstmgr_reg_pkg.sv
index 2ff6498..6f027bf 100644
--- a/hw/ip/rstmgr/rtl/rstmgr_reg_pkg.sv
+++ b/hw/ip/rstmgr/rtl/rstmgr_reg_pkg.sv
@@ -35,7 +35,7 @@
typedef struct packed {
logic q;
- } rstmgr_reg2hw_sw_rst_regen_mreg_t;
+ } rstmgr_reg2hw_sw_rst_regwen_mreg_t;
typedef struct packed {
logic q;
@@ -80,7 +80,7 @@
typedef struct packed {
rstmgr_reg2hw_reset_info_reg_t reset_info; // [11:11]
rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [10:6]
- rstmgr_reg2hw_sw_rst_regen_mreg_t [1:0] sw_rst_regen; // [5:4]
+ rstmgr_reg2hw_sw_rst_regwen_mreg_t [1:0] sw_rst_regwen; // [5:4]
rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [1:0] sw_rst_ctrl_n; // [3:0]
} rstmgr_reg2hw_t;
@@ -98,7 +98,7 @@
parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_CTRL_OFFSET = 5'h 4;
parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_ATTR_OFFSET = 5'h 8;
parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_OFFSET = 5'h c;
- parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGEN_OFFSET = 5'h 10;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_OFFSET = 5'h 10;
parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_OFFSET = 5'h 14;
// Reset values for hwext registers and their fields
@@ -116,7 +116,7 @@
RSTMGR_ALERT_INFO_CTRL,
RSTMGR_ALERT_INFO_ATTR,
RSTMGR_ALERT_INFO,
- RSTMGR_SW_RST_REGEN,
+ RSTMGR_SW_RST_REGWEN,
RSTMGR_SW_RST_CTRL_N
} rstmgr_id_e;
@@ -126,7 +126,7 @@
4'b 0001, // index[1] RSTMGR_ALERT_INFO_CTRL
4'b 0001, // index[2] RSTMGR_ALERT_INFO_ATTR
4'b 1111, // index[3] RSTMGR_ALERT_INFO
- 4'b 0001, // index[4] RSTMGR_SW_RST_REGEN
+ 4'b 0001, // index[4] RSTMGR_SW_RST_REGWEN
4'b 0001 // index[5] RSTMGR_SW_RST_CTRL_N
};
diff --git a/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv b/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv
index a8fe0e1..99f5666 100644
--- a/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv
+++ b/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv
@@ -126,11 +126,11 @@
logic [3:0] alert_info_attr_qs;
logic alert_info_re;
logic [31:0] alert_info_qs;
- logic sw_rst_regen_we;
- logic sw_rst_regen_en_0_qs;
- logic sw_rst_regen_en_0_wd;
- logic sw_rst_regen_en_1_qs;
- logic sw_rst_regen_en_1_wd;
+ logic sw_rst_regwen_we;
+ logic sw_rst_regwen_en_0_qs;
+ logic sw_rst_regwen_en_0_wd;
+ logic sw_rst_regwen_en_1_qs;
+ logic sw_rst_regwen_en_1_wd;
logic sw_rst_ctrl_n_re;
logic sw_rst_ctrl_n_we;
logic sw_rst_ctrl_n_val_0_qs;
@@ -323,20 +323,20 @@
);
- // Subregister 0 of Multireg sw_rst_regen
- // R[sw_rst_regen]: V(False)
+ // Subregister 0 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen]: V(False)
// F[en_0]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
- ) u_sw_rst_regen_en_0 (
+ ) u_sw_rst_regwen_en_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (sw_rst_regen_we),
- .wd (sw_rst_regen_en_0_wd),
+ .we (sw_rst_regwen_we),
+ .wd (sw_rst_regwen_en_0_wd),
// from internal hardware
.de (1'b0),
@@ -344,10 +344,10 @@
// to internal hardware
.qe (),
- .q (reg2hw.sw_rst_regen[0].q),
+ .q (reg2hw.sw_rst_regwen[0].q),
// to register interface (read)
- .qs (sw_rst_regen_en_0_qs)
+ .qs (sw_rst_regwen_en_0_qs)
);
// F[en_1]: 1:1
@@ -355,13 +355,13 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
- ) u_sw_rst_regen_en_1 (
+ ) u_sw_rst_regwen_en_1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (sw_rst_regen_we),
- .wd (sw_rst_regen_en_1_wd),
+ .we (sw_rst_regwen_we),
+ .wd (sw_rst_regwen_en_1_wd),
// from internal hardware
.de (1'b0),
@@ -369,10 +369,10 @@
// to internal hardware
.qe (),
- .q (reg2hw.sw_rst_regen[1].q),
+ .q (reg2hw.sw_rst_regwen[1].q),
// to register interface (read)
- .qs (sw_rst_regen_en_1_qs)
+ .qs (sw_rst_regwen_en_1_qs)
);
@@ -415,7 +415,7 @@
addr_hit[1] = (reg_addr == RSTMGR_ALERT_INFO_CTRL_OFFSET);
addr_hit[2] = (reg_addr == RSTMGR_ALERT_INFO_ATTR_OFFSET);
addr_hit[3] = (reg_addr == RSTMGR_ALERT_INFO_OFFSET);
- addr_hit[4] = (reg_addr == RSTMGR_SW_RST_REGEN_OFFSET);
+ addr_hit[4] = (reg_addr == RSTMGR_SW_RST_REGWEN_OFFSET);
addr_hit[5] = (reg_addr == RSTMGR_SW_RST_CTRL_N_OFFSET);
end
@@ -447,11 +447,11 @@
assign alert_info_ctrl_index_wd = reg_wdata[7:4];
assign alert_info_attr_re = addr_hit[2] & reg_re & !reg_error;
assign alert_info_re = addr_hit[3] & reg_re & !reg_error;
- assign sw_rst_regen_we = addr_hit[4] & reg_we & !reg_error;
+ assign sw_rst_regwen_we = addr_hit[4] & reg_we & !reg_error;
- assign sw_rst_regen_en_0_wd = reg_wdata[0];
+ assign sw_rst_regwen_en_0_wd = reg_wdata[0];
- assign sw_rst_regen_en_1_wd = reg_wdata[1];
+ assign sw_rst_regwen_en_1_wd = reg_wdata[1];
assign sw_rst_ctrl_n_re = addr_hit[5] & reg_re & !reg_error;
assign sw_rst_ctrl_n_we = addr_hit[5] & reg_we & !reg_error;
@@ -484,8 +484,8 @@
end
addr_hit[4]: begin
- reg_rdata_next[0] = sw_rst_regen_en_0_qs;
- reg_rdata_next[1] = sw_rst_regen_en_1_qs;
+ reg_rdata_next[0] = sw_rst_regwen_en_0_qs;
+ reg_rdata_next[1] = sw_rst_regwen_en_1_qs;
end
addr_hit[5]: begin
diff --git a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
index 3fb664c..62d5b83 100644
--- a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
+++ b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
@@ -356,8 +356,6 @@
resval: "1",
},
],
- tags: [// Don't reset other IPs as it will affect CSR access on these IPs
- "excl:CsrAllTests:CsrExclWrite"]
}
}
@@ -387,6 +385,4 @@
}
}
]
-
-
}
