commit eea96b9043fd99f47280beb1e19504fba5bcc560
author sriyerg <46467186+sriyerg@users.noreply.github.com> Thu Mar 12 22:00:15 2020 -0700
committer Philipp Wagner <mail@philipp-wagner.com> Fri Mar 13 11:13:37 2020 +0000
tree 745177c8d494703b10a6c35dd4ef0fd0bdd1d68b
parent d69dcdf0e182862287c233202f8a6f7610de736a

Revert "[i2c, dv] Update i2c.hjson to support automation for csr excl"

This reverts commit d69dcdf0e182862287c233202f8a6f7610de736a.

hw/ip/i2c/data/i2c.hjson

diff --git a/hw/ip/i2c/data/i2c.hjson b/hw/ip/i2c/data/i2c.hjson
index 954db5f..6911679 100644
--- a/hw/ip/i2c/data/i2c.hjson
+++ b/hw/ip/i2c/data/i2c.hjson
@@ -70,8 +70,6 @@
       swaccess: "ro"
       hwaccess: "hwo"
       hwext:    "true"
-      tags: [// ro registers - exclude init and write-read check
-             "excl:CsrAllTests:CsrExclWriteCheck"]
       fields: [
         { bits: "0"
           name: "FMTFULL"
@@ -109,8 +107,6 @@
       hwaccess: "hrw"
       hwext: "true"
       hwre: "true"
-      tags: [// ro registers - exclude init and write-read check
-             "excl:CsrAllTests:CsrExclCheck"]
       fields: [
         {bits: "7:0"}
       ]
@@ -222,8 +218,6 @@
       swaccess: "ro"
       hwaccess: "hwo"
       hwext: "true"
-      tags: [// ro registers - exclude init and write-read check
-             "excl:CsrAllTests:CsrExclWriteCheck"]
       fields: [
         { bits: "5:0"
           name: "FMTLVL"
@@ -259,8 +253,6 @@
       swaccess: "ro"
       hwaccess: "hwo"
       hwext:    "true"
-      tags: [// ro registers - exclude init and write-read check
-             "excl:CsrAllTests:CsrExclCheck"]
       fields: [
         { bits: "15:0"
           name: "SCL_RX"

hw/ip/i2c/dv/env/seq_lib/i2c_common_vseq.sv

diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_common_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_common_vseq.sv
index 94b255f..d1602ef 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_common_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_common_vseq.sv
@@ -22,6 +22,21 @@
     run_common_vseq_wrapper(num_trans); // inherit from cip_base_vseq.sv
   endtask : body
 
+  // function to add csr exclusions of the given type using the csr_excl_item item
+  virtual function void add_csr_exclusions(string           csr_test_type,
+                                           csr_excl_item    csr_excl,
+                                           string           scope = "ral");
+
+    // intr_state is affected by writes to other csrs
+    csr_excl.add_excl({scope, ".", "intr_state"}, CsrExclCheck);
+    // RO registers - exclude init and write-read check
+    csr_excl.add_excl({scope, ".", "status"}, CsrExclWriteCheck);
+    csr_excl.add_excl({scope, ".", "fifo_status"}, CsrExclWriteCheck);
+    // RO registers - exclude init and write-read check
+    csr_excl.add_excl({scope, ".", "val"}, CsrExclCheck);
+    csr_excl.add_excl({scope, ".", "rdata"}, CsrExclCheck);
+  endfunction : add_csr_exclusions
+
   task post_start();
     `uvm_info(`gfn, "stop simulation", UVM_DEBUG)
   endtask : post_start