commit eea799259b26294891f0228f6d76e028404cbeac
author Steve Nelson <steve.nelson@wdc.com> Tue Jan 26 06:31:54 2021 -0800
committer rasmus-madsen <53917183+rasmus-madsen@users.noreply.github.com> Thu Jan 28 19:20:04 2021 +0100
tree 916053e3fb55990891eba1df6ca3b1cfea9120c4
parent af3b272938f4ca8c0d6ab953264a241805163a96

[csrng/dv] testplan

Signed-off-by: Steve Nelson <steve.nelson@wdc.com>

hw/ip/csrng/data/csrng_testplan.hjson

diff --git a/hw/ip/csrng/data/csrng_testplan.hjson b/hw/ip/csrng/data/csrng_testplan.hjson
index f10ffa8..89da81c 100644
--- a/hw/ip/csrng/data/csrng_testplan.hjson
+++ b/hw/ip/csrng/data/csrng_testplan.hjson
@@ -20,8 +20,9 @@
     {
       name: firmware
       desc: '''
-            Verify ability to access SW app registers based on value of efuse input
-            Verify regen bit enables/disables write access to control registers
+            Verify ability to access genbits register based on value of efuse input.
+            Verify regen bit disables write access of control registers.
+            Verify registers at End-Of-Test.
             '''
       milestone: V2
       tests: []
@@ -29,10 +30,11 @@
     {
       name: interrupts
       desc: '''
-            Verify csrng cmd_req_done interrupt assert/clear when expected/predicted.
-            Verify csrng entropy_req interrupt assert/clear when expected/predicted.
-            Verify csrng hw_inst_exc interrupt assert/clear when expected/predicted.
-            Verify csrng intr_fifo_err interrupt assert/clear when expected/predicted.
+            Verify cs_cmd_req_done interrupt asserts/clears as predicted.
+            Verify cs_entropy_req interrupt asserts/clears as predicted.
+            Verify cs_hw_inst_exc interrupt asserts/clears as predicted.
+            Verify cs_fifo_err interrupt asserts/clears as predicted.
+            Verify fifo error status bits are set as predicted.
             '''
       milestone: V2
       tests: []
@@ -44,6 +46,16 @@
             Verify all HW app csrng commands req/status behave as predicted.
             Verify above for all valid values of acmd, clen, flags, glen.
             Verify for multiple hw app interfaces running in parallel.
+            Verify sw/hw app interfaces running in parallel.
+            '''
+      milestone: V2
+      tests: []
+    }
+    {
+      name: life cycle
+      desc: '''
+            Verify lifecycle hardware debug mode enables AES bypass, reading CSRNG internal state.
+	    Verify CSRNG internal state for all csrng/genbits operations.
             '''
       milestone: V2
       tests: []
@@ -52,7 +64,7 @@
       name: genbits
       desc: '''
             Verify genbits generated as predicted.
-            Verify fips bits as predicted.
+            Verify fips bits is passed through properly.
             Verify for multiple hw app interfaces running in parallel.
             '''
       milestone: V2

hw/ip/csrng/rtl/csrng_pkg.sv

diff --git a/hw/ip/csrng/rtl/csrng_pkg.sv b/hw/ip/csrng/rtl/csrng_pkg.sv
index 411becf..a243ba2 100644
--- a/hw/ip/csrng/rtl/csrng_pkg.sv
+++ b/hw/ip/csrng/rtl/csrng_pkg.sv
@@ -11,7 +11,8 @@
 
   parameter int unsigned   GENBITS_BUS_WIDTH = 128;
   parameter int unsigned   CSRNG_CMD_WIDTH = 32;
-  parameter int unsigned   FIPS_GENBITS_BUS_WIDTH = entropy_src_pkg::FIPS_BUS_WIDTH + GENBITS_BUS_WIDTH;
+  parameter int unsigned   FIPS_GENBITS_BUS_WIDTH = entropy_src_pkg::FIPS_BUS_WIDTH +
+                           GENBITS_BUS_WIDTH;
 
   // instantiation interface
   typedef struct packed {