commit ee94ef27ef02b98b0d021999f8e866318eb45c1a
author Mark Branstad <mark.branstad@wdc.com> Wed Nov 10 07:03:21 2021 -0800
committer mwbranstad <52834797+mwbranstad@users.noreply.github.com> Fri Nov 12 16:03:07 2021 -0600
tree a1185314f338edbc7ffaa5894ef944986723460d
parent 7f2bdc9f34f693e906379a073cf1fe5f5d349729

[edn/rtl] prim count err not gated by enable

The module enable has been removed from the prim count err signal.

Signed-off-by: Mark Branstad <mark.branstad@wdc.com>

hw/ip/edn/rtl/edn_core.sv

diff --git a/hw/ip/edn/rtl/edn_core.sv b/hw/ip/edn/rtl/edn_core.sv
index 385536d..68f801f 100644
--- a/hw/ip/edn/rtl/edn_core.sv
+++ b/hw/ip/edn/rtl/edn_core.sv
@@ -237,12 +237,12 @@
   assign event_edn_cmd_req_done = csrng_cmd_ack;
 
   // set the interrupt sources
-  assign event_edn_fatal_err = edn_enable && (
+  assign event_edn_fatal_err = (edn_enable && (
          sfifo_rescmd_err_sum ||
          sfifo_gencmd_err_sum ||
          edn_ack_sm_err_sum ||
-         edn_main_sm_err_sum ||
-         edn_cntr_err_sum);
+         edn_main_sm_err_sum)) ||
+         edn_cntr_err_sum;
 
   // set fifo errors that are single instances of source
   assign sfifo_rescmd_err_sum = (|sfifo_rescmd_err) ||
@@ -284,7 +284,7 @@
   assign hw2reg.err_code.edn_main_sm_err.de = edn_enable && edn_main_sm_err_sum;
 
   assign hw2reg.err_code.edn_cntr_err.d = 1'b1;
-  assign hw2reg.err_code.edn_cntr_err.de = edn_enable && edn_cntr_err_sum;
+  assign hw2reg.err_code.edn_cntr_err.de = edn_cntr_err_sum;
 
 
  // set the err code type bits