[dv/alert_handler] interrupt needs one clock cycle to be reset

In the alert_handler design, there is a `timeout` counter that will
count how many cycles the interrupt has been set. If the cycle is larger
than the threshold, the corresponding escalation will be triggered.
Upon interrupt is set, design will take one more clock cycle to stop the
counter. But tb's scb here stop the counter immediately. If the
interrupt is issued at the last clock cycle before timeout, design will
continue to count one more clock cycle and trigger the escalation, while
in tb I will exit immediately.
This PR fixed it by adding a one clock cycle delay before setting the
interrupt values.

Signed-off-by: Cindy Chen <chencindy@google.com>