commit ee3b976e2bd2fea9c2e4d09705969218bbdd2af6
author Eunchan Kim <eunchan@opentitan.org> Thu Apr 01 11:49:50 2021 -0700
committer Eunchan Kim <eunchan@opentitan.org> Tue Apr 06 13:05:14 2021 -0700
tree 360bd620021d3eeed07db31c8c83d4850c067ae3
parent 0d62c3c104417b714d6713444d2bef4815be9709

[spi_device] Add more syn constraints

- Defined false_path from csb to any output to host systems
- Defined input/output clock to use later (half-clock constraints)

Signed-off-by: Eunchan Kim <eunchan@opentitan.org>

hw/ip/spi_device/rtl/spi_device.sv

diff --git a/hw/ip/spi_device/rtl/spi_device.sv b/hw/ip/spi_device/rtl/spi_device.sv
index 52fabaa..8ff0fd9 100644
--- a/hw/ip/spi_device/rtl/spi_device.sv
+++ b/hw/ip/spi_device/rtl/spi_device.sv
@@ -598,7 +598,7 @@
 
     // Config (changed dynamically)
     .order_i      (rxorder),
-    .io_mode_i    (io_mode_outclk)
+    .io_mode_i    (io_mode)
   );
 
   spi_p2s u_p2s (
@@ -625,8 +625,8 @@
     .FifoWidth (FifoWidth),
     .FifoDepth (FifoDepth)
   ) u_fwmode (
-    .clk_i,
-    .rst_ni,
+    .clk_i    (sram_clk),
+    .rst_ni   (sram_rst_n),
 
     .clk_spi_in_i  (clk_spi_in_buf),
     .rst_rxfifo_ni (rst_rxfifo_n),

hw/top_earlgrey/syn/asic.constraints.sdc

diff --git a/hw/top_earlgrey/syn/asic.constraints.sdc b/hw/top_earlgrey/syn/asic.constraints.sdc
index f6450bd..84ac04b 100644
--- a/hw/top_earlgrey/syn/asic.constraints.sdc
+++ b/hw/top_earlgrey/syn/asic.constraints.sdc
@@ -162,9 +162,20 @@
 create_clock -name SPI_DEV_CLK  -period ${SPI_DEV_TCK} [get_ports ${SPI_DEV_CLK_PIN}]
 set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} [get_clocks SPI_DEV_CLK]
 
+create_generated_clock -name SPI_DEV_IN_CLK -source SPI_DEV_CLK -divide_by 1 \
+    [get_pins top_earlgrey/u_spi_device/u_clk_spi_in_buf/clk_o]
+create_generated_clock -name SPI_DEV_OUT_CLK -source SPI_DEV_CLK -divide_by 1 \
+    -invert [get_pins top_earlgrey/u_spi_device/u_clk_spi_out_buf/clk_o]
+
+## TODO: Define SRAM clock, which is muxed clock. Do we need set_case_analysis?
+## sram_clk is after clock gating cell
+create_generated_clock -name SPI_SRAM_CLK -source SPI_DEV_CLK -divide_by 1 \
+    [get_pins top_earlgrey/u_spi_device/u_sram_clk_cg/clk_o]
+
 ## TODO: these are dummy constraints and likely incorrect, need to properly constrain min/max
-set SPI_DEV_IN_DEL_FRACTION 0.7
-set SPI_DEV_OUT_DEL_FRACTION 0.7
+# FRACTION is reduced to 0.2 as internal datapath for SPI is half clk period
+set SPI_DEV_IN_DEL_FRACTION 0.2
+set SPI_DEV_OUT_DEL_FRACTION 0.2
 set SPI_DEV_IN_DEL    [expr ${SPI_DEV_IN_DEL_FRACTION} * ${SPI_DEV_TCK}]
 set SPI_DEV_OUT_DEL   [expr ${SPI_DEV_OUT_DEL_FRACTION} * ${SPI_DEV_TCK}]
 
@@ -181,6 +192,13 @@
 set_output_delay ${SPI_DEV_OUT_DEL} [get_ports SPI_DEV_D2]   -clock SPI_DEV_CLK
 set_output_delay ${SPI_DEV_OUT_DEL} [get_ports SPI_DEV_D3]   -clock SPI_DEV_CLK
 
+# False path from CSb to return to host as CSb for that path behaves as reset.
+#set_ideal_network [get_pins top_earlgrey/u_spi_device/u_csb_rst_scan_mux/clk_o]
+set_false_path -through [get_pins top_earlgrey/u_spi_device/cio_csb_i] \
+               -through [get_pins top_earlgrey/u_spi_device/cio_sd_en_o*]
+set_false_path -through [get_pins top_earlgrey/u_spi_device/cio_csb_i] \
+               -through [get_pins top_earlgrey/u_spi_device/cio_sd_o*]
+
 #####################
 # SPI HOST clock   #
 #####################