[dv/doc] updated dv_plan links to new location
Signed-off-by: Rasmus Madsen <rasmus.madsen@wdc.com>
diff --git a/doc/project/development_stages.md b/doc/project/development_stages.md
index d200d43..76377d8 100644
--- a/doc/project/development_stages.md
+++ b/doc/project/development_stages.md
@@ -222,7 +222,7 @@
```hjson
{
design_spec: "hw/ip/gpio/doc"
- dv_doc: "hw/ip/gpio/doc/dv_doc"
+ dv_doc: "hw/ip/gpio/doc/dv"
hw_checklist: "hw/ip/gpio/doc/checklist"
sw_checklist: "sw/device/lib/dif/dif_gpio"
}
diff --git a/doc/ug/dv_methodology/index.md b/doc/ug/dv_methodology/index.md
index 94de1fe..b91ec3b 100644
--- a/doc/ug/dv_methodology/index.md
+++ b/doc/ug/dv_methodology/index.md
@@ -164,7 +164,7 @@
Each of the IP level DV environments are described in further detail within their own [dv document](#dv-plan) document.
To find all of them, please navigate to this [landing page]({{< relref "hw" >}}).
-The [UART dv document]({{< relref "hw/ip/uart/doc/dv_doc" >}}) documentation which can be found there can be used as an example / reference.
+The [UART dv document]({{< relref "hw/ip/uart/doc/dv" >}}) documentation which can be found there can be used as an example / reference.
### Core Ibex Level DV
diff --git a/doc/ug/getting_started_dv.md b/doc/ug/getting_started_dv.md
index e456787..fcceb6f 100644
--- a/doc/ug/getting_started_dv.md
+++ b/doc/ug/getting_started_dv.md
@@ -36,7 +36,7 @@
However, it is expected to list all the verification components needed and depict the planned testbench as a block diagram.
Under the 'design verification' directory in the OpenTitan team drive, some sample testbench block diagrams are available in the `.svg` format, which can be used as a template.
The Hjson dv_plan on the other hand, is required to be completed.
-Please refer to the [dv_planner tool]({{< relref "util/dvsim/testplanner/README.md" >}}) documentation for additional details on how to write the Hjson dv_plan.
+Please refer to the [testplanner tool]({{< relref "util/dvsim/testplanner/README.md" >}}) documentation for additional details on how to write the Hjson dv_plan.
Once done, these documents are to be reviewed with the designer(s) and other project members for completeness and clarity.
## UVM RAL Model
diff --git a/hw/_index.md b/hw/_index.md
index fbac20f..3ffabf9 100644
--- a/hw/_index.md
+++ b/hw/_index.md
@@ -41,7 +41,7 @@
* `top_earlgrey`
* [Design specification]({{< relref "hw/top_earlgrey/doc" >}})
- * [dv document]({{< relref "hw/top_earlgrey/doc/dv_doc" >}})
+ * [dv document]({{< relref "hw/top_earlgrey/doc/dv" >}})
* [DV simulation results, with coverage (nightly)](https://reports.opentitan.org/hw/top_earlgrey/dv/latest/results.html)
* FPV results (nightly) (TBD)
* [AscentLint results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/ascentlint/latest/results.html)
diff --git a/hw/ip/aes/doc/checklist.md b/hw/ip/aes/doc/checklist.md
index f02d56f..97c9a28 100644
--- a/hw/ip/aes/doc/checklist.md
+++ b/hw/ip/aes/doc/checklist.md
@@ -110,8 +110,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [AES dv document]({{<relref "hw/ip/aes/doc/dv_doc" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [AES dv_plan]({{<relref "hw/ip/aes/doc/dv_doc/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [AES dv document]({{<relref "hw/ip/aes/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [AES dv_plan]({{<relref "hw/ip/aes/doc/dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/csrng/doc/checklist.md b/hw/ip/csrng/doc/checklist.md
index 1d36cd3..950de3d 100644
--- a/hw/ip/csrng/doc/checklist.md
+++ b/hw/ip/csrng/doc/checklist.md
@@ -115,8 +115,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [CSRNG dv document]({{<relref "hw/ip/csrng/doc/dv_doc" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Not Started | [CSRNG dv_plan]({{<relref "hw/ip/csrng/doc/dv_doc/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [CSRNG dv document]({{<relref "hw/ip/csrng/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Not Started | [CSRNG dv_plan]({{<relref "hw/ip/csrng/doc/dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Not Started |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
Testbench | [SIM_TB_ENV_CREATED][] | Not Started |
diff --git a/hw/ip/edn/doc/checklist.md b/hw/ip/edn/doc/checklist.md
index 1170115..e918a32 100644
--- a/hw/ip/edn/doc/checklist.md
+++ b/hw/ip/edn/doc/checklist.md
@@ -113,8 +113,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [EDN dv document]({{<relref "hw/ip/edn/doc/dv_doc" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Not Started | [EDN dv_plan]({{<relref "hw/ip/edn/doc/dv_doc/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [EDN dv document]({{<relref "hw/ip/edn/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Not Started | [EDN dv_plan]({{<relref "hw/ip/edn/doc/dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Not Started |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
Testbench | [SIM_TB_ENV_CREATED][] | Not Started |
diff --git a/hw/ip/entropy_src/doc/checklist.md b/hw/ip/entropy_src/doc/checklist.md
index 8794301..d2ccece 100644
--- a/hw/ip/entropy_src/doc/checklist.md
+++ b/hw/ip/entropy_src/doc/checklist.md
@@ -110,8 +110,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [ENTROPY_SRC dv document]({{<relref "hw/ip/entropy_src/doc/dv_doc" >}})
-Documentation | [DV_PLAN_COMPLETED][] | In Progress | [ENTROPY_SRC dv_plan]({{<relref "hw/ip/entropy_src/doc/dv_doc/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [ENTROPY_SRC dv document]({{<relref "hw/ip/entropy_src/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | In Progress | [ENTROPY_SRC dv_plan]({{<relref "hw/ip/entropy_src/doc/dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/flash_ctrl/doc/checklist.md b/hw/ip/flash_ctrl/doc/checklist.md
index a56f998..4c990ce 100644
--- a/hw/ip/flash_ctrl/doc/checklist.md
+++ b/hw/ip/flash_ctrl/doc/checklist.md
@@ -111,7 +111,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [flash_ctrl_dv_doc]({{<relref "dv_doc/index.md" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [flash_ctrl_dv_doc]({{<relref "dv/index.md" >}})
Documentation | [DV_PLAN_COMPLETED][] | Done |
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
diff --git a/hw/ip/gpio/doc/checklist.md b/hw/ip/gpio/doc/checklist.md
index c0876d9..b079c1f 100644
--- a/hw/ip/gpio/doc/checklist.md
+++ b/hw/ip/gpio/doc/checklist.md
@@ -137,7 +137,7 @@
Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception (Security, Power, Debug)
Review | [V2_CHECKLIST_SCOPED][] | Done |
-[gpio_dv_doc]: {{<relref "/hw/ip/gpio/doc/dv_doc/index.md">}}
+[gpio_dv_doc]: {{<relref "/hw/ip/gpio/doc/dv/index.md">}}
[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}
[DV_PLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_plan_completed" >}}
diff --git a/hw/ip/hmac/doc/checklist.md b/hw/ip/hmac/doc/checklist.md
index d759957..01b8d28 100644
--- a/hw/ip/hmac/doc/checklist.md
+++ b/hw/ip/hmac/doc/checklist.md
@@ -118,8 +118,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|----------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [hmac_dv_doc]({{<relref "dv_doc/index.md" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done |
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [hmac_dv_doc]({{<relref "dv/index.md" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done |
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
@@ -137,12 +137,12 @@
Code Quality | [TB_LINT_SETUP][] | Done |
Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A | Except for IP module
Review | [DESIGN_SPEC_REVIEWED][] | Done |
-Review | [DV_PLAN_REVIEWED][] | Done |
+Review | [DV_PLAN_REVIEWED][] | Done |
Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception (Security, Power, Debug)
Review | [V2_CHECKLIST_SCOPED][] | Done |
-[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}
-[DV_PLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_plan_completed" >}}
+[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}
+[DV_PLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_plan_completed" >}}
[TB_TOP_CREATED]: {{<relref "/doc/project/checklist.md#tb_top_created" >}}
[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#preliminary_assertion_checks_added" >}}
[SIM_TB_ENV_CREATED]: {{<relref "/doc/project/checklist.md#sim_tb_env_created" >}}
diff --git a/hw/ip/i2c/doc/checklist.md b/hw/ip/i2c/doc/checklist.md
index 1c4a3b7..109170d 100644
--- a/hw/ip/i2c/doc/checklist.md
+++ b/hw/ip/i2c/doc/checklist.md
@@ -112,8 +112,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [i2c_dv_doc]({{<relref "hw/ip/i2c/doc/dv_doc" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [i2c_dv_plan]({{<relref "hw/ip/i2c/doc/dv_doc/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [i2c_dv_doc]({{<relref "hw/ip/i2c/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [i2c_dv_plan]({{<relref "hw/ip/i2c/doc/dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/keymgr/doc/checklist.md b/hw/ip/keymgr/doc/checklist.md
index 94ca5d8..98254a7 100644
--- a/hw/ip/keymgr/doc/checklist.md
+++ b/hw/ip/keymgr/doc/checklist.md
@@ -115,8 +115,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [KEYMGR dv document]({{<relref "hw/ip/keymgr/doc/dv_doc" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [KEYMGR dv_plan]({{<relref "hw/ip/keymgr/doc/dv_doc/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [KEYMGR dv document]({{<relref "hw/ip/keymgr/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [KEYMGR dv_plan]({{<relref "hw/ip/keymgr/doc/dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/lc_ctrl/doc/checklist.md b/hw/ip/lc_ctrl/doc/checklist.md
index 20c1474..247838c 100644
--- a/hw/ip/lc_ctrl/doc/checklist.md
+++ b/hw/ip/lc_ctrl/doc/checklist.md
@@ -115,8 +115,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [LC_CTRL dv document]({{<relref "hw/ip/lc_ctrl/doc/dv_doc" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Not Started | [LC_CTRL dv_plan]({{<relref "hw/ip/lc_ctrl/doc/dv_doc/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [LC_CTRL dv document]({{<relref "hw/ip/lc_ctrl/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Not Started | [LC_CTRL dv_plan]({{<relref "hw/ip/lc_ctrl/doc/dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Not Started |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
Testbench | [SIM_TB_ENV_CREATED][] | Not Started |
diff --git a/hw/ip/otbn/doc/checklist.md b/hw/ip/otbn/doc/checklist.md
index 5f94396..06c384f 100644
--- a/hw/ip/otbn/doc/checklist.md
+++ b/hw/ip/otbn/doc/checklist.md
@@ -110,8 +110,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [OTBN dv document]({{<relref "hw/ip/otbn/doc/dv_doc" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [OTBN dv_plan]({{<relref "hw/ip/otbn/doc/dv_doc/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [OTBN dv document]({{<relref "hw/ip/otbn/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [OTBN dv_plan]({{<relref "hw/ip/otbn/doc/dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/otp_ctrl/doc/checklist.md b/hw/ip/otp_ctrl/doc/checklist.md
index 7e13ee3..32bbd47 100644
--- a/hw/ip/otp_ctrl/doc/checklist.md
+++ b/hw/ip/otp_ctrl/doc/checklist.md
@@ -115,8 +115,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [OTP_CTRL dv document]({{<relref "hw/ip/otp_ctrl/doc/dv_doc" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [OTP_CTRL dv_plan]({{<relref "hw/ip/otp_ctrl/doc/dv_doc/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [OTP_CTRL dv document]({{<relref "hw/ip/otp_ctrl/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [OTP_CTRL dv_plan]({{<relref "hw/ip/otp_ctrl/doc/dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/pattgen/doc/checklist.md b/hw/ip/pattgen/doc/checklist.md
index 82ba2e9..c78315f 100644
--- a/hw/ip/pattgen/doc/checklist.md
+++ b/hw/ip/pattgen/doc/checklist.md
@@ -112,8 +112,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [pattgen_dv_doc]({{<relref "hw/ip/pattgen/doc/dv_doc" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [pattgen_dv_plan]({{<relref "hw/ip/pattgen/doc/dv_doc/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [pattgen_dv_doc]({{<relref "hw/ip/pattgen/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [pattgen_dv_plan]({{<relref "hw/ip/pattgen/doc/dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/pwrmgr/doc/checklist.md b/hw/ip/pwrmgr/doc/checklist.md
index 6aa0f70..98de24e 100644
--- a/hw/ip/pwrmgr/doc/checklist.md
+++ b/hw/ip/pwrmgr/doc/checklist.md
@@ -110,8 +110,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [PWRMGR dv document]({{<relref "hw/top_earlgrey/doc/dv_doc/index.md" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Not Started | [PWRMGR dv_plan]()
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [PWRMGR dv document]({{<relref "hw/top_earlgrey/doc/dv/index.md" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Not Started | [PWRMGR dv_plan1]()
Testbench | [TB_TOP_CREATED][] | Not Started |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
Testbench | [SIM_TB_ENV_CREATED][] | Not Started |
diff --git a/hw/ip/usbdev/doc/checklist.md b/hw/ip/usbdev/doc/checklist.md
index e130eec..58eca13 100644
--- a/hw/ip/usbdev/doc/checklist.md
+++ b/hw/ip/usbdev/doc/checklist.md
@@ -110,8 +110,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | In Progress | [USB Device dv document]({{<relref "hw/ip/usbdev/doc/dv_doc" >}})
-Documentation | [DV_PLAN_COMPLETED][] | In Progress | [USB Device dv_plan]({{<relref "hw/ip/usbdev/doc/dv_doc/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | In Progress | [USB Device dv document]({{<relref "hw/ip/usbdev/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | In Progress | [USB Device dv_plan]({{<relref "hw/ip/usbdev/doc/dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/top_earlgrey/doc/dv_plan/index.md b/hw/top_earlgrey/doc/dv/index.md
similarity index 100%
rename from hw/top_earlgrey/doc/dv_plan/index.md
rename to hw/top_earlgrey/doc/dv/index.md
diff --git a/hw/top_earlgrey/ip/xbar/doc/checklist.md b/hw/top_earlgrey/ip/xbar/doc/checklist.md
index d07601e..261577b 100644
--- a/hw/top_earlgrey/ip/xbar/doc/checklist.md
+++ b/hw/top_earlgrey/ip/xbar/doc/checklist.md
@@ -140,7 +140,7 @@
Review | Signoff date | Done | 2019-11-04
-[DV_PLAN]: {{<relref "/hw/ip/tlul/doc/dv_doc">}}
+[DV_PLAN]: {{<relref "/hw/ip/tlul/doc/dv">}}
[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv-plan-draft-completed" >}}
[DV_PLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_plan-completed" >}}
diff --git a/util/dvsim/testplanner/README.md b/util/dvsim/testplanner/README.md
index 83fb029..8b5610e 100644
--- a/util/dvsim/testplanner/README.md
+++ b/util/dvsim/testplanner/README.md
@@ -168,7 +168,7 @@
* **`common_testplan.hjson`**: shared dv_plan imported within the DUT dv_plan
* **`foo_dv_doc.md`**: DUT dv_plan imported within the dv document doc in Markdown
-In addition, see the [UART dv document]({{< relref "hw/ip/uart/doc/dv_doc" >}}) for a
+In addition, see the [UART dv document]({{< relref "hw/ip/uart/doc/dv" >}}) for a
real 'production' example of inline expansion of an imported dv_plan as a table
within the dv document.
The [UART dv_plan](https://github.com/lowRISC/opentitan/blob/master/hw/ip/uart/data/uart_testplan.hjson)
diff --git a/util/uvmdvgen/README.md b/util/uvmdvgen/README.md
index fb356d6..cf7c50b 100644
--- a/util/uvmdvgen/README.md
+++ b/util/uvmdvgen/README.md
@@ -292,7 +292,7 @@
* `i2c_host_dv_doc.md`
This is the initial dv document that will describe the entire testbench. This
- is equivalent to the template available [here](https://github.com/lowRISC/opentitan/blob/master/hw/dv/doc/dv_doc_template.md).
+ is equivalent to the template available [here](https://github.com/lowRISC/opentitan/blob/master/hw/dv/doc/dv_template.md).
The [VLNV](https://fusesoc.readthedocs.io/en/master/user/overview.html#core-naming-rules)
name in the generated FuseSoC core files is set using the `--vendor` switch for
