[dv/alert_handler] fix alert ping timeout seq regression error
This PR fixes the timeout issue in nightly regression regarding
alert_handler_ping_timeout_vseq.
The issue is that we locked the ping_en register via regwen before
enabling the ping_en csr.
The solution is to move the order of regwen write task.
This PR also sets the min number of alert_en to be NUM_ALERTS-4 to avoid
this sequence running too long.
Signed-off-by: Cindy Chen <chencindy@opentitan.org>
diff --git a/hw/ip_templates/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv b/hw/ip_templates/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv
index c83a131..93c04e3 100644
--- a/hw/ip_templates/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv
+++ b/hw/ip_templates/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv
@@ -40,6 +40,11 @@
esc_ping_timeout == '1;
}
+ // At least enable `NUM_ALERTS-4` alerts to avoid this sequence running too long.
+ constraint enable_one_alert_c {
+ $countones(alert_en) dist {NUM_ALERTS :/ 8, [NUM_ALERTS-4 : NUM_ALERTS-1] :/ 2};
+ }
+
constraint ping_timeout_cyc_c {
ping_timeout_cyc inside {[1:MAX_PING_TIMEOUT_CYCLE]};
}
diff --git a/hw/ip_templates/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv b/hw/ip_templates/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv
index 5037753..76bced3 100644
--- a/hw/ip_templates/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv
+++ b/hw/ip_templates/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv
@@ -132,7 +132,7 @@
.loc_alert_en(local_alert_en),
.loc_alert_class(local_alert_class_map));
- // write class_ctrl and clren_reg
+ // write class_ctrl
alert_handler_rand_wr_class_ctrl(lock_bit_en);
alert_handler_wr_regwen_regs(clr_regwen, alert_regwen, local_alert_regwen, ping_timer_regwen,
class_regwen);
@@ -152,6 +152,10 @@
// when all configuration registers are set, write lock register
lock_config(do_lock_config);
+ // once all above configs are written, lock them with regwen
+ alert_handler_wr_regwen_regs(clr_regwen, alert_regwen, local_alert_regwen, ping_timer_regwen,
+ class_regwen);
+
// if config is not locked, update max_intr_timeout and max_wait_phases cycles
if (!config_locked) begin
bit [TL_DW-1:0] max_intr_timeout_cyc;
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv b/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv
index c83a131..93c04e3 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv
@@ -40,6 +40,11 @@
esc_ping_timeout == '1;
}
+ // At least enable `NUM_ALERTS-4` alerts to avoid this sequence running too long.
+ constraint enable_one_alert_c {
+ $countones(alert_en) dist {NUM_ALERTS :/ 8, [NUM_ALERTS-4 : NUM_ALERTS-1] :/ 2};
+ }
+
constraint ping_timeout_cyc_c {
ping_timeout_cyc inside {[1:MAX_PING_TIMEOUT_CYCLE]};
}
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv b/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv
index 5037753..76bced3 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv
@@ -132,7 +132,7 @@
.loc_alert_en(local_alert_en),
.loc_alert_class(local_alert_class_map));
- // write class_ctrl and clren_reg
+ // write class_ctrl
alert_handler_rand_wr_class_ctrl(lock_bit_en);
alert_handler_wr_regwen_regs(clr_regwen, alert_regwen, local_alert_regwen, ping_timer_regwen,
class_regwen);
@@ -152,6 +152,10 @@
// when all configuration registers are set, write lock register
lock_config(do_lock_config);
+ // once all above configs are written, lock them with regwen
+ alert_handler_wr_regwen_regs(clr_regwen, alert_regwen, local_alert_regwen, ping_timer_regwen,
+ class_regwen);
+
// if config is not locked, update max_intr_timeout and max_wait_phases cycles
if (!config_locked) begin
bit [TL_DW-1:0] max_intr_timeout_cyc;
