commit eda8031db20166f15bcd21f8db02129c1867dbd0
author Weicai Yang <weicai@google.com> Mon Nov 16 13:38:15 2020 -0800
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Mon Nov 23 17:14:46 2020 -0800
tree c7bf0981a9c0a4fc3c68af1bdc5cb9ea889d3fe1
parent 64566b82c56ca9ddc709fdd9ea4ba10ab40c9101

[dv/keymgr] Cleanup some warnings in xcelium

Signed-off-by: Weicai Yang <weicai@google.com>

hw/dv/tools/dvsim/xcelium.hjson

diff --git a/hw/dv/tools/dvsim/xcelium.hjson b/hw/dv/tools/dvsim/xcelium.hjson
index c61101b..b859f81 100644
--- a/hw/dv/tools/dvsim/xcelium.hjson
+++ b/hw/dv/tools/dvsim/xcelium.hjson
@@ -22,14 +22,24 @@
                "-access +rw",
                // Use this to conditionally compile for Xcelium (example: LRM interpretations differ
                // across tools).
-               "+define+XCELIUM"]
+               "+define+XCELIUM",
+               // Ignore "timescale is not specified for the package" warning
+               "-nowarn TSNSPK",
+               // Ignore "IEEE 1800-2009 SystemVerilog simulation semantics" warning
+               "-nowarn DSEMEL",
+               // Ignore hierarchial ref warnings in interfaces
+               "-nowarn CUVIHR",
+               ]
 
   run_opts:   ["-input {run_script}",
                "-licqueue",
                "-64bit -xmlibdirname {build_dir}/xcelium.d -R",
                "+SVSEED={seed}",
                "+UVM_TESTNAME={uvm_test}",
-               "+UVM_TEST_SEQ={uvm_test_seq}"]
+               "+UVM_TEST_SEQ={uvm_test_seq}",
+               // Ignore "IEEE 1800-2009 SystemVerilog simulation semantics" warning
+               "-nowarn DSEM2009",
+               ]
 
   // Vars that need to exported to the env.
   exports: [