[dv] Slightly generalise run_stress_all_with_rand_reset_vseq
This task was originally designed for running stress sequences,
selected by plusarg. More recently, we taught it to take an optional
sequence argument, which would be used instead of the stress sequence.
Tidy things up a bit, moving the generic stuff that takes a sequence
to a new task (run_seq_with_rand_reset_vseq) and putting the plusargs
handling in a wrapper task.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/dv/sv/cip_lib/doc/index.md b/hw/dv/sv/cip_lib/doc/index.md
index f693cf8..b7a5f17 100644
--- a/hw/dv/sv/cip_lib/doc/index.md
+++ b/hw/dv/sv/cip_lib/doc/index.md
@@ -221,8 +221,8 @@
response (with `d_error` = 1), but also triggers a fatal alert and updates status CSRs
such as `ERR_CODE`. The list of CSRs that are impacted by this alert event, maintained
in `cfg.tl_intg_alert_fields`, are also checked for correctness.
-* **task run_stress_all_with_rand_reset_vseq**: This task runs 3 parallel threads,
- which are ip_stress_all_vseq, run_tl_errors_vseq and reset sequence. After
+* **task run_seq_with_rand_reset_vseq**: This task runs 3 parallel threads,
+ which are a sequence provided, run_tl_errors_vseq and reset sequence. After
reset occurs, the other threads will be killed and then all the CSRs will be read
for check. This task runs multiple iterations to ensure DUT won't be broken after
reset and TL errors.
diff --git a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
index 34275ca..6822ffc 100644
--- a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
+++ b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
@@ -57,8 +57,8 @@
// mask out bits out of the csr/mem range and LSB 2 bits
bit [BUS_AW-1:0] csr_addr_mask[string];
- // This knob is used in run_stress_all_with_rand_reset_vseq to control how long we wait before
- // injecting a reset.
+ // This knob is used in run_seq_with_rand_reset_vseq to control how long we wait before injecting
+ // a reset.
rand uint rand_reset_delay;
constraint rand_reset_delay_c {
rand_reset_delay dist {
@@ -577,18 +577,29 @@
endtask
- // task to insert random reset within the input vseqs list, then check all CSR values
- virtual task run_stress_all_with_rand_reset_vseq(int num_times = 1,
- bit do_tl_err = 1,
- uint reset_delay_bound = 10_000_000,
- uvm_sequence seq = null);
+ // Run a stress sequence (chosen by plusarg) in parallel with a TL errors vseq and then suddenly
+ // inject a reset.
+ virtual task run_stress_all_with_rand_reset_vseq(int num_times);
string stress_seq_name;
- void'($value$plusargs("stress_seq=%0s", stress_seq_name));
+ int had_stress_seq_plusarg = $value$plusargs("stress_seq=%0s", stress_seq_name);
+ `DV_CHECK_FATAL(had_stress_seq_plusarg)
+
+ run_seq_with_rand_reset_vseq(create_seq_by_name(stress_seq_name), num_times);
+ endtask
+
+ // Run the given sequence and possibly a TL errors vseq (if do_tl_err is set). Suddenly inject a
+ // reset after at most reset_delay_bound cycles. When we come out of reset, check all CSR values
+ // to ensure they are the documented reset values.
+ virtual task run_seq_with_rand_reset_vseq(uvm_sequence seq,
+ int num_times = 1,
+ bit do_tl_err = 1,
+ uint reset_delay_bound = 10_000_000);
+ `DV_CHECK_FATAL(seq != null)
for (int i = 1; i <= num_times; i++) begin
bit ongoing_reset;
bit do_read_and_check_all_csrs;
- `uvm_info(`gfn, $sformatf("running run_stress_all_with_rand_reset_vseq iteration %0d/%0d",
+ `uvm_info(`gfn, $sformatf("running run_seq_with_rand_reset_vseq iteration %0d/%0d",
i, num_times), UVM_LOW)
// Arbitration: requests at highest priority granted in FIFO order, so that we can predict
// results for many non-blocking accesses
@@ -605,11 +616,8 @@
end
begin : run_stress_seq
dv_base_vseq #(RAL_T, CFG_T, COV_T, VIRTUAL_SEQUENCER_T) dv_vseq;
- if (seq == null) begin
- `downcast(dv_vseq, create_seq_by_name(stress_seq_name))
- end else begin
- `downcast(dv_vseq, seq.clone())
- end
+ `downcast(dv_vseq, seq.clone())
+
dv_vseq.do_apply_reset = 0;
dv_vseq.set_sequencer(p_sequencer);
`DV_CHECK_RANDOMIZE_FATAL(dv_vseq)
@@ -842,8 +850,8 @@
// injecting a reset. Since the IP block is otherwise quiescent, we only really care about what
// point in a TL transaction the reset occurs. Each TL transaction takes roughly 10 cycles, so
// there's no need to wait longer than 1000 cycles (which would be ~100 TL transactions).
- run_stress_all_with_rand_reset_vseq(.num_times(num_times), .do_tl_err(1),
- .reset_delay_bound(1000), .seq(cip_seq));
+ run_seq_with_rand_reset_vseq(.seq(cip_seq), .num_times(num_times), .do_tl_err(1),
+ .reset_delay_bound(1000));
endtask
virtual task run_alert_rsp_seq_nonblocking();
diff --git a/hw/dv/sv/dv_lib/dv_base_vseq.sv b/hw/dv/sv/dv_lib/dv_base_vseq.sv
index 271b770..f3ba395 100644
--- a/hw/dv/sv/dv_lib/dv_base_vseq.sv
+++ b/hw/dv/sv/dv_lib/dv_base_vseq.sv
@@ -140,7 +140,7 @@
endtask
// This is called after apply_reset in this class and after apply_resets_concurrently
- // in cip_base_vseq::run_stress_all_with_rand_reset_vseq.
+ // in cip_base_vseq::run_seq_with_rand_reset_vseq.
virtual task post_apply_reset(string reset_kind = "HARD");
endtask
