commit ec5301e7d67e020b7690a957943e6f5c31dd4436
author Michael Schaffner <msf@google.com> Mon Jul 26 17:22:32 2021 -0700
committer Michael Schaffner <msf@google.com> Tue Jul 27 10:20:31 2021 -0700
tree fb393ac0dbd2cece4309b7c05b1b6e27f251cbbf
parent d8dcf2a466cd3a35812a910c3d93786f70af2a11

[topgen] Remove hardcoded ROM memory from template

Signed-off-by: Michael Schaffner <msf@google.com>

util/topgen/templates/toplevel.sv.tpl

diff --git a/util/topgen/templates/toplevel.sv.tpl b/util/topgen/templates/toplevel.sv.tpl
index 605d2b5..fcff22f 100644
--- a/util/topgen/templates/toplevel.sv.tpl
+++ b/util/topgen/templates/toplevel.sv.tpl
@@ -395,71 +395,6 @@
 
   assign ${m["inter_signal_list"][1]["top_signame"]}_rsp.rerror = ${m["name"]}_rerror;
 
-  % elif m["type"] == "rom":
-<%
-     data_width = int(top["datawidth"])
-     full_data_width = data_width + int(m['integ_width'])
-     dw_byte = data_width // 8
-     addr_width = ((int(m["size"], 0) // dw_byte) -1).bit_length()
-     rom_depth = (int(m["size"], 0) // dw_byte)
-     max_char = len(str(max(data_width, addr_width)))
-%>\
-  // ROM device
-  logic ${lib.bitarray(1,          max_char)} ${m["name"]}_req;
-  logic ${lib.bitarray(addr_width, max_char)} ${m["name"]}_addr;
-  logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_rdata;
-  logic ${lib.bitarray(1,          max_char)} ${m["name"]}_rvalid;
-
-  tlul_adapter_sram #(
-    .SramAw(${addr_width}),
-    .SramDw(${data_width}),
-    .Outstanding(2),
-    .ErrOnWrite(1),
-    .CmdIntgCheck(1),
-    .EnableRspIntgGen(1),
-    .EnableDataIntgGen(0)
-  ) u_tl_adapter_${m["name"]} (
-    % for key in clocks:
-    .${key}   (${clocks[key]}),
-    % endfor
-    % for port, reset in resets.items():
-    .${port}   (${lib.get_reset_path(reset, m['domain'], top)}),
-    % endfor
-
-    .tl_i        (${m["name"]}_tl_req),
-    .tl_o        (${m["name"]}_tl_rsp),
-    .en_ifetch_i (tlul_pkg::InstrEn),
-    .req_o       (${m["name"]}_req),
-    .req_type_o  (),
-    .gnt_i       (1'b1), // Always grant as only one requester exists
-    .we_o        (),
-    .addr_o      (${m["name"]}_addr),
-    .wdata_o     (),
-    .wmask_o     (),
-    .intg_error_o(), // Connect to ROM checker and ROM scramble later
-    .rdata_i     (${m["name"]}_rdata[${data_width-1}:0]),
-    .rvalid_i    (${m["name"]}_rvalid),
-    .rerror_i    (2'b00)
-  );
-
-  prim_rom_adv #(
-    .Width(${full_data_width}),
-    .Depth(${rom_depth}),
-    .MemInitFile(BootRomInitFile)
-  ) u_rom_${m["name"]} (
-    % for key in clocks:
-    .${key}   (${clocks[key]}),
-    % endfor
-    % for port, reset in resets.items():
-    .${port}   (${lib.get_reset_path(reset, m['domain'], top)}),
-    % endfor
-    .req_i    (${m["name"]}_req),
-    .addr_i   (${m["name"]}_addr),
-    .rdata_o  (${m["name"]}_rdata),
-    .rvalid_o (${m["name"]}_rvalid),
-    .cfg_i    (rom_cfg_i)
-  );
-
   % elif m["type"] == "eflash":
 
   // host to flash communication