[dv] Enable top-level scb
1. enable scb
2. enable byte access for main_ram and hmac mem in top-level
3. increase xbar test to 50 seeds
Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/hw/dv/sv/cip_lib/cip_base_vseq.sv b/hw/dv/sv/cip_lib/cip_base_vseq.sv
index 041c20e..8554428 100644
--- a/hw/dv/sv/cip_lib/cip_base_vseq.sv
+++ b/hw/dv/sv/cip_lib/cip_base_vseq.sv
@@ -18,8 +18,14 @@
// user can set the name of common seq to run directly without using $value$plusargs
string common_seq_type;
+ // address mask struct
+ typedef struct packed {
+ bit [TL_AW-1:0] addr;
+ bit [TL_DBW-1:0] mask;
+ } addr_mask_t;
+
bit [TL_DW-1:0] exp_mem[int];
- int mem_exist_addr_q[$];
+ addr_mask_t mem_exist_addr_q[$];
// mem_ranges without base address
addr_range_t updated_mem_ranges[$];
@@ -501,18 +507,21 @@
tl_access(.addr(addr), .write(1), .data(data), .mask(mask), .blocking(1));
if (!cfg.under_reset) begin
+ bit [TL_DW-1:0] data_mask;
addr[1:0] = 0;
- exp_mem[addr] = data;
- mem_exist_addr_q.push_back(addr);
+ foreach (mask[i]) data_mask[i*8+:8] = {8{mask[i]}};
+ exp_mem[addr] = (exp_mem[addr] & ~data_mask) | (data & data_mask);
+ mem_exist_addr_q.push_back(addr_mask_t'{addr, mask});
end
end
end
// Randomly pick a previously written address for partial read.
exp_mem.size > 0: begin // read
// get all the programmed addresses and randomly pick one
- addr = mem_exist_addr_q[$urandom_range(0, mem_exist_addr_q.size - 1)];
- if (get_mem_access_by_addr(ral, addr) != "WO") begin;
- mask = get_rand_contiguous_mask();
+ addr_mask_t addr_mask = mem_exist_addr_q[$urandom_range(0, mem_exist_addr_q.size - 1)];
+ addr = addr_mask.addr;
+ if (get_mem_access_by_addr(ral, addr) != "WO") begin
+ mask = get_rand_contiguous_mask(addr_mask.mask);
tl_access(.addr(addr), .write(0), .data(data), .mask(mask), .blocking(1));
if (!cfg.under_reset) begin
@@ -572,10 +581,14 @@
endtask
// TLUL mask must be contiguous, e.g. 'b1001, 'b1010 aren't allowed
- virtual function bit[TL_DBW-1:0] get_rand_contiguous_mask();
+ virtual function bit[TL_DBW-1:0] get_rand_contiguous_mask(bit [TL_DBW-1:0] valid_mask = '1);
bit [TL_DBW-1:0] mask;
`DV_CHECK_STD_RANDOMIZE_WITH_FATAL(mask,
- $countones(mask ^ {mask[TL_DBW-2:0], 1'b0}) <= 2;)
+ $countones(mask ^ {mask[TL_DBW-2:0], 1'b0}) <= 2;
+ // for data bits aren't valid (unknown), mask bit should be 0
+ foreach (valid_mask[i]) {
+ !valid_mask[i] -> !mask[i];
+ })
return mask;
endfunction
diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index a174b8d..0d3720b 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -93,6 +93,7 @@
{
name: xbar_mode
run_opts: ["+xbar_mode=1"]
+ reseed: 50
}
]
diff --git a/hw/top_earlgrey/dv/env/chip_env_cfg.sv b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
index 9146695..a67141a 100644
--- a/hw/top_earlgrey/dv/env/chip_env_cfg.sv
+++ b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
@@ -58,8 +58,6 @@
chip_mem_e mems[] = {Rom, Ram, FlashBank0, FlashBank1};
has_devmode = 0;
- // TODO: may need to add scb later
- en_scb = 0;
super.initialize(csr_base_addr);
// create uart agent config obj
@@ -87,6 +85,10 @@
protected virtual function void apply_ral_fixes();
// Out of reset, the link is in disconnected state.
ral.usbdev.intr_state.disconnected.set_reset(1'b1);
+
+ // ram_main mem and hmac mem support partial write
+ ral.ram_main.set_mem_partial_write_support(1);
+ ral.hmac.msg_fifo.set_mem_partial_write_support(1);
endfunction
endclass
diff --git a/hw/top_earlgrey/dv/env/chip_scoreboard.sv b/hw/top_earlgrey/dv/env/chip_scoreboard.sv
index 7ac8759..680782a 100644
--- a/hw/top_earlgrey/dv/env/chip_scoreboard.sv
+++ b/hw/top_earlgrey/dv/env/chip_scoreboard.sv
@@ -49,6 +49,11 @@
end
endtask
+ // TODO, may add some checking later
+ virtual task process_tl_access(tl_seq_item item, tl_channels_e channel = DataChannel);
+ return;
+ endtask
+
virtual function void reset(string kind = "HARD");
super.reset(kind);
// reset local fifos queues and variables
