[ spi_host, doc] Initial spec draft Signed-off-by: Martin Lueker-Boden <martin.lueker-boden@wdc.com>
diff --git a/hw/ip/spi_host/data/spi_host.hjson b/hw/ip/spi_host/data/spi_host.hjson index 30c7828..b19ee99 100644 --- a/hw/ip/spi_host/data/spi_host.hjson +++ b/hw/ip/spi_host/data/spi_host.hjson
@@ -1,57 +1,542 @@ // Copyright lowRISC contributors. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -{ name: "SPI_HOST", +{ name: "spi_host", clock_primary: "clk_i", + other_clock_list: [ "clk_core_i" ], + reset_primary: "rst_ni", + other_reset_list: [ "rst_core_ni" ], bus_device: "tlul", - available_input_list: [ + bus_host: "none", + regwidth: "32", + param_list: [ + { name: "ByteOrder", + desc: '''Byte order to use when transmitting or receiving data. If ByteOrder = 0, + the IP uses a Big-Endian ordering for the bytes in TXDATA and RXDATA. + The most significant byte (MSB) of TXDATA is transmitted first, and + received data is placed in the MSB location of RXDATA. If ByteOrder = 1, + a Little-Endian ordering is used for these registers, and the LSB of each + gets priority for receiving and transmitting data.''' + type: "int", + default: "0" + }, + { name: "MaxCS", + desc: "The number of active-low chip select (cs_n) lines to create.", + type: "int", + default: "1" + }, ], available_output_list: [ - { name: "sck", desc: "SPI Clock" }, - { name: "csb", desc: "Chip Enable#" }, + { name: "sck" + desc: "SPI Clock" + }, + { name: "csb" + desc: '''Chip Select# (One hot, active low). The size of this port should match MaxCS.''' + width: "1" + } ], available_inout_list: [ - { name: "sd", width: 4, desc: "SPI In/Out ports" }, + { name: "sd", + desc: "SPI data bus", + width: "4" + }, ], - scan: "true", // Enable `scanmode_i` port - regwidth: "32", + interrupt_list: [ + { name: "error", + desc: '''Error-related interrupts, see !!ERROR_ENABLE register for more + information.''' + }, + { name: "spi_event", + desc: '''Event-related interrupts, see !!EVENT_ENABLE register for more + information.''' + } + ], registers: [ { name: "CONTROL", desc: "Control register", swaccess: "rw", - hwaccess: "hrw", + hwaccess: "hro", fields: [ - { bits: "3:0", - name: "data", - desc: '''This is a dummy register - ''' + { bits: "31", + name: "SPIEN", + desc: '''Enables the SPI host. On reset, this field is 0, meaning + that no transactions can proceed.''' + resval: "0x0" + }, + { bits: "30", + name: "RST_FSM", + desc: '''Holds the control FSM in reset when set to 1. (Must be + explicitly cleared again before commands can be issued.)''' + resval: "0x0", + }, + { bits: "29", + name: "RST_TXFIFO", + desc: '''Holds the TX FIFO in reset when set to 1. (Must be explicitly + cleared again before using the TX FIFO.)''' + resval: "0x0", + }, + { bits: "28", + name: "RST_RXFIFO", + desc: '''Holds the RX FIFO in reset when set to 1. (Must be explicitly + cleared again before using the RX FIFO.)''' + resval: "0x0" + }, + { bits: "27", + name: "PASSTHRU", + desc: '''Enables Pass-through mode, wherein the SPI_HOST IP surrenders + control of the SPI bus to another block. In this mode the + `sck`, `cs_n` and `sd` signals are no longer driven by + the SPI_HOST IP, rather they are multiplexed out to match the + on-chip inputs `pt_sck_i`, `pt_cs_n_i`, `pt_sden_i`, `pt_sdo_i`, + and `pt_sdi_o`. (Since the `sd` bus is bidirectional, there are + separate input, output and tri-state controls for this bus.)''', + resval: "0x0" + }, + { bits: "24:16", + name: "TX_WATERMARK" + desc: '''If !!EVENT_ENABLE.TXWM is set, the IP will send + an interrupt when the depth of the RX FIFO drops below + TX_WATERMARK words (32b each).''' resval: "0" }, - { bits: "4", - name: "sck", - desc: '''This is a dummy register - ''' - resval: "0" + { bits: "15:9", + name: "RX_WATERMARK" + desc: '''If !!EVENT_ENABLE.RXWM is set, the IP will send + an interrupt when the depth of the RX FIFO reaches + RX_WATERMARK words (32b each).''' + resval: "127" }, - { bits: "5", - name: "csb", - desc: '''This is a dummy register - ''' - resval: "0" + { bits: "8", + name: "MANCS_EN", + desc: '''Enable Manual Chip Select. Typically each command + manages the CS lines automatically, issuing a command + to exactly one device, and lowering and raising the + appropriate CS line after transmitting or receiving the + necessary bytes. Asserting this bit overrides this + automatic selection, instead setting the CS lines to + reflect the contents of the !!CONTROL.MANUAL_CS field.''' + resval: "0x0" }, - { bits: "6", - name: "dir", - desc: '''This is a dummy register - ''' - resval: "0" + { bits: "7:0", + name: "MANUAL_CS" + desc: '''When !!CONTROL.MANCS_EN = 1, the cs_n lines are tied directly to the + value of MANUAL_CS.''' + resval: 0 + } + ] + }, + { name: "STATUS", + desc: "Status register", + swaccess: "ro", + hwaccess: "hwo", + fields: [ + { bits: "31", + name: "READY", + desc: '''When high, indicates the SPI host is ready to receive + commands. Writing a one to !!COMMAND_0.GO when READY is low is + an error, and will trigger an interrupt. + ''', + resval: "0x0" + }, + { bits: "30", + name: "ACTIVE", + desc: '''When high, indicates the SPI host is processing a previously + issued command.''' + resval: "0x0" + }, + { bits: "29", + name: "TXFULL", + desc: '''When high, indicates that the transmit data fifo is full. + Any further writes to !!TXDATA will create an error interrupt. + ''' + resval: "0x0" + }, + { bits: "28", + name: "TXEMPTY", + desc: '''When high, indicates that the transmit data fifo is empty. + ''' + resval: "0x0" + }, + { bits: "27" + name: "TXSTALL", + desc: '''If high, signifies that an ongoing transaction has stalled + due to lack of data in the TX FIFO''', + resval: "0x0" + }, + { bits: "26", + name: "TXWM", + desc: '''If high, the amount of data in the TX FIFO has fallen below the + level of !!CONTROL.TX_WATERMARK words (32b each).''' + resval: "0x0" + }, + { bits: "25", + name: "RXFULL", + desc: '''When high, indicates that the receive fifo is full. Any + ongoing transactions will stall until firmware reads some + data from !!RXDATA.''' + resval: "0x0" + }, + { bits: "24", + name: "RXEMPTY", + desc: '''When high, indicates that the receive fifo is empty. + Any reads from RX FIFO will cause an error interrupt. + ''' + resval: "0x0" + }, + { bits: "23", + name: "RXSTALL", + desc: '''If high, signifies that an ongoing transaction has stalled + due to lack of available space in the RX FIFO''', + resval: "0x0" + }, + { bits: "22", + name: "BYTEORDER", + desc: '''The value of the ByteOrder parameter, provided so that firmware + can confirm proper IP configuration.''' + } + { bits: "20", + name: "RXWM", + desc: '''If high, the number of 32-bits in the RX FIFO now exceeds the + !!CONTROL.RX_WATERMARK entries (32b each).''' + resval: "0x0" + }, + { bits: "17:9", + name: "RXQD", + desc: '''Receive queue depth. Indicates how many unread entries are currently in the + RX FIFO. When active, this result may an underestimate due + to synchronization delays. + ''', + resval: "0x0" + }, + { bits: "8:0", + name: "TXQD", + desc: '''Transmit queue depth. Indicates how many unsent entries are currently + in the TX FIFO. When active, this result may be an + over-estimate due to synchronization delays, + ''', + resval: "0x0" + } + ] + }, + { multireg: { name: "CONFIGOPTS", + desc: '''Configuration options register. + + Contains options for controlling each peripheral. One register per + cs_n line''', + swaccess: "rw", + hwaccess: "hro", + cname: "configopts", + count: "MaxCS", + fields: [ + { bits: "31", + name: "CPOL", + desc: '''The polarity of the sck clock signal. When CPOL is 0, + sck is low when idle, and emits high pulses. When CPOL + is low, sck is high when idle, and emits a series of low + pulses. + ''' + resval: "0x0" + }, + { bits: "30", + name: "CPHA", + desc: '''The phase of the sck clock signal relative to the data. When + CPHA = 0, the data changes on the trailing edge of sck + and is typically sampled on the leading edge. Conversely + if CPHA = 1 high, data lines change on the leading edge of + sck and are typically sampled on the trailing edge. + CPHA should be chosen to match the phase of the selected + device. The sampling behavior is modified by the + !!CONFIGOPTS_0.FULLCYC bit. + ''', + resval: "0x0" + }, + { bits: "29", + name: "FULLCYC", + desc: '''Full cycle. Modifies the CPHA sampling behaviour to allow + for longer device logic setup times. Rather than sampling the SD + bus a half cycle after shifting out data, the data is sampled + a full cycle after shifting data out. This means that if + CPHA = 0, data is shifted out on the trailing edge, and + sampled a full cycle later. If CPHA = 1, data is shifted and + sampled with the trailing edge, also separated by a + full cycle.''', + resval: 0 + }, + { bits: "28", + name: "CSAAT", + desc: '''Chip select active after transaction. If CSAAT = 0, the + chip select line is raised immediately at the end of the + transaction. If CSAAT = 1, the chip select line is left + low at the end of the current sequence. This potentially + allows for the creation of longer or otherwise more + complex sequences.''' + resval: "0x0" + }, + { bits: "27:24", + name: "CSNLEAD", + desc: '''CS_N Leading Time. Indicates the number of half sck cycles, + CSNLEAD+1, to leave between the falling edge of cs_n and + the first edge of sck. Setting this register to zero + corresponds to the minimum delay of one-half sck cycle''' + resval: 0 + }, + { bits: "23:20", + name: "CSNTRAIL" + desc: '''CS_N Trailing Time. Indicates the number of half sck cycles, + CSNTRAIL+1, to leave between last edge of sck and the rising + edge of cs_n. Setting this register to zero corresponds + to the minimum delay of one-half sck cycle.''' + resval: 0 + }, + { bits: "19:16", + name: "CSNIDLE" + desc: '''Minimum idle time between commands. Indicates the minimum + number of sck half-cycles to hold cs_n high between commands. + Setting this register to zero creates a minimally-wide CS_N-high + pulse of one-half sck cycle.''' + resval: 0 + }, + { bits: "15:0", + name: "CLKDIV", + desc: '''Core clock divider. Slows down subsequent SPI transactions by a + factor of (CLKDIV+1) relative to the core clock frequency. The + period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)`''' + resval: 0 + }, + ] + } + }, + { multireg: { name: "COMMAND", + desc: '''Command Register + + Parameters specific to each command. One register per cs_n line''', + swaccess: "rw", + hwaccess: "hro", + hwqe: "true", + cname: "command", + count: "MaxCS", + fields: [ + { bits: "3:0", + name: "TX1_CNT", + desc: '''The number of 1-byte bursts to transmit in this command, + at the single-line data width (8 sck clocks per cycle). + All other data lines are high-Z during this command phase. + This field is ignored in full-duplex standard-mode + (i.e. when !!COMMAND_0.FULLDPLX = 1 and !!COMMAND_0.SPEED = 0). + ''', + resval: "0x0" + }, + { bits: "12:4", + name: "TXN_CNT", + desc: '''The number of 1-byte bursts to transmit in this command, + at the full-data width (Determined by the !!COMMAND_0.SPEED + field). + ''', + resval: "0x0" + }, + { bits: "16:13", + name: "DUMMY_CYCLES", + desc: '''Controls the number of sck dummy cycles inserted between + end of the last TX byte and the beginning of the first RX + byte. No data is transmitted or received and all outputs + are high-Z during this command phase. + This field is ignored in full-duplex standard-mode + (i.e. when !!COMMAND_0.FULLDPLX = 1 and !!COMMAND_0.SPEED = 0). + ''', + resval: "0x0" + }, + { bits: "25:17", + name: "RX_CNT", + desc: '''In Dual or Quad mode, this is the number of 1-byte bursts + to receive in this command. + This field is ignored in full-duplex standard-mode + (i.e. when !!COMMAND_0.FULLDPLX = 1 and !!COMMAND_0.SPEED = 0). + ''', + resval: "0x0" + }, + { bits: "26", + name: "FULLDPLX", + desc: '''Allows full-duplex operation for this command. In full-duplex + mode, !!COMMAND_0.TXN_CNT bytes are transmitted on 'sd[0]' and + and the same number of bytes are received on 'sd[1]'. This + flag only applies if !!COMMAND_0.SPEED = 0.''', + resval: "0x0" + }, + { bits: "27", + name: "HIGHZ", + desc: '''Forces high-impendance when not transmitting. Typically Standard + Mode commands exclusively transmit on sd[0], and receive on sd[1]. + The sd[1] line is always high-impedance, but for half-duplex commands + the sd[0] line is typically held low during dummy and receive cycles. + This bit forces the sd[0] to high-impedance during dummy and receive + cycles.''', + resval: "0x0" + }, + { bits: "30:29", + name: "SPEED", + desc: '''The speed for the following command: "0" = Standard SPI. "1" = Dual SPI. + "2"=Quad SPI, "3": RESERVED.''', + resval: "0x0" + }, + { bits: "31", + name: "GO", + hwaccess: "hrw", + desc: '''Writing a one to this field finalizes the command and submits it to the SPI_HOST core. + This field is self-clearing, so each write to this field only triggers one command.''' + resval: "0x0", + tags: [// Updated by the hw. Exclude from write-checks. + "excl:CsrNonInitTests:CsrExclWriteCheck"] + } + ] + } + }, + { window: { + name: "TXDATA", + items: "1", + validbits: "32", + byte-write: "true", + desc: '''SPI Transmit Data. + + The serial order of bit transmission + is chosen to match SPI flash devices. Individual bytes + are always transmitted with the most significant bit first. + Multi-byte writes are also supported, and if ByteOrder = 0, + the bits of !!TXDATA are transmitted strictly in order of + decreasing signficance (i.e. most signicant bit first). + For some processor architectures, this could lead to shuffling + of flash data as compared to how it is written in memory. + In which case, choosing ByteOrder = 1 can reverse the + byte-order of multi-byte data writes. (Though within + each byte the most significant bit is always sent first.) + ''' + swaccess: "wo", + unusual: "false" + } + }, + { name: "RXDATA", + desc: '''SPI Receive Data. + + Received data is expected in the same + order used for the !!TXDATA register. Each individual byte + is expected to arrive most-significant bit first. If + ByteOrder = 0, the first byte received will be transferred to + RXDATA[31:24], and following bytes will be stored in + decreasing byte order. If ByteOrder = 1, incoming bytes will be + stored in the reverse order.''', + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "31:0", + name: "data", + resval: "0x0", + desc: "Data Received" + } + ] + }, + { name: "ERROR_ENABLE", + desc: "Controls which classes of errors raise an interrupt." + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", + name: "CMDERR", + desc: '''Command Error: If this bit is set, the block sends an error + interrupt whenever a command is issued (i.e. a 1 is + written to COMMAND.GO) while STATUS.READY is + not asserted.''', + resval: "0x1" + }, + { bits: "1", + name: "OVERFLOW", + desc: '''Overflow Errors: If this bit is set, the block sends an + error interrupt whenever the TX FIFO overflows.''' + resval: "0x1" + }, + { bits: "2", + name: "UNDERFLOW", + desc: '''Underflow Errors: If this bit is set, the block sends an + error interrupt whenever there is a read from !!RXDATA + but the RX FIFO is empty.''' + resval: "0x1" }, ] - // This is a dummy register in order to - // connect some logic to the TL-UL bus. - // Do not write to or read from this reg - // until this has been replaced by correctly - // behaving logic. - tags: ["excl:CsrAllTests:CsrExclAll"] }, + { name: "ERROR_STATUS", + desc: '''Indicates that any errors that have occurred. + + When an error + occurs, the corresponding bit must be cleared here before + issuing any further commands.''' + swaccess: "rw1c", + hwaccess: "hwo", + fields: [ + { bits: "0", + name: "CMDERR", + desc: '''Indicates a write to !!COMMAND_0.GO when + !!STATUS.READY = 0. + ''' + resval: "0x0" + }, + { bits: "1", + name: "OVERFLOW", + desc: '''Indicates that firmware has overflowed the TX FIFO''' + resval: "0x0" + }, + { bits: "2", + name: "UNDERFLOW", + desc: '''Indicates that firmware has attempted to read from + !!RXDATA when the RX FIFO is empty.''', + resval: "0x0" + }, + ] + }, + { name: "EVENT_ENABLE", + desc: "Controls which classes of SPI events raise an interrupt.", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "2", + name: "RXFULL", + desc: '''Assert to send a spi_event interrupt whenever !!STATUS.RXFULL + goes high''', + resval: "0x0" + }, + { bits: "3", + name: "TXEMPTY", + desc: '''Assert to send a spi_event interrupt whenever !!STATUS.TXEMPTY + goes high''', + resval: "0x0" + }, + { bits: "4", + name: "RXWM", + desc: '''Assert to send a spi_event interrupt whenever the number of 32-bit words in + the RX FIFO is greater than !!CONTROL.RX_WATERMARK. To prevent the + reassertion of this interrupt, read more data from the RX FIFO, or + increase !!CONTROL.RX_WATERMARK.''', + resval: "0x0" + }, + { bits: "5", + name: "TXWM", + desc: '''Assert to send a spi_event interrupt whenever the number of 32-bit words in + the TX FIFO is less than !!CONTROL.TX_WATERMARK. To prevent the + reassertion of this interrupt add more data to the TX FIFO, or + reduce !!CONTROL.TX_WATERMARK.''', + resval: "0x0" + }, + { bits: "6", + name: "READY", + desc: '''Assert to send a spi_event interrupt whenever !!STATUS.READY + goes high''', + resval: "0x0" + }, + { bits: "7", + name: "IDLE", + desc: '''Assert to send a spi_event interrupt whenever !!STATUS.ACTIVE + goes low''', + resval: "0x0" + } + ] + } ] }
diff --git a/hw/ip/spi_host/doc/_index.md b/hw/ip/spi_host/doc/_index.md new file mode 100644 index 0000000..6842e76 --- /dev/null +++ b/hw/ip/spi_host/doc/_index.md
@@ -0,0 +1,552 @@ +--- +title: "SPI_HOST HWIP Technical Specification" +--- + +# Overview + +This document specifies SPI_HOST hardware IP (HWIP) functionality. +This module conforms to the [Comportable guideline for peripheral functionality.]({{< relref "doc/rm/comportability_specification/index.md" >}}) +See that document for integration overview within the broader top-level system. + +## Features + +- Hardware control for remote devices using the Serial Peripheral Interface (SPI) +- Primarily designed for serial NOR flash devices such as the [Winbond W25Q01JV](https://www.winbond.com/resource-files/W25Q01JV%20SPI%20RevB%2011132019.pdf) +- Number of chip select lines controlled by `MaxCS` parameter +- Support for Standard SPI, Dual SPI or Quad SPI commands + - Pins `sd[0]` through `sd[3]` are intended to connect to lines IO<sub>0</sub> through IO<sub>3</sub> respectively, on the target device. + - Pin `sd[0]` may also be identified as "MOSI" by other SPI Hosts, while `sd[1]` is commonly referred to as "MISO" +- RX and TX data held in separate FIFOs + - 288 bytes for TX data, 256 bytes for RX data + - FIFOs loaded/unloaded via 32-bit TL-UL registers + - Support for arbitrary byte-count in each transaction + - Parametrizable support for Big- or Little-Endian systems in ordering I/O bytes within 32-bit words. +- SPI clock rate controlled by separate input clock to core + - SPI `sck` line typically toggles at 1/2 the core clock frequency + - An additional clock rate divider exists to reduce the frequency if needed +- Support for all SPI polarity and phases (CPOL, CPHA) + - Additional support for "Full-cycle" SPI transactions, wherein data can be read a full SPI Clock cycle after the active edge (as opposed to one half cycle as is typical for SPI interfaces) +- Single Transfer Rate (STR) only (i.e. data received on multiple lines, but only on one clock edge) + - *No support* for Dual Transfer Rate (DTR) +- Pass-through mode for coordination with [SPI_DEVICE IP]({{< relref "hw/ip/spi_device/doc/_index.md" >}}) +- Automatic or manual control of chip select lines +- Condensed interrupt footprint: Two lines for two distinct interrupt classes: "error" and "spi_event" + - Fine-grain interrupt masking supplied by secondary enable registers + +## Description + +The Serial Peripheral Interface (SPI) is a synchronous serial interface quite commonly used for NOR flash devices as well as a number of other off-chip peripherals such as ADC's, DAC's, or temperature sensors. +The interface is a *de facto* standard (not a formal one), and so there is no definitive reference describing the interface, or establishing compliance criteria. + +It is therefore important to consult the data sheets for the desired peripheral devices in order to ensure compatibility. +For instance, this OpenTitan SPI Host IP is primarily designed for controlling Quad SPI NOR flash devices, such as the [W25Q01JV Serial NOR flash from Winbond](https://www.winbond.com/resource-files/W25Q01JV%20SPI%20RevB%2011132019.pdf) or this [1 Gb M25QL NOR flash from Micron](https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_l_01g_bbb_0.pdf?rev=43d124f03bbf4ef0962435e9ec63a185). +Though this IP implementation aims to be general enough to support a variety of devices, the Winbond serial flash device is used as the primary reference for understanding our host requirements. + +There are also a number of good references describing legacy host implementations for this protocol, which are useful for understanding some of the general needs for a wider range of target devices. +For instance, the legacy [SPI Block Guide](https://web.archive.org/web/20150413003534/http://www.ee.nmt.edu/~teare/ee308l/datasheets/S12SPIV3.pdf) from Motorola contains a definitive overview of some of the the general requirements for a standard SPI host, notably the definitions of SPI clock phase and polarity (CPOL and CPHA). +In order to potentially support a broad range of devices, this SPI Host IP also supports all four of the standard SPI clock phases. + +### SPI Protocol Basics + +Broadly speaking, the SPI host accepts commands from the TL-UL interface and, based on these commands, serially transmits and receives data on the external SPI interface pins. +The timing and data-line formatting of the command sequence depend on the external peripheral device and the nature of the specific command issued. + +In each standard SPI command a number of instruction-, address- or data-bytes are transmitted on `sd[0]`, and response bytes are received on `sd[1]`. +So in standard-mode commands, `sd[0]` is always configured as an output, and `sd[1]` is always an input. +In standard SPI commands the `sd[0]` and `sd[1]` lines can be used as a full-duplex communication channel. +Not all devices exploit this capability, opting instead to have clear input and output phases for each command. +This half-duplex signaling behavior is especially common in devices with also support Dual- and Quad-mode commands, which are always half-duplex. +The SPI_HOST IP optionally supports both full-duplex and half-duplex commands in standard mode. + +Along with the data lines, the SPI protocol also includes a chip select line, commonly called CS\#, or in this IP we refer to it as `cs_n`. +The SPI bus can be connected to many target peripherals, but each device on the bus gets its own chip select line, and so this active-low signal designates a particular device for each command. + +The chip-select line also marks the beginning and end of each command. +No device will accept any command input until `cs_n` has been asserted for that device, and most devices (if not all) do not accept a second command unless `cs_n` has been deasserted to mark the end of the previous command. +Some simple devices, particularly those that support SPI daisy-chaining, do not process command input at all until *after* the `cs_n` line has been deasserted. +In the case of NOR flash devices, read and write commands are indeterminate in length, and the data transfer ends only when the `cs_n` line is deasserted. +So, though the exact details of operation may vary from device to device, the edges of the `cs_n` signal serve as an important markers for delineating the boundaries of each transaction. + +The `sd` and `cs_n` lines are accompanied by a serial clock, `sck`. +The host is responsible for generating the serial clock, and typically each side asserts outgoing data on one edge of the clock (e.g. on the rising edge) and samples data in the next edge (e.g. on the falling edge). +When it comes to devices there is no universal convention on clock polarity (CPOL) or clock phase (CPHA). +Some devices expect the clock line to be low when the host is idle, thus the clock should come as a sequence of positive pulses (CPOL = 0). +On the other hand, other devices expect CPOL = 1, meaning that the clock line is inverted: *high* when idle with sequences of *negative* pulses. + +Devices also differ in their expectations of clock *phase* (CPHA) relative to the data. +Devices with CPHA = 0, expect that both the host and device will be sampling data on the *leading* edge, and asserting data on the *trailing* edge. +(Because of the option for either polarity, the terms "leading" and "trailing" are preferred to "rising" or "falling"). +When CPHA = 0, the first output bit is asserted with the falling edge of `cs_n`. +Meanwhile if CPHA = 1, data is always is asserted on the leading edge of `sck`, and data is always sampled on the trailing edge of sck. + +When operating at the fastest-rated clock speeds, some flash devices (i.e. both the Winbond and Micron devices noted above), require setup times which exceed half a clock-cycle. +In order to support these fastest data rates, the SPI_HOST IP offers a modified "Full-cycle" (FULLCYC = 1) timing mode where data can be sampled a *full* cycle after the target device asserts data on the `sd` bus. +This full cycle mode has no effect on any of the signals transmitted, only on the timing of the sampling of the incoming signals. + +{{< wavejson >}} +{signal: [ + {name: "clk_core_i", wave: "p.................."}, + {name: "sck (CPOL=0)", wave: "0.1010101010101010."}, + {name: "sck (CPOL=1)", wave: "1.0101010101010101."}, + {name: "cs_n", wave: "10................1"}, + ["CPHA = 0", + {name: "sd[0] (output)", wave: "22.2.2.2.2.2.2.2...", data: ["","out7", "out6", "out5", "out4", "out3", "out2", "out1", "out0" ]}, + {name: "sd[1] (input)", wave: "22.2.2.2.2.2.2.2.2.", data: ["","in7", "in6", "in5", "in4", "in3", "in2", "in1", "in0",""]}, + {name: "Sampling Event (FULLCYC=0)", wave: "1.H.H.H.H.H.H.H.H.."}, + {name: "Sampling Event (FULLCYC=1)", wave: "1..H.H.H.H.H.H.H.H."}, + ], + ["CPHA = 1", + {name: "sd[0] (output)", wave: "2.2.2.2.2.2.2.2.2..", data: ["","out7", "out6", "out5", "out4", "out3", "out2", "out1", "out0" ]}, + {name: "sd[1] (input)", wave: "2.2.2.2.2.2.2.2.2.2", data: ["","in7", "in6", "in5", "in4", "in3", "in2", "in1", "in0",""]}, + {name: "Sampling Event (FULLCYC=0)", wave: "1..H.H.H.H.H.H.H.H."}, + {name: "Sampling Event (FULLCYC=1)", wave: "1...H.H.H.H.H.H.H.H"}, + ], +], + head: { + text: "Standard SPI transaction (1 byte) illustrating of the impact of the CPOL, CPHA, and FULLCYC settings" + }, + foot: { + } +} +{{< /wavejson >}} + +As mentioned earlier, the `sd[0]` and `sd[1]` lines are unidirectional in Standard SPI mode. +On the other hand in the faster Dual- or Quad-modes, all data lines are bidirectional, and in Quad mode the number of data lines increases to four. +For the purposes of this IP, Dual or Quad-mode commands can be thought of as consisting of up to four command phases in which the host: +1. Transmits instructions or data at single-line rate, +2. Transmits instructions address or data on 2 or 4 data lines, +3. Holds the bus in a high-impedance state for some number of "dummy" clock cycles (neither side transmits), or +4. Receives information from the target device. + +This four phase command scheme is also applied to half-duplex interactions when in standard mode. + +{{< wavejson >}} +{signal: [ + {name: "clk_core_i", wave: "p.............................."}, + {name: "sck (CPOL=0)", wave: "0.1010101010101010101010101010."}, + {name: "cs_n", wave: "10............................1"}, + {name: "sd[0]", wave: "22.2.2.2.2.2.2.2.2.2.z...2.2.x.", data: ["","cmd7", "cmd6", "cmd5", "cmd4", "cmd3", "cmd2", "cmd1", "cmd0", + "out4", "out0", "in4", "in0" ]}, + {name: "sd[1]", wave: "z................2.2.z...2.2.x.", data: ["out5", "out1", "in5", "in1"]}, + {name: "sd[2]", wave: "z................2.2.z...2.2.x.", data: ["out6", "out2", "in6", "in2"]}, + {name: "sd[3]", wave: "z................2.2.z...2.2.x.", data: ["out7", "out3", "in7", "in3"]}, + {name: "Transaction phase:", wave: "x2...............3...4...5...x.", data: ['TX1', 'TXn', 'Dummy','RX'] }, + {name: "Sampling Event (FULLCYC=0)", wave: "1.........................H.H.."}, + {name: "Sampling Event (FULLCYC=1)", wave: "1..........................H.H."}, +], + head: { + text: "Example Quad SPI transaction: 1 byte TX (Single), 1 byte (Quad), 2 dummy cycles and 1 RX byte with CPHA=0" + }, +} +{{< /wavejson >}} + +For even faster transfer rates, some flash chips support double transfer rate (DTR) variations to the SPI protocol wherein the device receives and transmits fresh data on *both* the leading and trailing edge. +This IP only supports single transfer rate (STR), *not* DTR. +A preliminary investigation of DTR transfer mode suggests that proper support for setup and hold times in this mode may require a level of sub-cycle timing control which is not currently planned for this IP. + +# Theory of Operations + +**TODO**: Review text for accuracy after review updates. + +## SPI_HOST IP Command Interface + +Issuing a command generally consists of the following steps: +1. Configure the IP to be compatible with the target peripheral. +The {{< regref "CONFIGOPTS_0" >}} multi-register has one set of configuration settings for each `cs_n` line. +2. Load the instructions and data to be transmitted into the TXFIFO via the {{< regref "TXDATA" >}} register, +3. Issue a 32-bit command to the appropriate Command multi-register (e.g. for controlling the device on `cs_n[0]` use {{< regref "COMMAND_0" >}}). +Each command register has the following information, + - The speed to use, {{< regref "COMMAND_0.SPEED_0" >}}, for this particular command (Standard, Dual, or Quad) + - The number of bytes to transmit at *reduced* data rate, {{<regref "COMMAND_0.TX1_CNT_0" >}}, using `sd[0]` only + - This field is specifically intended for Dual or Quad commands where the first instruction must be sent serially on `sd[0]` + - The number of bytes to transmit at full data rate, {{< regref "COMMAND_0.TXN_CNT_0" >}} + - The number of dummy `sck` cycles to wait before reading data, {{< regref "COMMAND_0.DUMMY_CYCLES_0" >}} + - The number of bytes to receive at the full Dual or Quad rate, {{< regref "COMMAND_0.RX_CNT_0" >}} +4. Read the peripheral response from the {{< regref "RXDATA" >}} register. + +### Configuration options + +The {{< regref "CONFIGOPTS_0" >}} multi-register has one entry per `cs_n` line and holds clock configuration and timing settings which are specific to each peripheral. +Once the {{< regref "CONFIGOPTS_0" >}} multi-register has been programed for each SPI peripheral device, the values can be left unchanged. + +The following sections give details on how the SPI_HOST can be used to control a specific peripheral. +For simplicity, this section decribes how to interact one device, attached to `cs_n[0]`, and as such references are made to the multi-registers {{< regref "CONFIGOPTS_0" >}} and {{< regref "COMMAND_0" >}}. +To configure timing and send commands to devices on other `cs_n` lines, instead use the `COMMAND` and `CONFIGOPTS` multi-registers corresponding to desired `cs_n` line. + +The most common differences between target devices are the requirements for a specific SPI clock phase or polarity, CPOL and CPHA, which were described in the previous section [SPI Protocol Basics](#spi-protocol-basics). +These clock parameters can be set via the {{< regref "CONFIGOPTS_0.CPOL_0">}} or {{< regref "CONFIGOPTS_0.CPHA_0" >}} register fields. +Likewise, as also described in the previous section, if device setup times require a full clock cycle before sampling the output, Full-Cycle Mode can be enabled by asserting the {{< regref "CONFIGOPTS_0.FULLCYC_0" >}} bit. + +#### Clock rate selection + +The SPI clock rate for each peripheral is set by two factors: +- The SPI_HOST core clock (which may be generated independently from the TL-UL interface clock) +- An additional 16-bit clock divider + +The SPI protocol usually requires activity (either sampling or asserting data) on either edge of the `sck` clock. +For this reason the maximum `sck` frequency is at most one half the SPI_HOST core frequency. +In order to support a broader range of SPI clock frequencies, the SPI_HOST core operates on a separate clock domain, which may be independent from the TL-UL bus clock. +This arrangement allows gives more flexibility in setting the serial clock frequency by means of an external PLL, and in principle the sck frequency could even be configured to *exceed* the bus clock. +For example, if the TL-UL bus is operating at 100MHz, a 200MHz SPI core clock can be fed to the SPI_HOST IP, in order to acheive data rates of 100 MTransfers/s (near the maximum clock rate of the Winbond flash device). + +Since some peripheral devices attached to the same SPI_HOST may require different clock frequencies, there is also the option to divide the core clock by an additional factor when dealing with slower peripherals. + +$$T_\textrm{sck,0}=\frac{1}{2}\frac{T_\textrm{core}}{\textrm{CONFIGOPTS_0.CLKDIV}+1}$$ + +Alternatively, this clock-divide feature can also be used to entirely bypass the need for an independent core clock. +Instead the core can be driven by the TL-UL bus clock, and the `sck` period can be adjusted using the {{< regref CONFIGOPTS_0.CLKDIV_0 >}} setting. + +#### Chip-select timing control + +Typically the `cs_n` line is automatically deasserted after the last edge of `sck`. +However, by asserting {{< regref "CONFIGOPTS_0.CSAAT_0" >}} before issuing a particular command, one can instruct the core to hold `cs_n` low indefinitely after the last clock edge. +This is useful for merging two adjacent commands together, to create very long commands such as continuous read operations. +The `cs_n` line can then be deasserted by either issuing another command after clearing the {{< regref "CONFIGOPTS_0.CSAAT_0" >}} field, issuing a command to a different device (using a different `COMMAND` register), or simply resetting the core FSM via the {{< regref "CONTROL.RST_FSM">}} register. + +Most devices require at least one-half `sck` clock-cycle between either edge of `cs_n` and the nearest `sck` edge. +However, some devices may require more timing margin and so the SPI_HOST core offers some configuration registers for controlling the timing of the `cs_n` edges when operating under automatic control. +The relevant parameters are as follows: +- T<sub>IDLE</sub>: The minimum time between each rising edge of `cs_n` and the following falling edge. +This time delay is a half `sck` cycle by default but can be extended to as long as eight `sck` cycles by setting the {{< regref "CONFIGOPTS_0.CSNIDLE_0">}} register. +- T<sub>LEAD</sub>: The minimum time between each falling edge of `cs_n` and the first leading edge of `sck`. +This time delay is a half `sck` cycle by default but can be extended to as long as eight `sck` cycles by setting the {{< regref "CONFIGOPTS_0.CSNLEAD_0">}} register. +- T<sub>TRAIL</sub>: The minimum time between the last trailing edge of `sck` and the following rising edge of `cs_n`. +This time delay is a half `sck` cycle by default but can be extended to as long as eight `sck` cycles by setting the {{< regref "CONFIGOPTS_0.CSNTRAIL_0">}} register. + +{{< wavejson >}} +{signal: [ + {name: "sck", wave: "l....1010|10........"}, + {name: "cs_n", wave: "10.......|.....1...0", node: ".A...B.....C...D...E"} +], + edge: ["A<->B minimum (CSNLEAD+1)", "C<->D minimum (CSNTRAIL+1)", "D<->E minimum (CSNIDLE+1)"], + head: { + text: "Impact of CSNLEAD, CSNTRAIL and CSNIDLE CONFIGOPTS register settings", + tick: 1 + }, + foot: { + text: ["tspan", "All ticks are in units of ½T", + ["tspan", {'baseline-shift':'sub'}, "sck"], + "=½T", + ["tspan", {'baseline-shift':'sub'}, "core"], + "×(CLKDIV+1)"] + } +} +{{< /wavejson >}} + +These settings are all minimum bounds, and delays in the FSM implementation may create more margin in each of these timing constraints. + +### Special Command Fields + +The {{< regref "COMMAND_0" >}} register must be written every time a command is issued. +Whenever a `1` is written to {{< regref "COMMAND_0.GO_0" >}}, the contents of the {{< regref "CONFIGOPTS_0" >}} and {{< regref "COMMAND_0" >}} registers are passed through the Config/Command CDC to the SPI_HOST core FSM, along with a Chip Select mask signal, indicating which device should receive the command (for example `cs_n[0]`) +Once the command is issued, the core will immediately deassert {{< regref "STATUS.READY" >}}, and once the command has started {{< regref "STATUS.ACTIVE" >}} will go high. +The {{< regref "STATUS.ACTIVE" >}} line takes a few cycles to assert, due to CDC delays. +The command is complete when {{< regref "STATUS.ACTIVE" >}} goes low. +A `spi_event` interrupt can also be triggered to go off on completion by setting {{< regref "EVENT_ENABLE.IDLE" >}}. + +### Chip Select Masks + +Each instance of the SPI_HOST IP supports a parametrizable number of chip select lines (`cs_n[MaxCS-1:0]`). +Each `cs_n` line can be routed either to a single peripheral or to a daisy-chain of peripherals. +Whenever a 1 is written to one of the the `GO` bits in the `COMMAND` multiregister, a `cs_n` mask is sent (along with the `COMMAND` and `CONFIGOPTS` multi-register data for that line) to indicate which device is meant to receive the command. +The SPI_HOST core typically then manages the details of asserting and deasserting the proper `cs_n` line, subject to the timing parameters expressed in {{< regref "CONFIGOPTS_0.CSAAT_0" >}}, {{< regref "CONFIGOPTS_0.CSNLEAD_0" >}}, {{< regref "CONFIGOPTS_0.CSNTRAIL_0" >}}, and {{< regref "CONFIGOPTS_0.CSNIDLE_0" >}}. + +Alternatively the `cs_n` lines can be controlled entirely by firmware. +If the register {{< regref "CONTROL.MANCS_EN" >}} is set high then the `cs_n` lines are directly controlled by the {{< regref "CONTROL.MANUAL_CS" >}} register. + +If [Pass-through mode](#pass-through-mode) is enabled then the `cs_n` lines are controlled by *neither* the SPI_HOST hardware nor the firmware register. +In Pass-though mode, control of the `cs_n` lines passes directly to the inter-module port, `pt_cs_ni`. + +### Arbitrary Length Commands + +Typically the length of each command is limited by the maximum number of bits in the {{< regref "COMMAND_0.TXN_CNT_0" >}}, {{< regref "COMMAND_0.RX_CNT_0" >}}, and {{< regref "COMMAND_0.TX1_CNT_0" >}} fields. +However, a series of SPI_HOST IP commands can be merged into one long command sequence using the {{< regref "CONFIGOPTS_0.CSAAT_0" >}} field, which leaves the `cs_n` line low after the first SPI_HOST command. +By raising the `cs_n` line only after the last command has completed, the peripheral will interpret the resulting transmit/receive sequences as one long command. + +### Back-to-back Commands + +There is no command queue in the SPI_HOST IP. +However a second command can be placed into the Config/Command CDC whenever {{< regref "STATUS.READY" >}} is high, even if the previous command is still running. +The internal state within the Config/Command CDC provides the option of scheduling a second command to execute immediately after completion of the current command. + +On the other hand, writing a one to {{< regref "COMMAND_0.GO_0" >}} (or any `GO` bit in this multi-register) when {{< regref "STATUS.READY" >}} is low will trigger an error condition, which must be acknowledged by software. + +## Data Formatting (Placeholder) + +**Section moved to PR #5149** + +## Pass-through Mode + +The SPI_HOST also supports a special "Pass-through" mode, which allows for the direct control of the serial interface by another block (namely SPI_DEVICE). + +To enable this mode, one sets {{< regref "CONTROL.PASSTHRU" >}} to one. + +A multiplexor then configures the output signals `cio_sck_o` and `cio_cs_no` to directly match the inter-module signals `pt_sck_i` and `pt_cs_ni[MaxCS-1:0]`. +Likewise the bidirectional port-control `cio_sd_o[3:0]` and `cio_sdt_t[3:0]` are then respectively driven by inter-module signals `cio_sdo_i[3:0]` and `cio_sdi_o[3:0]`. +Meanwhile the peripheral data input signal `cio_sdo_o[3:0]` is always connected to the inter-module `pt_sdi_o[3:0]`. + +## Interrupt aggregation + +In order to reduce the total number of interrupts in the system, the SPI_HOST has only two interrupt lines: `error` and `spi_event`. +Within these two interrupt classes, there are a number of conditions which can trigger them. + +Each interrupt class has a secondary status and mask register, to control which sub-classes of SPI events will cause an interrupt. + +### SPI Events and Event Interrupts + +The SPI_HOST supports interrupts for the following SPI events: + +- `IDLE`: The SPI_HOST is idle. +- `READY`: The SPI_HOST is ready to accept a new command. +- `RXFULL`: The SPI_HOST has run out of room in the RXFIFO. +- `RXWM`: The number of 32-bit words in the RXFIFO currently exceeds the value set in {{< regref "CONTROL.RX_WATERMARK" >}}. +- `TXEMPTY`: The SPI_HOST has transmitted all the data in the TX FIFO. +- `TXWM`: The number of 32-bit words in the TX FIFO currently is currently less than the value set in {{< regref "CONTROL.TX_WATERMARK" >}} + +Most SPI events signal a particular condition that persists until it is fixed, and these conditions can be detected by polling the corresponding field in the {{< regref "STATUS" >}} register. + +In addition to these events, there are also two additional diagnostic fields in the {{< regref "STATUS" >}} register: +- `RXSTALL`: The RXFIFO is full, and the SPI HOST is stalled and waiting for firmware to remove some data. +- `TXSTALL`: The TX FIFO is not only empty, but the SPI HOST is stalled and waiting for firmware to add more data. + +These bits can provide diagnostic data for tuning the throughput of the device, but do not themselves generate event interrupts. + +By default none of these SPI events trigger an interrupt. +They need to be enabled by writing to the corresponding field in {{< regref "EVENT_ENABLE" >}}. + +The SPI event interrupt is signaled only when the IP enters the corresponding state. +For example if an interrupt is requested when the TX FIFO is empty, the IP will only generate one interrupt when the last data word is transmitted from the TX FIFO. +In this case, no new interrupts will be created until more data has been added to the FIFO, and all of it has been transmitted. + +### Error Interrupt Conditions + +An error interrupt is usually caused by a violation of the SPI_HOST programming model: +- If {{< regref "COMMAND_0.GO_0" >}} is asserted when {{< regref "STATUS.READY">}} is zero, the IP will assert {{< regref "ERROR_STATUS.CMDERR" >}}. +- The IP asserts {{< regref "ERROR_STATUS.OVERFLOW" >}} if it receives a write to {{< regref "TXDATA" >}} when the TX FIFO is full. +- Ihe IP asserts {{< regref "ERROR_STATUS.UNDERFLOW" >}} if it software attempts to read {{< regref "RXDATA" >}} when the RXFIFO is empty. + +By default all of these programming violations will cause an `error` interrupt when they occur. +They will also halt the IP until the corresponding bit is cleared in the {{< regref "ERROR_STATUS" >}} register. + + +Each of these errors can be optionally ignored by clearing the corresponding bit in {{< regref "ERROR_ENABLE" >}}. +Clearing an error-enable bit will suppress interrupts for that class of violation and will allow the IP to proceed even if one of these errors has occurred. +The {{< regref "ERROR_STATUS" >}} register will continue to report all of these violations even if one of the corresponding bits in {{< regref "ERROR_ENABLE" >}} is zero. + +The {{< regref "ERROR_STATUS" >}} bit should be cleared *before* clearing the error interrupt in the {{< regref "INTR_STATE" >}} register. +Failure do to so may result in a repeated interrupt. + +## Status Indicators + +*TODO:* TXDQ and RXDQ + +## Other Registers + +### SPI_HOST Enable + +The SPI_HOST state machine is disabled on reset. +Before any commands are processed, the block must be enabled by writing one to the {{< regref "CONTROL.SPIEN" >}} register. +Writing a zero to this register temporarily suspends any previously submitted transactions. +If the block is re-enabled by writing a one to {{< regref "CONTROL.SPIEN" >}}, any previously executing commands will continue from wherever they left off. + +An unacknowledged error interrupt will also suspend the core state machine. + +### Component reset + +In addition to the global hardware reset, there are three software reset options. +- The main control FSM can be held in reset by writing a one to {{< regref "CONTROL.RST_FSM" >}}. +This can be used to cancel a previous command. +- The TX FIFO can be cleared by writing a one to {{< regref "CONTROL.RST_TXFIFO">}} +- The RXFIFO can be cleared by writing a one to {{< regref "CONTROL.RST_RXFIFO">}} + +## Block Diagram + + + +## Hardware Interfaces + +{{< hwcfg "hw/ip/spi_host/data/spi_host.hjson" >}} + +## Design Details + +### Component Overview. + +**TODO** High level introductory description of +- Control FSM +- SDQ Shift register +- Byte Select +- Byte Merge +- TX FIFO and RXFIFO interfaces + +### Command and Config CDC + + +Highlights for this unit: +- New commands can always be written to {{< regref "COMMAND_0" >}} or {{< regref "CONFIGOPTS_0" >}} +- It is an error however to write a one to {{< regref "COMMAND_0.GO" >}} unless {{< regref "STATUS.READY" >}} is one. +- The {{< regref "COMMAND_0.GO" >}} bit triggers a four-phase synchronizer, which copies the relevant multi-registers and `cs_n` masks to `coreCmdConf`. +- {{<regref "STATUS.READY" >}} is low while this synchronizer is in operation +- The core FSM is responsible for issuing the `cc_ack` signal. +- `coreCmdCnf` is only updated and acknowledged (using `cc_ack`) when the FSM is not busy. + +{{< wavejson >}} +{ signal: [ + {name: "clk", wave: "p..............................."}, + {name: "READY", wave: "1.0..........1|.0..|...........1"}, + {name: "COMMAND, CONFIGOPTS", wave: "x3............|4...|............"}, + {name: "GO.q && GO.qe", wave: "010...........|10..|............"}, + {name: "cc_req", wave: "01.....0......|1...|.....0......"}, + {name: "cc_req_syncd", wave: "0..1.....0....|..1.|.......0...."}, + {name: "cc_ack", wave: "0...1.....0...|....|..1.....0..."}, + {name: "cc_ack_ayncd", wave: "0.....1.....0.|....|....1.....0."}, + {name: "core_cmd_cnf", wave: "x...3.........|....|..4........."}, + {name: "core_active", wave: "0...1.........|....|.01........."}, +], + head: {text: 'Command and Config Synchronizer Operation'}, + foot: {text: "Synchronizer delay uncertainties are not illustrated."} +} +{{< /wavejson >}} + +### Shift Register + +{{< wavejson >}} +{signal: [ + {name: "clk_core_i", wave: "p.........................."}, + {name: "txfifo.out[31:0]", wave: "2..........................", data:"0x123456XX"}, + {name: "bytesel.out[7:0]", wave: "2..2...............2.......", data:["0x12", "0x34", "0x56"]}, + {name: "cio_sck_o", wave: "0...1010101010101010101010."}, + {name: "cio_cs_no[0]", wave: "1..0......................."}, + {name: "cio_sd_i[1]", wave: "x..1.1.0.0.1.1.1.1.0.1.0.1."}, + {name: "sd_i_q[1]", wave: "x...1.1.0.0.1.1.1.1.0.1.0.1"}, + {name: "shiftreg.sample", wave: "0..101010101010101010101010"}, + {name: "shiftreg.shift", wave: "0...10101010101010..1010101"}, + {name: "shiftreg.wr_en", wave: "0.10..............10......."}, + {name: "shiftref.rd_en", wave: "0.................10......."}, + {name: "shiftreg.mode", wave: "2..........................", data: ["0"]}, + {name: "shiftreg.q[0]", wave: "x..0.1.1.0.0.1.1.1.0.1.0.1."}, + {name: "shiftreg.q[1]", wave: "x..1.0.1.1.0.0.1.1.0.0.1.0."}, + {name: "shiftreg.q[2]", wave: "x..0.1.0.1.1.0.0.1.1.0.0.1."}, + {name: "shiftreg.q[3]", wave: "x..0.0.1.0.1.1.0.0.0.1.0.0."}, + {name: "shiftreg.q[4]", wave: "x..1.0.0.1.0.1.1.0.1.0.1.0."}, + {name: "shiftreg.q[5]", wave: "x..0.1.0.0.1.0.1.1.1.1.0.1."}, + {name: "shiftreg.q[6]", wave: "x..0.0.1.0.0.1.0.1.0.1.1.0."}, + {name: "shiftreg.q[7]", wave: "x..0.0.0.1.0.0.1.0.0.0.1.1."}, + {name: "shiftreg.q (hex)", wave: "x..4.2.2.2.2.2.2.2.4.2.2.2.", + data: ["0x12", "0x25", "0x4B", "0x96", "0x2c", "0x59", "0xB3", "0x67", "0x34", "0x69", "0xD2", "0xA5"]}, + {name: "bytemerge.in[7:0]", wave: "x..................2.......", data: ["0xcf"]}, + {name: "cio_sd_o[0] (shiftreg.q[7])", wave: "x..0.0.0.1.0.0.1.0.0.0.1.1."}, +], +edge: [], + head: { + text: "Standard SPI transaction, showing simultaneous receipt and transmission of data." + }, + foot: { + } +} +{{< /wavejson >}} + +#### Standard mode + +#### Dual mode + +#### Quad mode + +### Byte Select + +The Byte Select, or `bytesel`, unit is responsible for unpacking data from the FIFO to it can be loaded into the shift register + +**TODO:** For simplicity move `ByteOrder` control to be between TXFIFO/TXDATA and between RXFIFO/RXDATA. + +{{< wavejson >}} +{signal: [ + {name: "clk_core_i", wave: "p......................"}, + {name: "txfifo.out[31:0]", wave: "x2.............x.......", data: ['0xDAD5F00D']}, + {name: "txfifo.empty", wave: "10.............1......."}, + {name: "txfifo.rd_en",wave: "0.............10......."}, + {name: "bytesel.q[31:0]", wave:"2..............2.......", data: ['0xBEADCAFE', '0xDAD5F00D']}, + {name: "bytesel.almost_empty", wave: "0..........1...0......."}, + {name: "bytesel.empty", wave: "0......................"}, + ['Big-Endian mode', + {name: "bytesel.idx[1:0]", wave: "2..2...2...2...2...2...", data: [3, 2, 1, 0, 3, 2]}, + {name: "bytesel.out[7:0]", wave: "2..2...2...2...2...2...", data: ['0xBE', '0xAD', '0xCA', '0xFE', '0xDA', '0xD5']}, + {name: "shiftreg.wr_en", wave: "0.10..10..10..10..10..1"}, + {name: "shiftreg.shift", wave: "0...10..10..10..10..10."}, + {name: "shiftreg.q[7:0]", wave: "4..2.2.2.2.2.2.2.2.2.2.", data: ['','0xBE', '0xEX', '0xAD', '0xDX', '0xCA', '0xAX', '0xFE', '0xEX','0xDA', '0xAX']}, + {name: "sd[0:3] (*)", wave: "4..2.2.2.2.2.2.2.2.2.2.", data: ['','B','E','A','D','C','A','F','E', 'D','A']}, + +], + ['Little-Endian mode', + {name: "bytesel.idx[1:0]", wave: "2..2...2...2...2...2...", data: [0, 1, 2, 3, 0, 1]}, + {name: "bytesel.out[7:0]", wave: "2..2...2...2...2...2...", data: ['0xFE', '0xCA', '0xAD', '0xBE', '0x0D', '0xF0']}, + {name: "shiftreg.wr_en", wave: "0.10..10..10..10..10..1"}, + {name: "shiftreg.shift", wave: "0...10..10..10..10..10."}, + {name: "shiftreg.q[7:0]", wave: "4..2.2.2.2.2.2.2.2.2.2.", data: ['','0xFE', '0xEX', '0xCA', '0xAX', '0xAD', '0xDX', '0xBE', '0xEX','0x0D', '0xDX']}, + {name: "sd[0:3] (*)", wave: "4..2.2.2.2.2.2.2.2.2.2.", data: ['','F','E','C','A','A','D','B','E','0','D']}, +], +], + head: { + text: "Processing of TX FIFO data as a function of the ByteOrder parameter (0: BE, 1: LE)" + }, + foot: { + text: "*Note bit-ordering for the sd bus. For Dual and Quad mode commands, sd[0] is always the MSB." + } +} +{{< /wavejson >}} + +### Byte Merge + +{{< wavejson >}} +{signal: [ + {name: "clk_core_i", wave: "p......................"}, + + {name: "sd[0:3] (*)", wave: "2.2.2.2.2.2.2.2.2.2.2.2", data: ['B','E','A','D','C','A','F','E','D','A', 'D', '5']}, + {name: "shiftreg.sample", wave: "10101010101010101010101"}, + {name: "shiftreg.q[7:0]", wave: "42.2.2.2.2.2.2.2.2.2.2.", data:["X","0xXB", "0xBE", "0xEA", "0xAD","0xDC","0xCA","0xAF","0xFE","0xED", "0xDA", "0xAD"]}, + {name: "bytemerge.rd_en", wave: "0..10..10..10..10..10.."}, + {name: "bytemerge.almost_full", wave: "0...........1...0......"}, + ['BE', + {name: "bytemerge.idx", wave:"2...2...2...2...2...2..", data: [3,2,1,0, 3, 2]}, + {name: "rxfifo.data_in[31:0]", wave:"2...2...2...2...2...2..", data: ["0xXXXXXXXX","0xBEXXXXXX","0xBEADXXXX", "0xBEADCAXX", "0xBEADCAFE", "0xDAADCAFE"]}, + ], + ['LE', + {name: "bytemerge.idx", wave:"2...2...2...2...2...2..", data: [0,1,2,3,0,1]}, + {name: "rxfifo.data_in[31:0]", wave:"2...2...2...2...2...2..", data: ["0xXXXXXXXX","0xXXXXXXBE","0xXXXXADBE", "0xXXCAADBE", "0xFECAADBE", "0xFECAADAD"]}, + ], + + {name: "rxfifo.wr_en", wave: "0...............10....."}, + {name: "rxfifo.full", wave: "0......................"} + ], + head: { + text: "Collection of RXFIFO data as a function of ByteOrder parameter" + }, + foot: { + text: "*Note bit-ordering for the sd bus. For Dual and Quad mode commands, sd[0] is always contains the MSB." + } +} +{{< /wavejson >}} + +#### End of Command + +#### RXFIFO Full or TX FIFO Empty + +### Config/Command CDC + +### Passthrough Mode Multiplexors + +# Programmer's Guide + +**TODO**. (Outline Below) + +## Basic Configuration + +## Issuing a Standard SPI command + +## Issuing a Dual or Quad SPI command + +### Instruction code sent at Standard SPI bit width + +### All Bytes Sent at Dual or Quad Rate + +## Register Table + +{{< registers "hw/ip/spi_host/data/spi_host.hjson" >}} \ No newline at end of file
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diff --git a/hw/ip/spi_host/rtl/spi_host.sv b/hw/ip/spi_host/rtl/spi_host.sv index fdd89dd..534c8f6 100644 --- a/hw/ip/spi_host/rtl/spi_host.sv +++ b/hw/ip/spi_host/rtl/spi_host.sv
@@ -8,31 +8,45 @@ `include "prim_assert.sv" -module spi_host ( - input clk_i, - input rst_ni, +module spi_host + import spi_host_reg_pkg::*; +#( + parameter int ByteOrder = 0, + parameter int MaxCS = 1 +) ( + input clk_i, + input rst_ni, + input clk_core_i, + input rst_core_ni, - input lc_ctrl_pkg::lc_tx_t scanmode_i, + input lc_ctrl_pkg::lc_tx_t scanmode_i, // Register interface - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, // SPI Interface - output logic cio_sck_o, - output logic cio_sck_en_o, - output logic cio_csb_o, - output logic cio_csb_en_o, - output logic [3:0] cio_sd_o, - output logic [3:0] cio_sd_en_o, - input [3:0] cio_sd_i + output logic cio_sck_o, + output logic cio_sck_en_o, + output logic [MaxCS-1:0] cio_csb_o, + output logic [MaxCS-1:0] cio_csb_en_o, + output logic [3:0] cio_sd_o, + output logic [3:0] cio_sd_en_o, + input [3:0] cio_sd_i, + + output logic intr_error_o, + output logic intr_spi_event_o ); - import spi_host_reg_pkg::*; + wire event_spi_event = 1'b0; + wire event_error = 1'b0; spi_host_reg2hw_t reg2hw; spi_host_hw2reg_t hw2reg; + tlul_pkg::tl_h2d_t txfifo_win_h2d [1]; + tlul_pkg::tl_d2h_t txfifo_win_d2h [1]; + // Register module spi_host_reg_top u_reg ( .clk_i, @@ -41,6 +55,9 @@ .tl_i (tl_i), .tl_o (tl_o), + .tl_win_o (txfifo_win_h2d), + .tl_win_i (txfifo_win_d2h), + .reg2hw, .hw2reg, @@ -48,25 +65,96 @@ ); // Some dummy connections - assign cio_sd_o = (reg2hw.control.dir.q) ? reg2hw.control.data.q : '0; - assign cio_sd_en_o = (reg2hw.control.dir.q) ? reg2hw.control.data.q : '0; - assign hw2reg.control.data.d = (!reg2hw.control.dir.q) ? cio_sd_i : '0; - assign hw2reg.control.data.de = (!reg2hw.control.dir.q) ? 1'b1 : 1'b0; + assign cio_sck_o = '0; + assign cio_sck_en_o = '1; + assign cio_csb_o = {MaxCS{'0}}; + assign cio_csb_en_o = {MaxCS{'1}}; + assign cio_sd_o = 4'h0; + assign cio_sd_en_o = 4'h0; - assign cio_sck_o = reg2hw.control.sck.q; - assign cio_sck_en_o = reg2hw.control.sck.q; - assign cio_csb_o = reg2hw.control.csb.q; - assign cio_csb_en_o = reg2hw.control.csb.q; + assign hw2reg.status.txqd.d = 9'h0; + assign hw2reg.status.txqd.de = 1'b0; + assign hw2reg.status.rxqd.d = 9'h0; + assign hw2reg.status.rxqd.de = 1'b0; + assign hw2reg.status.rxwm.d = 1'b0; + assign hw2reg.status.rxwm.de = 1'b0; + assign hw2reg.status.byteorder.d = 1'b0; + assign hw2reg.status.byteorder.de = 1'b0; + assign hw2reg.status.rxstall.d = 1'b0; + assign hw2reg.status.rxstall.de = 1'b0; + assign hw2reg.status.rxempty.d = 1'b0; + assign hw2reg.status.rxempty.de = 1'b0; + assign hw2reg.status.rxfull.d = 1'b0; + assign hw2reg.status.rxfull.de = 1'b0; + assign hw2reg.status.txwm.d = 1'b0; + assign hw2reg.status.txwm.de = 1'b0; + assign hw2reg.status.txstall.d = 1'b0; + assign hw2reg.status.txstall.de = 1'b0; + assign hw2reg.status.txempty.d = 1'b0; + assign hw2reg.status.txempty.de = 1'b0; + assign hw2reg.status.txfull.d = 1'b0; + assign hw2reg.status.txfull.de = 1'b0; + assign hw2reg.status.active.d = 1'b0; + assign hw2reg.status.active.de = 1'b0; + assign hw2reg.status.ready.d = 1'b0; + assign hw2reg.status.ready.de = 1'b0; + for(genvar ii = 0; ii < MaxCS; ii++) begin : go_bit_tie_offs + assign hw2reg.command[ii].go.d = 1'b0; + assign hw2reg.command[ii].go.de = 1'b0; + end + assign txfifo_win_d2h[0].d_valid = 1'b0; + assign txfifo_win_d2h[0].d_opcode = tlul_pkg::AccessAck; + assign txfifo_win_d2h[0].d_param = 3'h0; + assign txfifo_win_d2h[0].d_size = {top_pkg::TL_SZW{1'b0}}; + assign txfifo_win_d2h[0].d_source = {top_pkg::TL_AIW{1'b0}}; + assign txfifo_win_d2h[0].d_sink = {top_pkg::TL_DIW{1'b0}}; + assign txfifo_win_d2h[0].d_data = {top_pkg::TL_DW{1'b0}}; + assign txfifo_win_d2h[0].d_user = {top_pkg::TL_DUW{1'b0}}; + assign txfifo_win_d2h[0].d_error = 1'b0; + assign txfifo_win_d2h[0].a_ready = 1'b0; + assign hw2reg.rxdata.d = 32'h0; + assign hw2reg.error_status.cmderr.d = 1'b0; + assign hw2reg.error_status.cmderr.de = 1'b0; + assign hw2reg.error_status.overflow.d = 1'b0; + assign hw2reg.error_status.overflow.de = 1'b0; + assign hw2reg.error_status.underflow.d = 1'b0; + assign hw2reg.error_status.underflow.de = 1'b0; - logic unused_sigs; - assign unused_sigs = ^scanmode_i; + prim_intr_hw #(.Width(1)) intr_hw_spi_event ( + .clk_i, + .rst_ni, + .event_intr_i (event_spi_event), + .reg2hw_intr_enable_q_i (reg2hw.intr_enable.spi_event.q), + .reg2hw_intr_test_q_i (reg2hw.intr_test.spi_event.q), + .reg2hw_intr_test_qe_i (reg2hw.intr_test.spi_event.qe), + .reg2hw_intr_state_q_i (reg2hw.intr_state.spi_event.q), + .hw2reg_intr_state_de_o (hw2reg.intr_state.spi_event.de), + .hw2reg_intr_state_d_o (hw2reg.intr_state.spi_event.d), + .intr_o (intr_spi_event_o) + ); - // Tie offs - assign hw2reg.control.dir.d = 1'b0; - assign hw2reg.control.dir.de = 1'b0; - assign hw2reg.control.sck.d = 1'b0; - assign hw2reg.control.sck.de = 1'b0; - assign hw2reg.control.csb.d = 1'b0; - assign hw2reg.control.csb.de = 1'b0; + prim_intr_hw #(.Width(1)) intr_hw_error ( + .clk_i, + .rst_ni, + .event_intr_i (event_error), + .reg2hw_intr_enable_q_i (reg2hw.intr_enable.error.q), + .reg2hw_intr_test_q_i (reg2hw.intr_test.error.q), + .reg2hw_intr_test_qe_i (reg2hw.intr_test.error.qe), + .reg2hw_intr_state_q_i (reg2hw.intr_state.error.q), + .hw2reg_intr_state_de_o (hw2reg.intr_state.error.de), + .hw2reg_intr_state_d_o (hw2reg.intr_state.error.d), + .intr_o (intr_error_o) + ); + + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) + `ASSERT_KNOWN(CioSckKnownO_A, cio_sck_o) + `ASSERT_KNOWN(CioSckEnKnownO_A, cio_sck_en_o) + `ASSERT_KNOWN(CioCsbKnownO_A, cio_csb_o) + `ASSERT_KNOWN(CioCsbEnKnownO_A, cio_csb_en_o) + `ASSERT_KNOWN(CioSdKnownO_A, cio_sd_o) + `ASSERT_KNOWN(CioSdEnKnownO_A, cio_sd_en_o) + `ASSERT_KNOWN(IntrSpiEventKnownO_A, intr_spi_event_o) + `ASSERT_KNOWN(IntrErrorKnownO_A, intr_error_o) endmodule : spi_host
diff --git a/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv b/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv index 17b9be2..66837e5 100644 --- a/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv +++ b/hw/ip/spi_host/rtl/spi_host_reg_pkg.sv
@@ -6,73 +6,341 @@ package spi_host_reg_pkg; + // Param list + parameter int ByteOrder = 0; + parameter int MaxCS = 1; + // Address width within the block - parameter int BlockAw = 2; + parameter int BlockAw = 6; //////////////////////////// // Typedefs for registers // //////////////////////////// typedef struct packed { struct packed { - logic [3:0] q; - } data; + logic q; + } error; struct packed { logic q; - } sck; + } spi_event; + } spi_host_reg2hw_intr_state_reg_t; + + typedef struct packed { struct packed { logic q; - } csb; + } error; struct packed { logic q; - } dir; + } spi_event; + } spi_host_reg2hw_intr_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } error; + struct packed { + logic q; + logic qe; + } spi_event; + } spi_host_reg2hw_intr_test_reg_t; + + typedef struct packed { + struct packed { + logic [7:0] q; + } manual_cs; + struct packed { + logic q; + } mancs_en; + struct packed { + logic [6:0] q; + } rx_watermark; + struct packed { + logic [8:0] q; + } tx_watermark; + struct packed { + logic q; + } passthru; + struct packed { + logic q; + } rst_rxfifo; + struct packed { + logic q; + } rst_txfifo; + struct packed { + logic q; + } rst_fsm; + struct packed { + logic q; + } spien; } spi_host_reg2hw_control_reg_t; + typedef struct packed { + struct packed { + logic [15:0] q; + } clkdiv; + struct packed { + logic [3:0] q; + } csnidle; + struct packed { + logic [3:0] q; + } csntrail; + struct packed { + logic [3:0] q; + } csnlead; + struct packed { + logic q; + } csaat; + struct packed { + logic q; + } fullcyc; + struct packed { + logic q; + } cpha; + struct packed { + logic q; + } cpol; + } spi_host_reg2hw_configopts_mreg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + logic qe; + } tx1_cnt; + struct packed { + logic [8:0] q; + logic qe; + } txn_cnt; + struct packed { + logic [3:0] q; + logic qe; + } dummy_cycles; + struct packed { + logic [8:0] q; + logic qe; + } rx_cnt; + struct packed { + logic q; + logic qe; + } fulldplx; + struct packed { + logic q; + logic qe; + } highz; + struct packed { + logic [1:0] q; + logic qe; + } speed; + struct packed { + logic q; + logic qe; + } go; + } spi_host_reg2hw_command_mreg_t; + + typedef struct packed { + struct packed { + logic q; + } cmderr; + struct packed { + logic q; + } overflow; + struct packed { + logic q; + } underflow; + } spi_host_reg2hw_error_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + } rxfull; + struct packed { + logic q; + } txempty; + struct packed { + logic q; + } rxwm; + struct packed { + logic q; + } txwm; + struct packed { + logic q; + } ready; + struct packed { + logic q; + } idle; + } spi_host_reg2hw_event_enable_reg_t; + typedef struct packed { struct packed { - logic [3:0] d; + logic d; logic de; - } data; + } error; struct packed { logic d; logic de; - } sck; + } spi_event; + } spi_host_hw2reg_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic [8:0] d; + logic de; + } txqd; + struct packed { + logic [8:0] d; + logic de; + } rxqd; struct packed { logic d; logic de; - } csb; + } rxwm; struct packed { logic d; logic de; - } dir; - } spi_host_hw2reg_control_reg_t; + } byteorder; + struct packed { + logic d; + logic de; + } rxstall; + struct packed { + logic d; + logic de; + } rxempty; + struct packed { + logic d; + logic de; + } rxfull; + struct packed { + logic d; + logic de; + } txwm; + struct packed { + logic d; + logic de; + } txstall; + struct packed { + logic d; + logic de; + } txempty; + struct packed { + logic d; + logic de; + } txfull; + struct packed { + logic d; + logic de; + } active; + struct packed { + logic d; + logic de; + } ready; + } spi_host_hw2reg_status_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } go; + } spi_host_hw2reg_command_mreg_t; + + typedef struct packed { + logic [31:0] d; + } spi_host_hw2reg_rxdata_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } cmderr; + struct packed { + logic d; + logic de; + } overflow; + struct packed { + logic d; + logic de; + } underflow; + } spi_host_hw2reg_error_status_reg_t; /////////////////////////////////////// // Register to internal design logic // /////////////////////////////////////// typedef struct packed { - spi_host_reg2hw_control_reg_t control; // [6:0] + spi_host_reg2hw_intr_state_reg_t intr_state; // [117:116] + spi_host_reg2hw_intr_enable_reg_t intr_enable; // [115:114] + spi_host_reg2hw_intr_test_reg_t intr_test; // [113:110] + spi_host_reg2hw_control_reg_t control; // [109:80] + spi_host_reg2hw_configopts_mreg_t [0:0] configopts; // [79:48] + spi_host_reg2hw_command_mreg_t [0:0] command; // [47:9] + spi_host_reg2hw_error_enable_reg_t error_enable; // [8:6] + spi_host_reg2hw_event_enable_reg_t event_enable; // [5:0] } spi_host_reg2hw_t; /////////////////////////////////////// // Internal design logic to register // /////////////////////////////////////// typedef struct packed { - spi_host_hw2reg_control_reg_t control; // [10:0] + spi_host_hw2reg_intr_state_reg_t intr_state; // [85:82] + spi_host_hw2reg_status_reg_t status; // [81:40] + spi_host_hw2reg_command_mreg_t [0:0] command; // [39:38] + spi_host_hw2reg_rxdata_reg_t rxdata; // [37:6] + spi_host_hw2reg_error_status_reg_t error_status; // [5:0] } spi_host_hw2reg_t; // Register Address - parameter logic [BlockAw-1:0] SPI_HOST_CONTROL_OFFSET = 2'h 0; + parameter logic [BlockAw-1:0] SPI_HOST_INTR_STATE_OFFSET = 6'h 0; + parameter logic [BlockAw-1:0] SPI_HOST_INTR_ENABLE_OFFSET = 6'h 4; + parameter logic [BlockAw-1:0] SPI_HOST_INTR_TEST_OFFSET = 6'h 8; + parameter logic [BlockAw-1:0] SPI_HOST_CONTROL_OFFSET = 6'h c; + parameter logic [BlockAw-1:0] SPI_HOST_STATUS_OFFSET = 6'h 10; + parameter logic [BlockAw-1:0] SPI_HOST_CONFIGOPTS_OFFSET = 6'h 14; + parameter logic [BlockAw-1:0] SPI_HOST_COMMAND_OFFSET = 6'h 18; + parameter logic [BlockAw-1:0] SPI_HOST_RXDATA_OFFSET = 6'h 20; + parameter logic [BlockAw-1:0] SPI_HOST_ERROR_ENABLE_OFFSET = 6'h 24; + parameter logic [BlockAw-1:0] SPI_HOST_ERROR_STATUS_OFFSET = 6'h 28; + parameter logic [BlockAw-1:0] SPI_HOST_EVENT_ENABLE_OFFSET = 6'h 2c; + + // Reset values for hwext registers and their fields + parameter logic [1:0] SPI_HOST_INTR_TEST_RESVAL = 2'h 0; + parameter logic [0:0] SPI_HOST_INTR_TEST_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] SPI_HOST_INTR_TEST_SPI_EVENT_RESVAL = 1'h 0; + parameter logic [31:0] SPI_HOST_RXDATA_RESVAL = 32'h 0; + parameter logic [31:0] SPI_HOST_RXDATA_DATA_RESVAL = 32'h 0; + + // Window parameter + parameter logic [BlockAw-1:0] SPI_HOST_TXDATA_OFFSET = 6'h 1c; + parameter logic [BlockAw-1:0] SPI_HOST_TXDATA_SIZE = 6'h 4; // Register Index typedef enum int { - SPI_HOST_CONTROL + SPI_HOST_INTR_STATE, + SPI_HOST_INTR_ENABLE, + SPI_HOST_INTR_TEST, + SPI_HOST_CONTROL, + SPI_HOST_STATUS, + SPI_HOST_CONFIGOPTS, + SPI_HOST_COMMAND, + SPI_HOST_RXDATA, + SPI_HOST_ERROR_ENABLE, + SPI_HOST_ERROR_STATUS, + SPI_HOST_EVENT_ENABLE } spi_host_id_e; // Register width information to check illegal writes - parameter logic [3:0] SPI_HOST_PERMIT [1] = '{ - 4'b 0001 // index[0] SPI_HOST_CONTROL + parameter logic [3:0] SPI_HOST_PERMIT [11] = '{ + 4'b 0001, // index[ 0] SPI_HOST_INTR_STATE + 4'b 0001, // index[ 1] SPI_HOST_INTR_ENABLE + 4'b 0001, // index[ 2] SPI_HOST_INTR_TEST + 4'b 1111, // index[ 3] SPI_HOST_CONTROL + 4'b 1111, // index[ 4] SPI_HOST_STATUS + 4'b 1111, // index[ 5] SPI_HOST_CONFIGOPTS + 4'b 1111, // index[ 6] SPI_HOST_COMMAND + 4'b 1111, // index[ 7] SPI_HOST_RXDATA + 4'b 0001, // index[ 8] SPI_HOST_ERROR_ENABLE + 4'b 0001, // index[ 9] SPI_HOST_ERROR_STATUS + 4'b 0001 // index[10] SPI_HOST_EVENT_ENABLE }; endpackage
diff --git a/hw/ip/spi_host/rtl/spi_host_reg_top.sv b/hw/ip/spi_host/rtl/spi_host_reg_top.sv index ab6321b..f670df4 100644 --- a/hw/ip/spi_host/rtl/spi_host_reg_top.sv +++ b/hw/ip/spi_host/rtl/spi_host_reg_top.sv
@@ -13,6 +13,11 @@ // Below Regster interface can be changed input tlul_pkg::tl_h2d_t tl_i, output tlul_pkg::tl_d2h_t tl_o, + + // Output port for window + output tlul_pkg::tl_h2d_t tl_win_o [1], + input tlul_pkg::tl_d2h_t tl_win_i [1], + // To HW output spi_host_reg_pkg::spi_host_reg2hw_t reg2hw, // Write input spi_host_reg_pkg::spi_host_hw2reg_t hw2reg, // Read @@ -23,7 +28,7 @@ import spi_host_reg_pkg::* ; - localparam int AW = 2; + localparam int AW = 6; localparam int DW = 32; localparam int DBW = DW/8; // Byte Width @@ -57,8 +62,51 @@ .tl_o ); - assign tl_reg_h2d = tl_i; - assign tl_o_pre = tl_reg_d2h; + tlul_pkg::tl_h2d_t tl_socket_h2d [2]; + tlul_pkg::tl_d2h_t tl_socket_d2h [2]; + + logic [1:0] reg_steer; + + // socket_1n connection + assign tl_reg_h2d = tl_socket_h2d[1]; + assign tl_socket_d2h[1] = tl_reg_d2h; + + assign tl_win_o[0] = tl_socket_h2d[0]; + assign tl_socket_d2h[0] = tl_win_i[0]; + + // Create Socket_1n + tlul_socket_1n #( + .N (2), + .HReqPass (1'b1), + .HRspPass (1'b1), + .DReqPass ({2{1'b1}}), + .DRspPass ({2{1'b1}}), + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth ({2{4'h0}}), + .DRspDepth ({2{4'h0}}) + ) u_socket ( + .clk_i, + .rst_ni, + .tl_h_i (tl_i), + .tl_h_o (tl_o_pre), + .tl_d_o (tl_socket_h2d), + .tl_d_i (tl_socket_d2h), + .dev_select_i (reg_steer) + ); + + // Create steering logic + always_comb begin + reg_steer = 1; // Default set to register + + // TODO: Can below codes be unique case () inside ? + if (tl_i.a_address[AW-1:0] >= 28 && tl_i.a_address[AW-1:0] < 32) begin + reg_steer = 0; + end + if (chk_err) begin + reg_steer = 1; + end + end tlul_adapter_reg #( .RegAw(AW), @@ -85,132 +133,1629 @@ // Define SW related signals // Format: <reg>_<field>_{wd|we|qs} // or <reg>_{wd|we|qs} if field == 1 or 0 - logic [3:0] control_data_qs; - logic [3:0] control_data_wd; - logic control_data_we; - logic control_sck_qs; - logic control_sck_wd; - logic control_sck_we; - logic control_csb_qs; - logic control_csb_wd; - logic control_csb_we; - logic control_dir_qs; - logic control_dir_wd; - logic control_dir_we; + logic intr_state_error_qs; + logic intr_state_error_wd; + logic intr_state_error_we; + logic intr_state_spi_event_qs; + logic intr_state_spi_event_wd; + logic intr_state_spi_event_we; + logic intr_enable_error_qs; + logic intr_enable_error_wd; + logic intr_enable_error_we; + logic intr_enable_spi_event_qs; + logic intr_enable_spi_event_wd; + logic intr_enable_spi_event_we; + logic intr_test_error_wd; + logic intr_test_error_we; + logic intr_test_spi_event_wd; + logic intr_test_spi_event_we; + logic [7:0] control_manual_cs_qs; + logic [7:0] control_manual_cs_wd; + logic control_manual_cs_we; + logic control_mancs_en_qs; + logic control_mancs_en_wd; + logic control_mancs_en_we; + logic [6:0] control_rx_watermark_qs; + logic [6:0] control_rx_watermark_wd; + logic control_rx_watermark_we; + logic [8:0] control_tx_watermark_qs; + logic [8:0] control_tx_watermark_wd; + logic control_tx_watermark_we; + logic control_passthru_qs; + logic control_passthru_wd; + logic control_passthru_we; + logic control_rst_rxfifo_qs; + logic control_rst_rxfifo_wd; + logic control_rst_rxfifo_we; + logic control_rst_txfifo_qs; + logic control_rst_txfifo_wd; + logic control_rst_txfifo_we; + logic control_rst_fsm_qs; + logic control_rst_fsm_wd; + logic control_rst_fsm_we; + logic control_spien_qs; + logic control_spien_wd; + logic control_spien_we; + logic [8:0] status_txqd_qs; + logic [8:0] status_rxqd_qs; + logic status_rxwm_qs; + logic status_byteorder_qs; + logic status_rxstall_qs; + logic status_rxempty_qs; + logic status_rxfull_qs; + logic status_txwm_qs; + logic status_txstall_qs; + logic status_txempty_qs; + logic status_txfull_qs; + logic status_active_qs; + logic status_ready_qs; + logic [15:0] configopts_clkdiv_0_qs; + logic [15:0] configopts_clkdiv_0_wd; + logic configopts_clkdiv_0_we; + logic [3:0] configopts_csnidle_0_qs; + logic [3:0] configopts_csnidle_0_wd; + logic configopts_csnidle_0_we; + logic [3:0] configopts_csntrail_0_qs; + logic [3:0] configopts_csntrail_0_wd; + logic configopts_csntrail_0_we; + logic [3:0] configopts_csnlead_0_qs; + logic [3:0] configopts_csnlead_0_wd; + logic configopts_csnlead_0_we; + logic configopts_csaat_0_qs; + logic configopts_csaat_0_wd; + logic configopts_csaat_0_we; + logic configopts_fullcyc_0_qs; + logic configopts_fullcyc_0_wd; + logic configopts_fullcyc_0_we; + logic configopts_cpha_0_qs; + logic configopts_cpha_0_wd; + logic configopts_cpha_0_we; + logic configopts_cpol_0_qs; + logic configopts_cpol_0_wd; + logic configopts_cpol_0_we; + logic [3:0] command_tx1_cnt_0_qs; + logic [3:0] command_tx1_cnt_0_wd; + logic command_tx1_cnt_0_we; + logic [8:0] command_txn_cnt_0_qs; + logic [8:0] command_txn_cnt_0_wd; + logic command_txn_cnt_0_we; + logic [3:0] command_dummy_cycles_0_qs; + logic [3:0] command_dummy_cycles_0_wd; + logic command_dummy_cycles_0_we; + logic [8:0] command_rx_cnt_0_qs; + logic [8:0] command_rx_cnt_0_wd; + logic command_rx_cnt_0_we; + logic command_fulldplx_0_qs; + logic command_fulldplx_0_wd; + logic command_fulldplx_0_we; + logic command_highz_0_qs; + logic command_highz_0_wd; + logic command_highz_0_we; + logic [1:0] command_speed_0_qs; + logic [1:0] command_speed_0_wd; + logic command_speed_0_we; + logic command_go_0_qs; + logic command_go_0_wd; + logic command_go_0_we; + logic [31:0] rxdata_qs; + logic rxdata_re; + logic error_enable_cmderr_qs; + logic error_enable_cmderr_wd; + logic error_enable_cmderr_we; + logic error_enable_overflow_qs; + logic error_enable_overflow_wd; + logic error_enable_overflow_we; + logic error_enable_underflow_qs; + logic error_enable_underflow_wd; + logic error_enable_underflow_we; + logic error_status_cmderr_qs; + logic error_status_cmderr_wd; + logic error_status_cmderr_we; + logic error_status_overflow_qs; + logic error_status_overflow_wd; + logic error_status_overflow_we; + logic error_status_underflow_qs; + logic error_status_underflow_wd; + logic error_status_underflow_we; + logic event_enable_rxfull_qs; + logic event_enable_rxfull_wd; + logic event_enable_rxfull_we; + logic event_enable_txempty_qs; + logic event_enable_txempty_wd; + logic event_enable_txempty_we; + logic event_enable_rxwm_qs; + logic event_enable_rxwm_wd; + logic event_enable_rxwm_we; + logic event_enable_txwm_qs; + logic event_enable_txwm_wd; + logic event_enable_txwm_we; + logic event_enable_ready_qs; + logic event_enable_ready_wd; + logic event_enable_ready_we; + logic event_enable_idle_qs; + logic event_enable_idle_wd; + logic event_enable_idle_we; // Register instances + // R[intr_state]: V(False) + + // F[error]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intr_state_error ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intr_state_error_we), + .wd (intr_state_error_wd), + + // from internal hardware + .de (hw2reg.intr_state.error.de), + .d (hw2reg.intr_state.error.d ), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.error.q ), + + // to register interface (read) + .qs (intr_state_error_qs) + ); + + + // F[spi_event]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intr_state_spi_event ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intr_state_spi_event_we), + .wd (intr_state_spi_event_wd), + + // from internal hardware + .de (hw2reg.intr_state.spi_event.de), + .d (hw2reg.intr_state.spi_event.d ), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.spi_event.q ), + + // to register interface (read) + .qs (intr_state_spi_event_qs) + ); + + + // R[intr_enable]: V(False) + + // F[error]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intr_enable_error ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intr_enable_error_we), + .wd (intr_enable_error_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.error.q ), + + // to register interface (read) + .qs (intr_enable_error_qs) + ); + + + // F[spi_event]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intr_enable_spi_event ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intr_enable_spi_event_we), + .wd (intr_enable_spi_event_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.spi_event.q ), + + // to register interface (read) + .qs (intr_enable_spi_event_qs) + ); + + + // R[intr_test]: V(True) + + // F[error]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_error ( + .re (1'b0), + .we (intr_test_error_we), + .wd (intr_test_error_wd), + .d ('0), + .qre (), + .qe (reg2hw.intr_test.error.qe), + .q (reg2hw.intr_test.error.q ), + .qs () + ); + + + // F[spi_event]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_spi_event ( + .re (1'b0), + .we (intr_test_spi_event_we), + .wd (intr_test_spi_event_wd), + .d ('0), + .qre (), + .qe (reg2hw.intr_test.spi_event.qe), + .q (reg2hw.intr_test.spi_event.q ), + .qs () + ); + + // R[control]: V(False) - // F[data]: 3:0 + // F[manual_cs]: 7:0 + prim_subreg #( + .DW (8), + .SWACCESS("RW"), + .RESVAL (8'h0) + ) u_control_manual_cs ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (control_manual_cs_we), + .wd (control_manual_cs_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.manual_cs.q ), + + // to register interface (read) + .qs (control_manual_cs_qs) + ); + + + // F[mancs_en]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_control_mancs_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (control_mancs_en_we), + .wd (control_mancs_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.mancs_en.q ), + + // to register interface (read) + .qs (control_mancs_en_qs) + ); + + + // F[rx_watermark]: 15:9 + prim_subreg #( + .DW (7), + .SWACCESS("RW"), + .RESVAL (7'h7f) + ) u_control_rx_watermark ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (control_rx_watermark_we), + .wd (control_rx_watermark_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.rx_watermark.q ), + + // to register interface (read) + .qs (control_rx_watermark_qs) + ); + + + // F[tx_watermark]: 24:16 + prim_subreg #( + .DW (9), + .SWACCESS("RW"), + .RESVAL (9'h0) + ) u_control_tx_watermark ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (control_tx_watermark_we), + .wd (control_tx_watermark_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.tx_watermark.q ), + + // to register interface (read) + .qs (control_tx_watermark_qs) + ); + + + // F[passthru]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_control_passthru ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (control_passthru_we), + .wd (control_passthru_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.passthru.q ), + + // to register interface (read) + .qs (control_passthru_qs) + ); + + + // F[rst_rxfifo]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_control_rst_rxfifo ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (control_rst_rxfifo_we), + .wd (control_rst_rxfifo_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.rst_rxfifo.q ), + + // to register interface (read) + .qs (control_rst_rxfifo_qs) + ); + + + // F[rst_txfifo]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_control_rst_txfifo ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (control_rst_txfifo_we), + .wd (control_rst_txfifo_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.rst_txfifo.q ), + + // to register interface (read) + .qs (control_rst_txfifo_qs) + ); + + + // F[rst_fsm]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_control_rst_fsm ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (control_rst_fsm_we), + .wd (control_rst_fsm_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.rst_fsm.q ), + + // to register interface (read) + .qs (control_rst_fsm_qs) + ); + + + // F[spien]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_control_spien ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (control_spien_we), + .wd (control_spien_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.spien.q ), + + // to register interface (read) + .qs (control_spien_qs) + ); + + + // R[status]: V(False) + + // F[txqd]: 8:0 + prim_subreg #( + .DW (9), + .SWACCESS("RO"), + .RESVAL (9'h0) + ) u_status_txqd ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.txqd.de), + .d (hw2reg.status.txqd.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_txqd_qs) + ); + + + // F[rxqd]: 17:9 + prim_subreg #( + .DW (9), + .SWACCESS("RO"), + .RESVAL (9'h0) + ) u_status_rxqd ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.rxqd.de), + .d (hw2reg.status.rxqd.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_rxqd_qs) + ); + + + // F[rxwm]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_status_rxwm ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.rxwm.de), + .d (hw2reg.status.rxwm.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_rxwm_qs) + ); + + + // F[byteorder]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_status_byteorder ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.byteorder.de), + .d (hw2reg.status.byteorder.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_byteorder_qs) + ); + + + // F[rxstall]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_status_rxstall ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.rxstall.de), + .d (hw2reg.status.rxstall.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_rxstall_qs) + ); + + + // F[rxempty]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_status_rxempty ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.rxempty.de), + .d (hw2reg.status.rxempty.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_rxempty_qs) + ); + + + // F[rxfull]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_status_rxfull ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.rxfull.de), + .d (hw2reg.status.rxfull.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_rxfull_qs) + ); + + + // F[txwm]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_status_txwm ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.txwm.de), + .d (hw2reg.status.txwm.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_txwm_qs) + ); + + + // F[txstall]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_status_txstall ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.txstall.de), + .d (hw2reg.status.txstall.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_txstall_qs) + ); + + + // F[txempty]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_status_txempty ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.txempty.de), + .d (hw2reg.status.txempty.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_txempty_qs) + ); + + + // F[txfull]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_status_txfull ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.txfull.de), + .d (hw2reg.status.txfull.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_txfull_qs) + ); + + + // F[active]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_status_active ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.active.de), + .d (hw2reg.status.active.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_active_qs) + ); + + + // F[ready]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_status_ready ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.ready.de), + .d (hw2reg.status.ready.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_ready_qs) + ); + + + + // Subregister 0 of Multireg configopts + // R[configopts]: V(False) + + // F[clkdiv_0]: 15:0 + prim_subreg #( + .DW (16), + .SWACCESS("RW"), + .RESVAL (16'h0) + ) u_configopts_clkdiv_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (configopts_clkdiv_0_we), + .wd (configopts_clkdiv_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.configopts[0].clkdiv.q ), + + // to register interface (read) + .qs (configopts_clkdiv_0_qs) + ); + + + // F[csnidle_0]: 19:16 prim_subreg #( .DW (4), .SWACCESS("RW"), .RESVAL (4'h0) - ) u_control_data ( + ) u_configopts_csnidle_0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (control_data_we), - .wd (control_data_wd), + .we (configopts_csnidle_0_we), + .wd (configopts_csnidle_0_wd), // from internal hardware - .de (hw2reg.control.data.de), - .d (hw2reg.control.data.d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.control.data.q ), + .q (reg2hw.configopts[0].csnidle.q ), // to register interface (read) - .qs (control_data_qs) + .qs (configopts_csnidle_0_qs) ); - // F[sck]: 4:4 + // F[csntrail_0]: 23:20 + prim_subreg #( + .DW (4), + .SWACCESS("RW"), + .RESVAL (4'h0) + ) u_configopts_csntrail_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (configopts_csntrail_0_we), + .wd (configopts_csntrail_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.configopts[0].csntrail.q ), + + // to register interface (read) + .qs (configopts_csntrail_0_qs) + ); + + + // F[csnlead_0]: 27:24 + prim_subreg #( + .DW (4), + .SWACCESS("RW"), + .RESVAL (4'h0) + ) u_configopts_csnlead_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (configopts_csnlead_0_we), + .wd (configopts_csnlead_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.configopts[0].csnlead.q ), + + // to register interface (read) + .qs (configopts_csnlead_0_qs) + ); + + + // F[csaat_0]: 28:28 prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_control_sck ( + ) u_configopts_csaat_0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (control_sck_we), - .wd (control_sck_wd), + .we (configopts_csaat_0_we), + .wd (configopts_csaat_0_wd), // from internal hardware - .de (hw2reg.control.sck.de), - .d (hw2reg.control.sck.d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.control.sck.q ), + .q (reg2hw.configopts[0].csaat.q ), // to register interface (read) - .qs (control_sck_qs) + .qs (configopts_csaat_0_qs) ); - // F[csb]: 5:5 + // F[fullcyc_0]: 29:29 prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_control_csb ( + ) u_configopts_fullcyc_0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (control_csb_we), - .wd (control_csb_wd), + .we (configopts_fullcyc_0_we), + .wd (configopts_fullcyc_0_wd), // from internal hardware - .de (hw2reg.control.csb.de), - .d (hw2reg.control.csb.d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.control.csb.q ), + .q (reg2hw.configopts[0].fullcyc.q ), // to register interface (read) - .qs (control_csb_qs) + .qs (configopts_fullcyc_0_qs) ); - // F[dir]: 6:6 + // F[cpha_0]: 30:30 prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_control_dir ( + ) u_configopts_cpha_0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (control_dir_we), - .wd (control_dir_wd), + .we (configopts_cpha_0_we), + .wd (configopts_cpha_0_wd), // from internal hardware - .de (hw2reg.control.dir.de), - .d (hw2reg.control.dir.d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.control.dir.q ), + .q (reg2hw.configopts[0].cpha.q ), // to register interface (read) - .qs (control_dir_qs) + .qs (configopts_cpha_0_qs) + ); + + + // F[cpol_0]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_configopts_cpol_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (configopts_cpol_0_we), + .wd (configopts_cpol_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.configopts[0].cpol.q ), + + // to register interface (read) + .qs (configopts_cpol_0_qs) ); - logic [0:0] addr_hit; + // Subregister 0 of Multireg command + // R[command]: V(False) + + // F[tx1_cnt_0]: 3:0 + prim_subreg #( + .DW (4), + .SWACCESS("RW"), + .RESVAL (4'h0) + ) u_command_tx1_cnt_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (command_tx1_cnt_0_we), + .wd (command_tx1_cnt_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.command[0].tx1_cnt.qe), + .q (reg2hw.command[0].tx1_cnt.q ), + + // to register interface (read) + .qs (command_tx1_cnt_0_qs) + ); + + + // F[txn_cnt_0]: 12:4 + prim_subreg #( + .DW (9), + .SWACCESS("RW"), + .RESVAL (9'h0) + ) u_command_txn_cnt_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (command_txn_cnt_0_we), + .wd (command_txn_cnt_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.command[0].txn_cnt.qe), + .q (reg2hw.command[0].txn_cnt.q ), + + // to register interface (read) + .qs (command_txn_cnt_0_qs) + ); + + + // F[dummy_cycles_0]: 16:13 + prim_subreg #( + .DW (4), + .SWACCESS("RW"), + .RESVAL (4'h0) + ) u_command_dummy_cycles_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (command_dummy_cycles_0_we), + .wd (command_dummy_cycles_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.command[0].dummy_cycles.qe), + .q (reg2hw.command[0].dummy_cycles.q ), + + // to register interface (read) + .qs (command_dummy_cycles_0_qs) + ); + + + // F[rx_cnt_0]: 25:17 + prim_subreg #( + .DW (9), + .SWACCESS("RW"), + .RESVAL (9'h0) + ) u_command_rx_cnt_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (command_rx_cnt_0_we), + .wd (command_rx_cnt_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.command[0].rx_cnt.qe), + .q (reg2hw.command[0].rx_cnt.q ), + + // to register interface (read) + .qs (command_rx_cnt_0_qs) + ); + + + // F[fulldplx_0]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_command_fulldplx_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (command_fulldplx_0_we), + .wd (command_fulldplx_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.command[0].fulldplx.qe), + .q (reg2hw.command[0].fulldplx.q ), + + // to register interface (read) + .qs (command_fulldplx_0_qs) + ); + + + // F[highz_0]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_command_highz_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (command_highz_0_we), + .wd (command_highz_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.command[0].highz.qe), + .q (reg2hw.command[0].highz.q ), + + // to register interface (read) + .qs (command_highz_0_qs) + ); + + + // F[speed_0]: 30:29 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_command_speed_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (command_speed_0_we), + .wd (command_speed_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.command[0].speed.qe), + .q (reg2hw.command[0].speed.q ), + + // to register interface (read) + .qs (command_speed_0_qs) + ); + + + // F[go_0]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_command_go_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (command_go_0_we), + .wd (command_go_0_wd), + + // from internal hardware + .de (hw2reg.command[0].go.de), + .d (hw2reg.command[0].go.d ), + + // to internal hardware + .qe (reg2hw.command[0].go.qe), + .q (reg2hw.command[0].go.q ), + + // to register interface (read) + .qs (command_go_0_qs) + ); + + + + // R[rxdata]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_rxdata ( + .re (rxdata_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rxdata.d), + .qre (), + .qe (), + .q (), + .qs (rxdata_qs) + ); + + + // R[error_enable]: V(False) + + // F[cmderr]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_error_enable_cmderr ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (error_enable_cmderr_we), + .wd (error_enable_cmderr_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.error_enable.cmderr.q ), + + // to register interface (read) + .qs (error_enable_cmderr_qs) + ); + + + // F[overflow]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_error_enable_overflow ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (error_enable_overflow_we), + .wd (error_enable_overflow_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.error_enable.overflow.q ), + + // to register interface (read) + .qs (error_enable_overflow_qs) + ); + + + // F[underflow]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_error_enable_underflow ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (error_enable_underflow_we), + .wd (error_enable_underflow_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.error_enable.underflow.q ), + + // to register interface (read) + .qs (error_enable_underflow_qs) + ); + + + // R[error_status]: V(False) + + // F[cmderr]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_error_status_cmderr ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (error_status_cmderr_we), + .wd (error_status_cmderr_wd), + + // from internal hardware + .de (hw2reg.error_status.cmderr.de), + .d (hw2reg.error_status.cmderr.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (error_status_cmderr_qs) + ); + + + // F[overflow]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_error_status_overflow ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (error_status_overflow_we), + .wd (error_status_overflow_wd), + + // from internal hardware + .de (hw2reg.error_status.overflow.de), + .d (hw2reg.error_status.overflow.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (error_status_overflow_qs) + ); + + + // F[underflow]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_error_status_underflow ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (error_status_underflow_we), + .wd (error_status_underflow_wd), + + // from internal hardware + .de (hw2reg.error_status.underflow.de), + .d (hw2reg.error_status.underflow.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (error_status_underflow_qs) + ); + + + // R[event_enable]: V(False) + + // F[rxfull]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_event_enable_rxfull ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (event_enable_rxfull_we), + .wd (event_enable_rxfull_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.event_enable.rxfull.q ), + + // to register interface (read) + .qs (event_enable_rxfull_qs) + ); + + + // F[txempty]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_event_enable_txempty ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (event_enable_txempty_we), + .wd (event_enable_txempty_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.event_enable.txempty.q ), + + // to register interface (read) + .qs (event_enable_txempty_qs) + ); + + + // F[rxwm]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_event_enable_rxwm ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (event_enable_rxwm_we), + .wd (event_enable_rxwm_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.event_enable.rxwm.q ), + + // to register interface (read) + .qs (event_enable_rxwm_qs) + ); + + + // F[txwm]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_event_enable_txwm ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (event_enable_txwm_we), + .wd (event_enable_txwm_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.event_enable.txwm.q ), + + // to register interface (read) + .qs (event_enable_txwm_qs) + ); + + + // F[ready]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_event_enable_ready ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (event_enable_ready_we), + .wd (event_enable_ready_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.event_enable.ready.q ), + + // to register interface (read) + .qs (event_enable_ready_qs) + ); + + + // F[idle]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_event_enable_idle ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (event_enable_idle_we), + .wd (event_enable_idle_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.event_enable.idle.q ), + + // to register interface (read) + .qs (event_enable_idle_qs) + ); + + + + + logic [10:0] addr_hit; always_comb begin addr_hit = '0; - addr_hit[0] = (reg_addr == SPI_HOST_CONTROL_OFFSET); + addr_hit[ 0] = (reg_addr == SPI_HOST_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == SPI_HOST_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == SPI_HOST_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == SPI_HOST_CONTROL_OFFSET); + addr_hit[ 4] = (reg_addr == SPI_HOST_STATUS_OFFSET); + addr_hit[ 5] = (reg_addr == SPI_HOST_CONFIGOPTS_OFFSET); + addr_hit[ 6] = (reg_addr == SPI_HOST_COMMAND_OFFSET); + addr_hit[ 7] = (reg_addr == SPI_HOST_RXDATA_OFFSET); + addr_hit[ 8] = (reg_addr == SPI_HOST_ERROR_ENABLE_OFFSET); + addr_hit[ 9] = (reg_addr == SPI_HOST_ERROR_STATUS_OFFSET); + addr_hit[10] = (reg_addr == SPI_HOST_EVENT_ENABLE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -218,30 +1763,255 @@ // Check sub-word write is permitted always_comb begin wr_err = 1'b0; - if (addr_hit[0] && reg_we && (SPI_HOST_PERMIT[0] != (SPI_HOST_PERMIT[0] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 0] && reg_we && (SPI_HOST_PERMIT[ 0] != (SPI_HOST_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 1] && reg_we && (SPI_HOST_PERMIT[ 1] != (SPI_HOST_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 2] && reg_we && (SPI_HOST_PERMIT[ 2] != (SPI_HOST_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 3] && reg_we && (SPI_HOST_PERMIT[ 3] != (SPI_HOST_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 4] && reg_we && (SPI_HOST_PERMIT[ 4] != (SPI_HOST_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 5] && reg_we && (SPI_HOST_PERMIT[ 5] != (SPI_HOST_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 6] && reg_we && (SPI_HOST_PERMIT[ 6] != (SPI_HOST_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 7] && reg_we && (SPI_HOST_PERMIT[ 7] != (SPI_HOST_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 8] && reg_we && (SPI_HOST_PERMIT[ 8] != (SPI_HOST_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 9] && reg_we && (SPI_HOST_PERMIT[ 9] != (SPI_HOST_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[10] && reg_we && (SPI_HOST_PERMIT[10] != (SPI_HOST_PERMIT[10] & reg_be))) wr_err = 1'b1 ; end - assign control_data_we = addr_hit[0] & reg_we & ~wr_err; - assign control_data_wd = reg_wdata[3:0]; + assign intr_state_error_we = addr_hit[0] & reg_we & ~wr_err; + assign intr_state_error_wd = reg_wdata[0]; - assign control_sck_we = addr_hit[0] & reg_we & ~wr_err; - assign control_sck_wd = reg_wdata[4]; + assign intr_state_spi_event_we = addr_hit[0] & reg_we & ~wr_err; + assign intr_state_spi_event_wd = reg_wdata[1]; - assign control_csb_we = addr_hit[0] & reg_we & ~wr_err; - assign control_csb_wd = reg_wdata[5]; + assign intr_enable_error_we = addr_hit[1] & reg_we & ~wr_err; + assign intr_enable_error_wd = reg_wdata[0]; - assign control_dir_we = addr_hit[0] & reg_we & ~wr_err; - assign control_dir_wd = reg_wdata[6]; + assign intr_enable_spi_event_we = addr_hit[1] & reg_we & ~wr_err; + assign intr_enable_spi_event_wd = reg_wdata[1]; + + assign intr_test_error_we = addr_hit[2] & reg_we & ~wr_err; + assign intr_test_error_wd = reg_wdata[0]; + + assign intr_test_spi_event_we = addr_hit[2] & reg_we & ~wr_err; + assign intr_test_spi_event_wd = reg_wdata[1]; + + assign control_manual_cs_we = addr_hit[3] & reg_we & ~wr_err; + assign control_manual_cs_wd = reg_wdata[7:0]; + + assign control_mancs_en_we = addr_hit[3] & reg_we & ~wr_err; + assign control_mancs_en_wd = reg_wdata[8]; + + assign control_rx_watermark_we = addr_hit[3] & reg_we & ~wr_err; + assign control_rx_watermark_wd = reg_wdata[15:9]; + + assign control_tx_watermark_we = addr_hit[3] & reg_we & ~wr_err; + assign control_tx_watermark_wd = reg_wdata[24:16]; + + assign control_passthru_we = addr_hit[3] & reg_we & ~wr_err; + assign control_passthru_wd = reg_wdata[27]; + + assign control_rst_rxfifo_we = addr_hit[3] & reg_we & ~wr_err; + assign control_rst_rxfifo_wd = reg_wdata[28]; + + assign control_rst_txfifo_we = addr_hit[3] & reg_we & ~wr_err; + assign control_rst_txfifo_wd = reg_wdata[29]; + + assign control_rst_fsm_we = addr_hit[3] & reg_we & ~wr_err; + assign control_rst_fsm_wd = reg_wdata[30]; + + assign control_spien_we = addr_hit[3] & reg_we & ~wr_err; + assign control_spien_wd = reg_wdata[31]; + + + + + + + + + + + + + + + assign configopts_clkdiv_0_we = addr_hit[5] & reg_we & ~wr_err; + assign configopts_clkdiv_0_wd = reg_wdata[15:0]; + + assign configopts_csnidle_0_we = addr_hit[5] & reg_we & ~wr_err; + assign configopts_csnidle_0_wd = reg_wdata[19:16]; + + assign configopts_csntrail_0_we = addr_hit[5] & reg_we & ~wr_err; + assign configopts_csntrail_0_wd = reg_wdata[23:20]; + + assign configopts_csnlead_0_we = addr_hit[5] & reg_we & ~wr_err; + assign configopts_csnlead_0_wd = reg_wdata[27:24]; + + assign configopts_csaat_0_we = addr_hit[5] & reg_we & ~wr_err; + assign configopts_csaat_0_wd = reg_wdata[28]; + + assign configopts_fullcyc_0_we = addr_hit[5] & reg_we & ~wr_err; + assign configopts_fullcyc_0_wd = reg_wdata[29]; + + assign configopts_cpha_0_we = addr_hit[5] & reg_we & ~wr_err; + assign configopts_cpha_0_wd = reg_wdata[30]; + + assign configopts_cpol_0_we = addr_hit[5] & reg_we & ~wr_err; + assign configopts_cpol_0_wd = reg_wdata[31]; + + assign command_tx1_cnt_0_we = addr_hit[6] & reg_we & ~wr_err; + assign command_tx1_cnt_0_wd = reg_wdata[3:0]; + + assign command_txn_cnt_0_we = addr_hit[6] & reg_we & ~wr_err; + assign command_txn_cnt_0_wd = reg_wdata[12:4]; + + assign command_dummy_cycles_0_we = addr_hit[6] & reg_we & ~wr_err; + assign command_dummy_cycles_0_wd = reg_wdata[16:13]; + + assign command_rx_cnt_0_we = addr_hit[6] & reg_we & ~wr_err; + assign command_rx_cnt_0_wd = reg_wdata[25:17]; + + assign command_fulldplx_0_we = addr_hit[6] & reg_we & ~wr_err; + assign command_fulldplx_0_wd = reg_wdata[26]; + + assign command_highz_0_we = addr_hit[6] & reg_we & ~wr_err; + assign command_highz_0_wd = reg_wdata[27]; + + assign command_speed_0_we = addr_hit[6] & reg_we & ~wr_err; + assign command_speed_0_wd = reg_wdata[30:29]; + + assign command_go_0_we = addr_hit[6] & reg_we & ~wr_err; + assign command_go_0_wd = reg_wdata[31]; + + assign rxdata_re = addr_hit[7] && reg_re; + + assign error_enable_cmderr_we = addr_hit[8] & reg_we & ~wr_err; + assign error_enable_cmderr_wd = reg_wdata[0]; + + assign error_enable_overflow_we = addr_hit[8] & reg_we & ~wr_err; + assign error_enable_overflow_wd = reg_wdata[1]; + + assign error_enable_underflow_we = addr_hit[8] & reg_we & ~wr_err; + assign error_enable_underflow_wd = reg_wdata[2]; + + assign error_status_cmderr_we = addr_hit[9] & reg_we & ~wr_err; + assign error_status_cmderr_wd = reg_wdata[0]; + + assign error_status_overflow_we = addr_hit[9] & reg_we & ~wr_err; + assign error_status_overflow_wd = reg_wdata[1]; + + assign error_status_underflow_we = addr_hit[9] & reg_we & ~wr_err; + assign error_status_underflow_wd = reg_wdata[2]; + + assign event_enable_rxfull_we = addr_hit[10] & reg_we & ~wr_err; + assign event_enable_rxfull_wd = reg_wdata[2]; + + assign event_enable_txempty_we = addr_hit[10] & reg_we & ~wr_err; + assign event_enable_txempty_wd = reg_wdata[3]; + + assign event_enable_rxwm_we = addr_hit[10] & reg_we & ~wr_err; + assign event_enable_rxwm_wd = reg_wdata[4]; + + assign event_enable_txwm_we = addr_hit[10] & reg_we & ~wr_err; + assign event_enable_txwm_wd = reg_wdata[5]; + + assign event_enable_ready_we = addr_hit[10] & reg_we & ~wr_err; + assign event_enable_ready_wd = reg_wdata[6]; + + assign event_enable_idle_we = addr_hit[10] & reg_we & ~wr_err; + assign event_enable_idle_wd = reg_wdata[7]; // Read data return always_comb begin reg_rdata_next = '0; unique case (1'b1) addr_hit[0]: begin - reg_rdata_next[3:0] = control_data_qs; - reg_rdata_next[4] = control_sck_qs; - reg_rdata_next[5] = control_csb_qs; - reg_rdata_next[6] = control_dir_qs; + reg_rdata_next[0] = intr_state_error_qs; + reg_rdata_next[1] = intr_state_spi_event_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = intr_enable_error_qs; + reg_rdata_next[1] = intr_enable_spi_event_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[7:0] = control_manual_cs_qs; + reg_rdata_next[8] = control_mancs_en_qs; + reg_rdata_next[15:9] = control_rx_watermark_qs; + reg_rdata_next[24:16] = control_tx_watermark_qs; + reg_rdata_next[27] = control_passthru_qs; + reg_rdata_next[28] = control_rst_rxfifo_qs; + reg_rdata_next[29] = control_rst_txfifo_qs; + reg_rdata_next[30] = control_rst_fsm_qs; + reg_rdata_next[31] = control_spien_qs; + end + + addr_hit[4]: begin + reg_rdata_next[8:0] = status_txqd_qs; + reg_rdata_next[17:9] = status_rxqd_qs; + reg_rdata_next[20] = status_rxwm_qs; + reg_rdata_next[22] = status_byteorder_qs; + reg_rdata_next[23] = status_rxstall_qs; + reg_rdata_next[24] = status_rxempty_qs; + reg_rdata_next[25] = status_rxfull_qs; + reg_rdata_next[26] = status_txwm_qs; + reg_rdata_next[27] = status_txstall_qs; + reg_rdata_next[28] = status_txempty_qs; + reg_rdata_next[29] = status_txfull_qs; + reg_rdata_next[30] = status_active_qs; + reg_rdata_next[31] = status_ready_qs; + end + + addr_hit[5]: begin + reg_rdata_next[15:0] = configopts_clkdiv_0_qs; + reg_rdata_next[19:16] = configopts_csnidle_0_qs; + reg_rdata_next[23:20] = configopts_csntrail_0_qs; + reg_rdata_next[27:24] = configopts_csnlead_0_qs; + reg_rdata_next[28] = configopts_csaat_0_qs; + reg_rdata_next[29] = configopts_fullcyc_0_qs; + reg_rdata_next[30] = configopts_cpha_0_qs; + reg_rdata_next[31] = configopts_cpol_0_qs; + end + + addr_hit[6]: begin + reg_rdata_next[3:0] = command_tx1_cnt_0_qs; + reg_rdata_next[12:4] = command_txn_cnt_0_qs; + reg_rdata_next[16:13] = command_dummy_cycles_0_qs; + reg_rdata_next[25:17] = command_rx_cnt_0_qs; + reg_rdata_next[26] = command_fulldplx_0_qs; + reg_rdata_next[27] = command_highz_0_qs; + reg_rdata_next[30:29] = command_speed_0_qs; + reg_rdata_next[31] = command_go_0_qs; + end + + addr_hit[7]: begin + reg_rdata_next[31:0] = rxdata_qs; + end + + addr_hit[8]: begin + reg_rdata_next[0] = error_enable_cmderr_qs; + reg_rdata_next[1] = error_enable_overflow_qs; + reg_rdata_next[2] = error_enable_underflow_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = error_status_cmderr_qs; + reg_rdata_next[1] = error_status_overflow_qs; + reg_rdata_next[2] = error_status_underflow_qs; + end + + addr_hit[10]: begin + reg_rdata_next[2] = event_enable_rxfull_qs; + reg_rdata_next[3] = event_enable_txempty_qs; + reg_rdata_next[4] = event_enable_rxwm_qs; + reg_rdata_next[5] = event_enable_txwm_qs; + reg_rdata_next[6] = event_enable_ready_qs; + reg_rdata_next[7] = event_enable_idle_qs; end default: begin
diff --git a/hw/ip/spi_host/spi_host.core b/hw/ip/spi_host/spi_host.core index ad3a539..6432e99 100644 --- a/hw/ip/spi_host/spi_host.core +++ b/hw/ip/spi_host/spi_host.core
@@ -8,6 +8,7 @@ filesets: files_rtl: depend: + - lowrisc:constants:top_pkg - lowrisc:ip:tlul - lowrisc:prim:all - lowrisc:ip:lc_ctrl_pkg
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 6fa4475..4a2af0e 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -1321,16 +1321,19 @@ clock_srcs: { clk_i: io_div4 + clk_core_i: io_div2 } clock_group: peri reset_connections: { rst_ni: rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel] + rst_core_ni: rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel] } base_addr: 0x40060000 clock_connections: { clk_i: clkmgr_aon_clocks.clk_io_div4_peri + clk_core_i: clkmgr_aon_clocks.clk_io_div2_peri } domain: "0" size: 0x1000 @@ -1359,11 +1362,37 @@ } ] param_list: [] - interrupt_list: [] + interrupt_list: + [ + { + name: error + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: interrupt + } + { + name: spi_event + width: 1 + bits: "1" + bitinfo: + [ + 2 + 1 + 1 + ] + type: interrupt + } + ] alert_list: [] wakeup_list: [] reset_request_list: [] - scan: "true" + scan: "false" scan_reset: "false" inter_signal_list: [ @@ -1388,16 +1417,19 @@ clock_srcs: { clk_i: io_div4 + clk_core_i: io_div2 } clock_group: peri reset_connections: { rst_ni: rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel] + rst_core_ni: rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel] } base_addr: 0x40070000 clock_connections: { clk_i: clkmgr_aon_clocks.clk_io_div4_peri + clk_core_i: clkmgr_aon_clocks.clk_io_div2_peri } domain: "0" size: 0x1000 @@ -1426,11 +1458,37 @@ } ] param_list: [] - interrupt_list: [] + interrupt_list: + [ + { + name: error + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: interrupt + } + { + name: spi_event + width: 1 + bits: "1" + bitinfo: + [ + 2 + 1 + 1 + ] + type: interrupt + } + ] alert_list: [] wakeup_list: [] reset_request_list: [] - scan: "true" + scan: "false" scan_reset: "false" inter_signal_list: [
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 3ea04d6..afe84cf 100755 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -282,16 +282,16 @@ }, { name: "spi_host0", type: "spi_host", - clock_srcs: {clk_i: "io_div4"}, + clock_srcs: {clk_i: "io_div4", clk_core_i: "io_div2"}, clock_group: "peri", - reset_connections: {rst_ni: "spi_host0"}, + reset_connections: {rst_ni: "spi_host0", rst_core_ni: "spi_host0"}, base_addr: "0x40060000", }, { name: "spi_host1", type: "spi_host", - clock_srcs: {clk_i: "io_div4"}, + clock_srcs: {clk_i: "io_div4", clk_core_i: "io_div2"}, clock_group: "peri", - reset_connections: {rst_ni: "spi_host1"}, + reset_connections: {rst_ni: "spi_host1", rst_core_ni: "spi_host1"}, base_addr: "0x40070000", }, { name: "i2c0",
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 9dc7607..c0893a8 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -279,6 +279,10 @@ logic intr_spi_device_rxerr; logic intr_spi_device_rxoverflow; logic intr_spi_device_txunderflow; + logic intr_spi_host0_error; + logic intr_spi_host0_spi_event; + logic intr_spi_host1_error; + logic intr_spi_host1_spi_event; logic intr_i2c0_fmt_watermark; logic intr_i2c0_rx_watermark; logic intr_i2c0_fmt_overflow; @@ -1115,14 +1119,19 @@ .cio_sd_o (cio_spi_host0_sd_d2p), .cio_sd_en_o (cio_spi_host0_sd_en_d2p), + // Interrupt + .intr_error_o (intr_spi_host0_error), + .intr_spi_event_o (intr_spi_host0_spi_event), + // Inter-module signals .tl_i(spi_host0_tl_req), .tl_o(spi_host0_tl_rsp), - .scanmode_i, // Clock and reset connections .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), - .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]) + .clk_core_i (clkmgr_aon_clocks.clk_io_div2_peri), + .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]), + .rst_core_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]) ); spi_host u_spi_host1 ( @@ -1138,14 +1147,19 @@ .cio_sd_o (cio_spi_host1_sd_d2p), .cio_sd_en_o (cio_spi_host1_sd_en_d2p), + // Interrupt + .intr_error_o (intr_spi_host1_error), + .intr_spi_event_o (intr_spi_host1_spi_event), + // Inter-module signals .tl_i(spi_host1_tl_req), .tl_o(spi_host1_tl_rsp), - .scanmode_i, // Clock and reset connections .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), - .rst_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel]) + .clk_core_i (clkmgr_aon_clocks.clk_io_div2_peri), + .rst_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel]), + .rst_core_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel]) ); i2c u_i2c0 (
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson index 23d4760..76676ff 100644 --- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson +++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -233,9 +233,9 @@ }, { name: "spi_host0", type: "spi_host", - clock_srcs: {clk_i: "io_div4"}, + clock_srcs: {clk_i: "io_div4", clk_core_i: "io_div2"}, clock_group: "peri", - reset_connections: {rst_ni: "spi_host0"}, + reset_connections: {rst_ni: "spi_host0", rst_core_ni: "spi_host0"}, base_addr: "0x40060000", }, { name: "rv_timer",
