[top] Integrate usbdev using topgen
This commit integrates the USB device (usbdev) into the Earlgrey top
using topgen. The previous, manually maintained, top_earlgrey_usb
versions of the top level are removed and the hello_usbdev example is
added to CI as a first sanity check.
This commit also contains work from Srikrishna Iyer <sriyer@google.com>.
This resolves lowRISC/OpenTitan#52 and lowRISC/OpenTitan#1007.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
diff --git a/ci/run_verilator_pytest.sh b/ci/run_verilator_pytest.sh
index ad58b48..4ff4fa7 100755
--- a/ci/run_verilator_pytest.sh
+++ b/ci/run_verilator_pytest.sh
@@ -15,6 +15,7 @@
BOOT_ROM_TARGET="boot_rom/boot_rom.elf"
TEST_TARGETS=(
+ "examples/hello_usbdev/hello_usbdev.elf"
"tests/aes/aes_test.elf"
"tests/flash_ctrl/flash_test.elf"
"tests/hmac/sha256_test.elf"
@@ -24,6 +25,7 @@
if [[ ! -z ${MAKE_BUILD+x} ]]; then
BOOT_ROM_TARGET="sw/device/sim/boot_rom/rom.elf"
TEST_TARGETS=(
+ "sw/device/sim/examples/hello_usbdev.elf"
"sw/device/sim/tests/aes/sw.elf"
"sw/device/sim/tests/flash_ctrl/sw.elf"
"sw/device/sim/tests/hmac/sw.elf"
diff --git a/hw/dv/dpi/usbdpi/usbdpi.c b/hw/dv/dpi/usbdpi/usbdpi.c
index 491bea2..1ba3f07 100644
--- a/hw/dv/dpi/usbdpi/usbdpi.c
+++ b/hw/dv/dpi/usbdpi/usbdpi.c
@@ -21,10 +21,6 @@
#include <sys/types.h>
#include <unistd.h>
-#if TOOL_VERILATOR
-#include "verilator_sim_ctrl.h"
-#endif
-
static const char *st_states[] = {"ST_IDLE 0", "ST_SEND 1", "ST_GET 2",
"ST_SYNC 3", "ST_EOP 4", "ST_EOP0 5"};
@@ -626,19 +622,6 @@
}
switch (ctx->state) {
case ST_IDLE:
-#if TOOL_VERILATOR
- if (ctx->frame == 35) {
- printf("USB: usbdpi done, frame: %d, success: %d, state: %d\n",
- ctx->frame, ctx->baudrate_set_successfully, ctx->state);
-
- // If we were able to set the BAUD rate sucessfully, the DUT
- // provided reasonable responses to our requests. Ideally, we
- // would have a more advanced test here.
- VerilatorSimCtrl::GetInstance().RequestStop(
- ctx->baudrate_set_successfully);
- }
-#endif
-
switch (ctx->frame) {
case 1:
setDeviceAddress(ctx);
diff --git a/hw/ip/usbdev/data/usbdev.hjson b/hw/ip/usbdev/data/usbdev.hjson
index 19d575c..343e157 100644
--- a/hw/ip/usbdev/data/usbdev.hjson
+++ b/hw/ip/usbdev/data/usbdev.hjson
@@ -2,19 +2,22 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{ name: "usbdev",
- clock_primary: "clk_fixed",
- other_clock_list: [ "clk_48MHz" ]
+ clock_primary: "clk_i",
+ other_clock_list: [ "clk_usb_48mhz_i" ]
+ reset_primary: "rst_ni",
+ other_reset_list: [ "rst_usb_48mhz_ni" ]
bus_device: "tlul",
bus_host: "none",
available_inout_list: [
- { name: "usb_dp", desc: "USB data D+" }
- { name: "usb_dn", desc: "USB data D-" }
+ #{ name: "d", desc: "USB data differential" }
+ { name: "dp", desc: "USB data D+" }
+ { name: "dn", desc: "USB data D-" }
],
available_input_list: [
- { name: "usb_sense", desc: "USB host VBUS sense" }
+ { name: "sense", desc: "USB host VBUS sense" }
],
available_output_list: [
- { name: "usb_pullup", desc: "USB Full Speed pullup control" }
+ { name: "pullup", desc: "USB Full Speed pullup control" }
],
param_list: [
{ name: "NEndpoints",
diff --git a/hw/ip/usbdev/data/usbdev.prj.hjson b/hw/ip/usbdev/data/usbdev.prj.hjson
new file mode 100644
index 0000000..1c5a066
--- /dev/null
+++ b/hw/ip/usbdev/data/usbdev.prj.hjson
@@ -0,0 +1,11 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+{
+ name: "usbdev",
+ version: "0.5",
+ life_stage: "L1",
+ design_stage: "D0",
+ verification_stage: "V0",
+}
diff --git a/hw/ip/usbdev/doc/_index.md b/hw/ip/usbdev/doc/_index.md
index 0b8cc4c..1515350 100644
--- a/hw/ip/usbdev/doc/_index.md
+++ b/hw/ip/usbdev/doc/_index.md
@@ -73,7 +73,7 @@
|External Pin|Internal Signal|Notes|
|------------|---------------|-----|
-|USB D+, USB D-|usb_d_i, usb_dp_i, usb_dn_i, usb_d_o, usb_se0_o|Interface to a differential USB transceiver. This interface can be selected by writing 1 to {{< regref "phy_config.rx_differential_mode" >}} and {{< regref "phy_config.tx_differential_mode" >}}.|
+|USB D+, USB D-|usb_d_i, usb_dp_i, usb_dn_i, usb_d_o, usb_se0_o|Interface to a differential USB transceiver. This interface can be selected by writing 1 to {{< regref "phy_config.rx_differential_mode" >}} and {{< regref "phy_config.tx_differential_mode" >}}. In differential mode, the single-ended signals usb_dp_i and usb_dn_i are used to detect the SE0 state.|
|USB D+, USB D-|usb_dp_i, usb_dn_i, usb_dp_o, usb_dn_o|Single-ended interface to regular IO cells. This interface can be used for prototyping on an FPGA, but will probably not be USB compliant. This interface can be selected by writing 0 to {{< regref "phy_config.rx_differential_mode" >}} and {{< regref "phy_config.tx_differential_mode" >}}.|
||usb_oe_o|Enable driving the external pins.|
|[usb_pullup]|usb_pullup_o|When the usb_pullup_o asserts a 1.5k pullup resistor should be connected to D+. This can be done inside the chip or with an external pin. A permanently connected resistor can also be used.|
diff --git a/hw/ip/usbdev/dv/tb/tb.sv b/hw/ip/usbdev/dv/tb/tb.sv
index c649e28..194584c 100644
--- a/hw/ip/usbdev/dv/tb/tb.sv
+++ b/hw/ip/usbdev/dv/tb/tb.sv
@@ -49,7 +49,7 @@
.rst_ni (rst_n ),
.clk_usb_48mhz_i (usb_clk ),
- .rst_usb_ni (usb_rst_n ),
+ .rst_usb_48mhz_ni (usb_rst_n ),
.tl_i (tl_if.h2d ),
.tl_o (tl_if.d2h ),
@@ -57,20 +57,20 @@
// USB Interface
// TOOD: need to hook up an interface
- .cio_usb_d_i (1'b0),
- .cio_usb_dp_i (1'b1),
- .cio_usb_dn_i (1'b0),
+ .cio_d_i (1'b0),
+ .cio_dp_i (1'b1),
+ .cio_dn_i (1'b0),
- .cio_usb_d_o (),
- .cio_usb_se0_o (),
- .cio_usb_dp_o (),
- .cio_usb_dn_o (),
- .cio_usb_oe_o (),
+ .cio_d_o (),
+ .cio_se0_o (),
+ .cio_dp_o (),
+ .cio_dn_o (),
+ .cio_oe_o (),
- .cio_usb_tx_mode_se_o (),
- .cio_usb_sense_i (1'b0),
- .cio_usb_pullup_en_o (),
- .cio_usb_suspend_o (),
+ .cio_tx_mode_se_o (),
+ .cio_sense_i (1'b0),
+ .cio_pullup_en_o (),
+ .cio_suspend_o (),
// Interrupts
.intr_pkt_received_o (intr_pkt_received ),
diff --git a/hw/ip/usbdev/rtl/usbdev.sv b/hw/ip/usbdev/rtl/usbdev.sv
index b3557e7..8a0a724 100644
--- a/hw/ip/usbdev/rtl/usbdev.sv
+++ b/hw/ip/usbdev/rtl/usbdev.sv
@@ -11,27 +11,27 @@
input logic clk_i,
input logic rst_ni,
input logic clk_usb_48mhz_i, // use usb_ prefix for signals in this clk
- input logic rst_usb_ni, // async reset, with relase sync to clk_usb_48_mhz_i
+ input logic rst_usb_48mhz_ni, // async reset, with relase sync to clk_usb_48_mhz_i
// Register interface
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// USB Interface
- input logic cio_usb_d_i,
- input logic cio_usb_dp_i,
- input logic cio_usb_dn_i,
+ input logic cio_d_i,
+ input logic cio_dp_i,
+ input logic cio_dn_i,
- output logic cio_usb_d_o,
- output logic cio_usb_se0_o,
- output logic cio_usb_dp_o,
- output logic cio_usb_dn_o,
- output logic cio_usb_oe_o,
+ output logic cio_d_o,
+ output logic cio_se0_o,
+ output logic cio_dp_o,
+ output logic cio_dn_o,
+ output logic cio_oe_o,
- output logic cio_usb_tx_mode_se_o,
- input logic cio_usb_sense_i,
- output logic cio_usb_pullup_en_o,
- output logic cio_usb_suspend_o,
+ output logic cio_tx_mode_se_o,
+ input logic cio_sense_i,
+ output logic cio_pullup_en_o,
+ output logic cio_suspend_o,
// Interrupts
output logic intr_pkt_received_o, // Packet received
@@ -165,7 +165,7 @@
.wdepth (hw2reg.usbstat.av_depth.d),
.clk_rd_i (clk_usb_48mhz_i),
- .rst_rd_ni (rst_usb_ni),
+ .rst_rd_ni (rst_usb_48mhz_ni),
.rvalid (usb_av_rvalid),
.rready (usb_av_rready),
.rdata (usb_av_rdata),
@@ -177,7 +177,7 @@
.Depth(RXFifoDepth)
) usbdev_rxfifo (
.clk_wr_i (clk_usb_48mhz_i),
- .rst_wr_ni (rst_usb_ni),
+ .rst_wr_ni (rst_usb_48mhz_ni),
.wvalid (usb_rx_wvalid),
.wready (usb_rx_wready),
@@ -236,7 +236,7 @@
.Width(3*NEndpoints)
) usbdev_sync_ep_cfg (
.clk_i (clk_usb_48mhz_i),
- .rst_ni (rst_usb_ni),
+ .rst_ni (rst_usb_48mhz_ni),
.d ({enable_setup, enable_out, ep_stall}),
.q ({usb_enable_setup, usb_enable_out, usb_ep_stall})
);
@@ -266,7 +266,7 @@
.Width (NEndpoints)
) usbdev_rdysync (
.clk_i (clk_usb_48mhz_i),
- .rst_ni (rst_usb_ni),
+ .rst_ni (rst_usb_48mhz_ni),
.d (in_rdy_async),
.q (usb_in_rdy)
);
@@ -277,7 +277,7 @@
.clk_src_i (clk_i),
.clk_dst_i (clk_usb_48mhz_i),
.rst_src_ni (rst_ni),
- .rst_dst_ni (rst_usb_ni),
+ .rst_dst_ni (rst_usb_48mhz_ni),
.src_pulse_i (reg2hw.data_toggle_clear[0].qe),
.dst_pulse_o (usb_data_toggle_clear_en)
);
@@ -297,7 +297,7 @@
prim_pulse_sync usbdev_setsent (
.clk_src_i (clk_usb_48mhz_i),
.clk_dst_i (clk_i),
- .rst_src_ni (rst_usb_ni),
+ .rst_src_ni (rst_usb_48mhz_ni),
.rst_dst_ni (rst_ni),
.src_pulse_i (usb_set_sent),
.dst_pulse_o (set_sent)
@@ -322,7 +322,7 @@
prim_pulse_sync usbdev_sync_in_err (
.clk_src_i (clk_usb_48mhz_i),
.clk_dst_i (clk_i),
- .rst_src_ni (rst_usb_ni),
+ .rst_src_ni (rst_usb_48mhz_ni),
.rst_dst_ni (rst_ni),
.src_pulse_i (usb_event_in_err),
.dst_pulse_o (event_in_err)
@@ -331,7 +331,7 @@
prim_pulse_sync usbdev_outrdyclr (
.clk_src_i (clk_usb_48mhz_i),
.clk_dst_i (clk_i),
- .rst_src_ni (rst_usb_ni),
+ .rst_src_ni (rst_usb_48mhz_ni),
.rst_dst_ni (rst_ni),
.src_pulse_i (usb_setup_received),
.dst_pulse_o (setup_received)
@@ -340,7 +340,7 @@
prim_pulse_sync sync_usb_event_rx_crc_err (
.clk_src_i (clk_usb_48mhz_i),
.clk_dst_i (clk_i),
- .rst_src_ni (rst_usb_ni),
+ .rst_src_ni (rst_usb_48mhz_ni),
.rst_dst_ni (rst_ni),
.src_pulse_i (usb_event_rx_crc_err),
.dst_pulse_o (event_rx_crc_err)
@@ -349,7 +349,7 @@
prim_pulse_sync sync_usb_event_rx_pid_err (
.clk_src_i (clk_usb_48mhz_i),
.clk_dst_i (clk_i),
- .rst_src_ni (rst_usb_ni),
+ .rst_src_ni (rst_usb_48mhz_ni),
.rst_dst_ni (rst_ni),
.src_pulse_i (usb_event_rx_pid_err),
.dst_pulse_o (event_rx_pid_err)
@@ -358,7 +358,7 @@
prim_pulse_sync sync_usb_event_rx_bitstuff_err (
.clk_src_i (clk_usb_48mhz_i),
.clk_dst_i (clk_i),
- .rst_src_ni (rst_usb_ni),
+ .rst_src_ni (rst_usb_48mhz_ni),
.rst_dst_ni (rst_ni),
.src_pulse_i (usb_event_rx_bitstuff_err),
.dst_pulse_o (event_rx_bitstuff_err)
@@ -367,7 +367,7 @@
prim_pulse_sync sync_usb_event_frame (
.clk_src_i (clk_usb_48mhz_i),
.clk_dst_i (clk_i),
- .rst_src_ni (rst_usb_ni),
+ .rst_src_ni (rst_usb_48mhz_ni),
.rst_dst_ni (rst_ni),
.src_pulse_i (usb_event_frame),
.dst_pulse_o (event_frame)
@@ -375,8 +375,8 @@
logic event_link_reset_q;
- always_ff @(posedge clk_usb_48mhz_i or negedge rst_usb_ni) begin
- if (!rst_usb_ni) begin
+ always_ff @(posedge clk_usb_48mhz_i or negedge rst_usb_48mhz_ni) begin
+ if (!rst_usb_48mhz_ni) begin
event_link_reset_q <= 0;
end else begin
event_link_reset_q <= event_link_reset;
@@ -431,7 +431,7 @@
.SramAw (SramAw)
) usbdev_impl (
.clk_48mhz_i (clk_usb_48mhz_i),
- .rst_ni (rst_usb_ni),
+ .rst_ni (rst_usb_48mhz_ni),
// Pins
.usb_d_i (usb_rx_d),
@@ -517,7 +517,7 @@
.Width (1+7)
) cdc_sys_to_usb (
.clk_i (clk_usb_48mhz_i),
- .rst_ni (rst_usb_ni),
+ .rst_ni (rst_usb_48mhz_ni),
.d ({reg2hw.usbctrl.enable.q, reg2hw.usbctrl.device_address.q}),
.q ({usb_enable, usb_device_addr})
);
@@ -537,7 +537,7 @@
prim_pulse_sync usbdev_resume (
.clk_src_i (clk_usb_48mhz_i),
.clk_dst_i (clk_i),
- .rst_src_ni (rst_usb_ni),
+ .rst_src_ni (rst_usb_48mhz_ni),
.rst_dst_ni (rst_ni),
.src_pulse_i (usb_event_link_resume),
.dst_pulse_o (event_link_resume)
@@ -549,7 +549,7 @@
prim_pulse_sync usbdev_devclr (
.clk_src_i (clk_usb_48mhz_i),
.clk_dst_i (clk_i),
- .rst_src_ni (rst_usb_ni),
+ .rst_src_ni (rst_usb_48mhz_ni),
.rst_dst_ni (rst_ni),
.src_pulse_i (usb_clr_devaddr),
.dst_pulse_o (hw2reg.usbctrl.device_address.de)
@@ -560,7 +560,7 @@
prim_pulse_sync sync_usb_event_av_empty (
.clk_src_i (clk_usb_48mhz_i),
.clk_dst_i (clk_i),
- .rst_src_ni (rst_usb_ni),
+ .rst_src_ni (rst_usb_48mhz_ni),
.rst_dst_ni (rst_ni),
.src_pulse_i (usb_event_av_empty),
.dst_pulse_o (event_av_empty)
@@ -570,7 +570,7 @@
prim_pulse_sync sync_usb_event_rx_full (
.clk_src_i (clk_usb_48mhz_i),
.clk_dst_i (clk_i),
- .rst_src_ni (rst_usb_ni),
+ .rst_src_ni (rst_usb_48mhz_ni),
.rst_dst_ni (rst_ni),
.src_pulse_i (usb_event_rx_full),
.dst_pulse_o (event_rx_full)
@@ -634,7 +634,7 @@
.clk_a_i (clk_i),
.clk_b_i (clk_usb_48mhz_i),
.rst_a_ni (rst_ni),
- .rst_b_ni (rst_usb_ni),
+ .rst_b_ni (rst_usb_48mhz_ni),
.a_req_i (mem_a_req),
.a_write_i (mem_a_write),
.a_addr_i (mem_a_addr),
@@ -854,25 +854,25 @@
.clk_i (clk_i),
.rst_ni (rst_ni),
.clk_usb_48mhz_i (clk_usb_48mhz_i),
- .rst_usb_ni (rst_usb_ni),
+ .rst_usb_48mhz_ni (rst_usb_48mhz_ni),
.rx_differential_mode_i (reg2hw.phy_config.rx_differential_mode),
.tx_differential_mode_i (reg2hw.phy_config.tx_differential_mode),
.sys_reg2hw_config_i (reg2hw.phy_config),
.sys_usb_sense_o (hw2reg.usbstat.usb_sense.d),
// Chip IO
- .cio_usb_d_i (cio_usb_d_i),
- .cio_usb_dp_i (cio_usb_dp_i),
- .cio_usb_dn_i (cio_usb_dn_i),
- .cio_usb_d_o (cio_usb_d_o),
- .cio_usb_se0_o (cio_usb_se0_o),
- .cio_usb_dp_o (cio_usb_dp_o),
- .cio_usb_dn_o (cio_usb_dn_o),
- .cio_usb_oe_o (cio_usb_oe_o),
- .cio_usb_tx_mode_se_o (cio_usb_tx_mode_se_o),
- .cio_usb_sense_i (cio_usb_sense_i),
- .cio_usb_pullup_en_o (cio_usb_pullup_en_o),
- .cio_usb_suspend_o (cio_usb_suspend_o),
+ .cio_usb_d_i (cio_d_i),
+ .cio_usb_dp_i (cio_dp_i),
+ .cio_usb_dn_i (cio_dn_i),
+ .cio_usb_d_o (cio_d_o),
+ .cio_usb_se0_o (cio_se0_o),
+ .cio_usb_dp_o (cio_dp_o),
+ .cio_usb_dn_o (cio_dn_o),
+ .cio_usb_oe_o (cio_oe_o),
+ .cio_usb_tx_mode_se_o (cio_tx_mode_se_o),
+ .cio_usb_sense_i (cio_sense_i),
+ .cio_usb_pullup_en_o (cio_pullup_en_o),
+ .cio_usb_suspend_o (cio_suspend_o),
// Internal interface
.usb_rx_d_o (usb_rx_d),
diff --git a/hw/ip/usbdev/rtl/usbdev_iomux.sv b/hw/ip/usbdev/rtl/usbdev_iomux.sv
index 732ef53..826cb8e 100644
--- a/hw/ip/usbdev/rtl/usbdev_iomux.sv
+++ b/hw/ip/usbdev/rtl/usbdev_iomux.sv
@@ -15,7 +15,7 @@
input logic clk_i,
input logic rst_ni,
input logic clk_usb_48mhz_i, // use usb_ prefix for signals in this clk
- input logic rst_usb_ni,
+ input logic rst_usb_48mhz_ni,
// Configuration (quasi-static)
input logic rx_differential_mode_i,
@@ -83,7 +83,7 @@
.Width (4)
) cdc_io_to_usb (
.clk_i (clk_usb_48mhz_i),
- .rst_ni (rst_usb_ni),
+ .rst_ni (rst_usb_48mhz_ni),
.d ({cio_usb_dp_i,
cio_usb_dn_i,
cio_usb_d_i,
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 272d144..934957f 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -19,6 +19,10 @@
name: fixed
freq: "100000000"
}
+ {
+ name: usb
+ freq: "48000000"
+ }
]
resets:
[
@@ -44,6 +48,12 @@
root: sys
clk: fixed
}
+ {
+ name: usb
+ type: leaf
+ root: sys
+ clk: usb
+ }
]
num_cores: "1"
module:
@@ -534,6 +544,138 @@
alert_list: []
scan: "false"
}
+ {
+ name: usbdev
+ type: usbdev
+ clock_connections:
+ {
+ clk_i: fixed
+ clk_usb_48mhz_i: usb
+ }
+ reset_connections:
+ {
+ rst_ni: sys_fixed
+ rst_usb_48mhz_ni: usb
+ }
+ base_addr: 0x40150000
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list:
+ [
+ {
+ name: sense
+ width: 1
+ type: input
+ }
+ ]
+ available_output_list:
+ [
+ {
+ name: pullup
+ width: 1
+ type: output
+ }
+ ]
+ available_inout_list:
+ [
+ {
+ name: dp
+ width: 1
+ type: inout
+ }
+ {
+ name: dn
+ width: 1
+ type: inout
+ }
+ ]
+ interrupt_list:
+ [
+ {
+ name: pkt_received
+ width: 1
+ type: interrupt
+ }
+ {
+ name: pkt_sent
+ width: 1
+ type: interrupt
+ }
+ {
+ name: disconnected
+ width: 1
+ type: interrupt
+ }
+ {
+ name: host_lost
+ width: 1
+ type: interrupt
+ }
+ {
+ name: link_reset
+ width: 1
+ type: interrupt
+ }
+ {
+ name: link_suspend
+ width: 1
+ type: interrupt
+ }
+ {
+ name: link_resume
+ width: 1
+ type: interrupt
+ }
+ {
+ name: av_empty
+ width: 1
+ type: interrupt
+ }
+ {
+ name: rx_full
+ width: 1
+ type: interrupt
+ }
+ {
+ name: av_overflow
+ width: 1
+ type: interrupt
+ }
+ {
+ name: link_in_err
+ width: 1
+ type: interrupt
+ }
+ {
+ name: rx_crc_err
+ width: 1
+ type: interrupt
+ }
+ {
+ name: rx_pid_err
+ width: 1
+ type: interrupt
+ }
+ {
+ name: rx_bitstuff_err
+ width: 1
+ type: interrupt
+ }
+ {
+ name: frame
+ width: 1
+ type: interrupt
+ }
+ {
+ name: connected
+ width: 1
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ scan: "false"
+ }
]
memory:
[
@@ -760,6 +902,10 @@
base_addr: 0x40080000
size_byte: 0x1000
}
+ {
+ base_addr: 0x40150000
+ size_byte: 0x1000
+ }
]
}
{
@@ -901,6 +1047,7 @@
gpio
spi_device
rv_timer
+ usbdev
]
}
nodes:
@@ -983,6 +1130,23 @@
xbar: false
pipeline_byp: "true"
}
+ {
+ name: usbdev
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: usbdev
+ addr_range:
+ [
+ {
+ base_addr: 0x40150000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ pipeline_byp: "true"
+ }
]
clock: clk_peri_i
}
@@ -996,6 +1160,7 @@
hmac
alert_handler
nmi_gen
+ usbdev
]
interrupt:
[
@@ -1159,6 +1324,86 @@
width: 1
type: interrupt
}
+ {
+ name: usbdev_pkt_received
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_pkt_sent
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_disconnected
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_host_lost
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_link_reset
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_link_suspend
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_link_resume
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_av_empty
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_rx_full
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_av_overflow
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_link_in_err
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_rx_crc_err
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_rx_pid_err
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_rx_bitstuff_err
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_frame
+ width: 1
+ type: interrupt
+ }
+ {
+ name: usbdev_connected
+ width: 1
+ type: interrupt
+ }
]
alert_module:
[
@@ -1192,6 +1437,13 @@
ChA[0..1]
]
}
+ {
+ name: usbdev
+ pad:
+ [
+ ChC[0..3]
+ ]
+ }
]
mio_modules:
[
@@ -1277,6 +1529,54 @@
}
]
}
+ {
+ name: usbdev_sense
+ width: 1
+ type: input
+ pad:
+ [
+ {
+ name: ChC
+ index: 0
+ }
+ ]
+ }
+ {
+ name: usbdev_pullup
+ width: 1
+ type: output
+ pad:
+ [
+ {
+ name: ChC
+ index: 1
+ }
+ ]
+ }
+ {
+ name: usbdev_dp
+ width: 1
+ type: inout
+ pad:
+ [
+ {
+ name: ChC
+ index: 2
+ }
+ ]
+ }
+ {
+ name: usbdev_dn
+ width: 1
+ type: inout
+ pad:
+ [
+ {
+ name: ChC
+ index: 3
+ }
+ ]
+ }
]
inputs: []
outputs: []
@@ -1312,6 +1612,16 @@
WEAK
]
}
+ {
+ name: ChC
+ type: IO_33V
+ count: 4
+ attr:
+ [
+ KEEP
+ STRONG
+ ]
+ }
]
}
}
\ No newline at end of file
diff --git a/hw/top_earlgrey/data/pins_artys7.xdc b/hw/top_earlgrey/data/pins_artys7.xdc
index 0b38752..e60fe40 100644
--- a/hw/top_earlgrey/data/pins_artys7.xdc
+++ b/hw/top_earlgrey/data/pins_artys7.xdc
@@ -11,6 +11,11 @@
set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135 } [get_ports { IO_CLK }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_clk[200]
create_clock -add -name sys_clk_pin -period 10.000 -waveform {0 5.000} [get_ports { IO_CLK }];
+## Clock Domain Crossings
+create_generated_clock -name clk_50_unbuf -source [get_pin clkgen/pll/CLKIN1] [get_pin clkgen/pll/CLKOUT0]
+create_generated_clock -name clk_48_unbuf -source [get_pin clkgen/pll/CLKIN1] [get_pin clkgen/pll/CLKOUT1]
+set_clock_groups -group clk_50_unbuf -group clk_48_unbuf -asynchronous
+
## Switches
set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { IO_GP4 }]; #IO_L20N_T3_A19_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { IO_GP5 }]; #IO_L21P_T3_DQS_15 Sch=sw[1]
@@ -48,10 +53,10 @@
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja_n[4]
## PMOD Header JB
-#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L9P_T1_DQS_14 Sch=jb_p[1]
-#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L9N_T1_DQS_D13_14 Sch=jb_n[1]
-#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L10P_T1_D14_14 Sch=jb_p[2]
-#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L10N_T1_D15_14 Sch=jb_n[2]
+set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DP0 }]; #IO_L9P_T1_DQS_14 Sch=jb_p[1]
+set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DN0 }]; #IO_L9N_T1_DQS_D13_14 Sch=jb_n[1]
+set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_PULLUP0 }]; #IO_L10P_T1_D14_14 Sch=jb_p[2]
+set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_SENSE0 }]; #IO_L10N_T1_D15_14 Sch=jb_n[2]
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11P_T1_SRCC_14 Sch=jb_p[3]
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L11N_T1_SRCC_14 Sch=jb_n[3]
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L12P_T1_MRCC_14 Sch=jb_p[4]
diff --git a/hw/top_earlgrey/data/pins_nexysvideo.xdc b/hw/top_earlgrey/data/pins_nexysvideo.xdc
index d9ec661..005f23e 100644
--- a/hw/top_earlgrey/data/pins_nexysvideo.xdc
+++ b/hw/top_earlgrey/data/pins_nexysvideo.xdc
@@ -6,6 +6,11 @@
set_property -dict { PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports { IO_CLK }]; #IO_L13P_T2_MRCC_34 Sch=sysclk
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports IO_CLK]
+## Clock Domain Crossings
+create_generated_clock -name clk_50_unbuf -source [get_pin clkgen/pll/CLKIN1] [get_pin clkgen/pll/CLKOUT0]
+create_generated_clock -name clk_48_unbuf -source [get_pin clkgen/pll/CLKIN1] [get_pin clkgen/pll/CLKOUT1]
+set_clock_groups -group clk_50_unbuf -group clk_48_unbuf -asynchronous
+
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IO_SDCK_IBUF]; # SDCK clock to be ignored
## FMC Transceiver clocks (Must be set to value provided by Mezzanine card, currently set to 156.25 MHz)
@@ -121,10 +126,10 @@
set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DN0 }]; #IO_L21N_T3_DQS_34 Sch=jb_n[1]
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_PULLUP0 }]; #IO_L19P_T3_34 Sch=jb_p[2]
set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_SENSE0 }]; #IO_L19N_T3_VREF_34 Sch=jb_n[2]
-set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DP1 }]; #IO_L24P_T3_34 Sch=jb_p[3]
-set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DN1 }]; #IO_L24N_T3_34 Sch=jb_n[3]
-set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_PULLUP1 }]; #IO_L23P_T3_34 Sch=jb_p[4]
-set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_SENSE1 }]; #IO_L23N_T3_34 Sch=jb_n[4]
+#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DP1 }]; #IO_L24P_T3_34 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DN1 }]; #IO_L24N_T3_34 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_PULLUP1 }]; #IO_L23P_T3_34 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_SENSE1 }]; #IO_L23N_T3_34 Sch=jb_n[4]
## Pmod header JC
@@ -132,7 +137,7 @@
#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { IO_SDCSB }]; #IO_L18N_T2_34 Sch=jc_n[1]
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDMOSI }]; #IO_L22P_T3_34 Sch=jc_p[2]
#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDMISO }]; #IO_L22N_T3_34 Sch=jc_n[2]
-set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { IO_OBS }]; #IO_L18P_T2_34 Sch=jc_p[1]
+#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { IO_OBS }]; #IO_L18P_T2_34 Sch=jc_p[1]
#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_34 Sch=jc_n[1]
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22P_T3_34 Sch=jc_p[2]
#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L22N_T3_34 Sch=jc_n[2]
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index aa0c919..a93fc75 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -11,6 +11,7 @@
clocks: [
{ name: "main", freq: "100000000" }
{ name: "fixed", freq: "100000000" }
+ { name: "usb", freq: "48000000" }
]
// Reset attributes
@@ -23,6 +24,7 @@
{ name: "sys", type: "root", clk: "main"}
{ name: "sys_fixed", type: "leaf", root: "sys", clk: "fixed"}
{ name: "spi_device", type: "leaf", root: "sys", clk: "fixed"}
+ { name: "usb", type: "leaf", root: "sys", clk: "usb"}
]
// Number of cores: used in rv_plic and timer
@@ -120,6 +122,12 @@
reset_connections: {rst_ni: "sys"},
base_addr: "0x40140000",
}
+ { name: "usbdev",
+ type: "usbdev",
+ clock_connections: {clk_i: "fixed", clk_usb_48mhz_i: "usb"},
+ reset_connections: {rst_ni: "sys_fixed", rst_usb_48mhz_ni: "usb"},
+ base_addr: "0x40150000",
+ },
]
// Memories (ROM, RAM, eFlash) are defined at the top.
@@ -170,7 +178,7 @@
// and include every modules.
// first item goes to LSB of the interrupt source
interrupt_module: ["gpio", "uart", "spi_device", "flash_ctrl",
- "hmac", "alert_handler", "nmi_gen" ]
+ "hmac", "alert_handler", "nmi_gen", "usbdev" ]
// RV_PLIC has two searching algorithm internally to pick the most highest priority interrupt
// source. "sequential" is smaller but slower, "matrix" is larger but faster.
@@ -205,6 +213,7 @@
//{ name: "uart.tx", pad: ["ChA[0]"]},
{ name: "uart", pad: ["ChA[0..1]"]},
// { name: "dio_module.signal_input", pad: ["ChA[31]"] }
+ { name: "usbdev", pad: ["ChC[0..3]"]},
],
// Multiplexing IO modules. The in/out ports of the modules below are
@@ -240,6 +249,7 @@
pads: [
{ name: "ChA" type: "IO_33V", count: 32 }, // Accessing as ChA[0] .. ChA[31]
{ name: "ChB" type: "IO_33V", count: 4, attr: ["KEEP", "WEAK"]},
+ { name: "ChC" type: "IO_33V", count: 4, attr: ["KEEP", "STRONG"]},
]
}
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index f41c7a1..21e38c4 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -26,6 +26,9 @@
input clk_i,
input rst_ni,
+ // USB clock
+ input clk_usb_48mhz_i,
+
// JTAG interface
input jtag_tck_i,
input jtag_tms_i,
@@ -195,11 +198,16 @@
end
% endif
- // clock assignments
+ // Clock assignments
% for clock in top['clocks']:
+ % if clock['name'] != "usb" :
assign ${clock['name']}_clk = clk_i;
+ % endif
% endfor
+ // Separate clock input for USB clock
+ assign usb_clk = clk_usb_48mhz_i;
+
// Non-debug module reset == reset for everything except for the debug module
logic ndmreset_req;
@@ -209,13 +217,20 @@
assign lc_rst_n = rst_ni;
assign sys_rst_n = (scanmode_i) ? lc_rst_n : ~ndmreset_req & lc_rst_n;
- //non-root reset assignments
+ // Non-root reset assignments
% for reset in top['resets']:
- % if reset['type'] in ['leaf']:
+ % if reset['type'] in ['leaf'] and reset['name'] != "usb" :
assign ${reset['name']}_rst_n = ${reset['root']}_rst_n;
% endif
% endfor
+ // Reset synchronizer for USB
+ logic [1:0] usb_rst_q;
+ always_ff @(posedge usb_clk) begin
+ usb_rst_q <= {usb_rst_q[0], sys_rst_n};
+ end
+ assign usb_rst_n = sys_rst_n & usb_rst_q[1];
+
// debug request from rv_dm to core
logic debug_req;
@@ -522,21 +537,42 @@
.tl_h_o (tl_${m["name"]}_h_h2d),
.tl_h_i (tl_${m["name"]}_h_d2h),
% endif
- % for p_in in m["available_input_list"] + m["available_inout_list"]:
- % if loop.first:
+ % if m["type"] == "usbdev":
+
+ // Differential data - Currently not used.
+ .cio_d_i (1'b0),
+ .cio_d_o (),
+ .cio_se0_o (),
+
+ // Single-ended data
+ .cio_dp_i (cio_usbdev_dp_p2d),
+ .cio_dn_i (cio_usbdev_dn_p2d),
+ .cio_dp_o (cio_usbdev_dp_d2p),
+ .cio_dn_o (cio_usbdev_dn_d2p),
+
+ // Non-data I/O
+ .cio_sense_i (cio_usbdev_sense_p2d),
+ .cio_oe_o (cio_usbdev_dp_en_d2p),
+ .cio_tx_mode_se_o (),
+ .cio_pullup_en_o (cio_usbdev_pullup_en_d2p),
+ .cio_suspend_o (),
+ % else:
+ % for p_in in m["available_input_list"] + m["available_inout_list"]:
+ % if loop.first:
// Input
- % endif
+ % endif
.${lib.ljust("cio_"+p_in["name"]+"_i",max_sigwidth+9)} (cio_${m["name"]}_${p_in["name"]}_p2d),
- % endfor
- % for p_out in m["available_output_list"] + m["available_inout_list"]:
- % if loop.first:
+ % endfor
+ % for p_out in m["available_output_list"] + m["available_inout_list"]:
+ % if loop.first:
// Output
- % endif
+ % endif
.${lib.ljust("cio_"+p_out["name"]+"_o", max_sigwidth+9)} (cio_${m["name"]}_${p_out["name"]}_d2p),
.${lib.ljust("cio_"+p_out["name"]+"_en_o",max_sigwidth+9)} (cio_${m["name"]}_${p_out["name"]}_en_d2p),
- % endfor
+ % endfor
+ % endif
% for intr in m["interrupt_list"] if "interrupt_list" in m else []:
% if loop.first:
@@ -608,6 +644,10 @@
);
% endfor
+ // USB assignments
+ assign cio_usbdev_dn_en_d2p = cio_usbdev_dp_en_d2p; // have a single output enable only
+ assign cio_usbdev_pullup_d2p = 1'b1;
+
// interrupt assignments
assign intr_vector = {
% for intr in top["interrupt"][::-1]:
diff --git a/hw/top_earlgrey/data/xbar_peri.hjson b/hw/top_earlgrey/data/xbar_peri.hjson
index 0786baa..fe300a2 100644
--- a/hw/top_earlgrey/data/xbar_peri.hjson
+++ b/hw/top_earlgrey/data/xbar_peri.hjson
@@ -35,9 +35,15 @@
clock: "clk_peri_i",
reset: "rst_peri_ni",
pipeline: "false"
+ },
+ { name: "usbdev",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: "false"
}
],
connections: {
- main: ["uart", "gpio", "spi_device", "rv_timer"],
+ main: ["uart", "gpio", "spi_device", "rv_timer", "usbdev"],
},
}
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index 5d6ddd3..19656ba 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -16,13 +16,14 @@
`include "dv_macros.svh"
`include "chip_hier_macros.svh"
- wire clk, rst_n;
+ wire clk, clk_usb_48mhz, rst_n;
wire [NUM_GPIOS-1:0] gpio_pins;
wire jtag_tck;
wire jtag_tms;
wire jtag_trst_n;
wire jtag_tdi;
wire jtag_tdo;
+ wire usb_dp0, usb_dn0, usb_sense0, usb_pullup0;
bit stub_cpu;
@@ -33,6 +34,13 @@
uart_if uart_if();
jtag_if jtag_if();
+ // USB-related signals
+ assign clk_usb_48mhz = clk; // TODO: Generate the 48MHz clock
+ assign usb_dp0 = 1'bz; // TODO: Do something more reasonable, is I/O
+ assign usb_dn0 = 1'bz; // TODO: Do something more reasonable, is I/O
+ assign usb_sense0 = 1'bz; // TODO: Do something more reasonable, is I/O
+ // TODO: Do something reasonable with usb_pullup0
+
// backdoors
bind `ROM_HIER mem_bkdr_if rom_mem_bkdr_if();
bind `FLASH0_MEM_HIER mem_bkdr_if flash0_mem_bkdr_if();
@@ -40,34 +48,40 @@
top_earlgrey_asic dut (
// Clock and Reset
- .IO_CLK (clk),
- .IO_RST_N (rst_n),
+ .IO_CLK (clk),
+ .IO_RST_N (rst_n),
+ .IO_CLK_USB_48MHZ (clk_usb_48mhz),
// JTAG interface
- .IO_JTCK (jtag_tck),
- .IO_JTMS (jtag_tms),
- .IO_JTRST_N (jtag_trst_n),
- .IO_JTDI (jtag_tdi),
- .IO_JTDO (jtag_tdo),
+ .IO_JTCK (jtag_tck),
+ .IO_JTMS (jtag_tms),
+ .IO_JTRST_N (jtag_trst_n),
+ .IO_JTDI (jtag_tdi),
+ .IO_JTDO (jtag_tdo),
// UART interface
- .IO_URX (uart_if.uart_rx),
- .IO_UTX (uart_if.uart_tx),
+ .IO_URX (uart_if.uart_rx),
+ .IO_UTX (uart_if.uart_tx),
+ // USB interface
+ .IO_USB_DP0 (usb_dp0),
+ .IO_USB_DN0 (usb_dn0),
+ .IO_USB_SENSE0 (usb_sense0),
+ .IO_USB_PULLUP0 (usb_pullup0),
// GPIO x 16 interface
- .IO_GP0 (gpio_pins[0 ]),
- .IO_GP1 (gpio_pins[1 ]),
- .IO_GP2 (gpio_pins[2 ]),
- .IO_GP3 (gpio_pins[3 ]),
- .IO_GP4 (gpio_pins[4 ]),
- .IO_GP5 (gpio_pins[5 ]),
- .IO_GP6 (gpio_pins[6 ]),
- .IO_GP7 (gpio_pins[7 ]),
- .IO_GP8 (gpio_pins[8 ]),
- .IO_GP9 (gpio_pins[9 ]),
- .IO_GP10 (gpio_pins[10]),
- .IO_GP11 (gpio_pins[11]),
- .IO_GP12 (gpio_pins[12]),
- .IO_GP13 (gpio_pins[13]),
- .IO_GP14 (gpio_pins[14]),
- .IO_GP15 (gpio_pins[15])
+ .IO_GP0 (gpio_pins[0 ]),
+ .IO_GP1 (gpio_pins[1 ]),
+ .IO_GP2 (gpio_pins[2 ]),
+ .IO_GP3 (gpio_pins[3 ]),
+ .IO_GP4 (gpio_pins[4 ]),
+ .IO_GP5 (gpio_pins[5 ]),
+ .IO_GP6 (gpio_pins[6 ]),
+ .IO_GP7 (gpio_pins[7 ]),
+ .IO_GP8 (gpio_pins[8 ]),
+ .IO_GP9 (gpio_pins[9 ]),
+ .IO_GP10 (gpio_pins[10]),
+ .IO_GP11 (gpio_pins[11]),
+ .IO_GP12 (gpio_pins[12]),
+ .IO_GP13 (gpio_pins[13]),
+ .IO_GP14 (gpio_pins[14]),
+ .IO_GP15 (gpio_pins[15])
);
// connect sw_msg_monitor
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index 56ad460..c5c4f44 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,18 +7,18 @@
package alert_handler_reg_pkg;
// Param list
- localparam int NAlerts = 1;
- localparam int EscCntDw = 32;
- localparam int AccuCntDw = 16;
- localparam int LfsrSeed = 2147483647;
- localparam logic [NAlerts-1:0] AsyncOn = 1'b0;
- localparam int N_CLASSES = 4;
- localparam int N_ESC_SEV = 4;
- localparam int N_PHASES = 4;
- localparam int N_LOC_ALERT = 4;
- localparam int PING_CNT_DW = 24;
- localparam int PHASE_DW = 2;
- localparam int CLASS_DW = 2;
+ parameter int NAlerts = 1;
+ parameter int EscCntDw = 32;
+ parameter int AccuCntDw = 16;
+ parameter int LfsrSeed = 2147483647;
+ parameter logic [NAlerts-1:0] AsyncOn = 1'b0;
+ parameter int N_CLASSES = 4;
+ parameter int N_ESC_SEV = 4;
+ parameter int N_PHASES = 4;
+ parameter int N_LOC_ALERT = 4;
+ parameter int PING_CNT_DW = 24;
+ parameter int PHASE_DW = 2;
+ parameter int CLASS_DW = 2;
////////////////////////////
// Typedefs for registers //
@@ -526,65 +526,65 @@
} alert_handler_hw2reg_t;
// Register Address
- parameter ALERT_HANDLER_INTR_STATE_OFFSET = 8'h 0;
- parameter ALERT_HANDLER_INTR_ENABLE_OFFSET = 8'h 4;
- parameter ALERT_HANDLER_INTR_TEST_OFFSET = 8'h 8;
- parameter ALERT_HANDLER_REGEN_OFFSET = 8'h c;
- parameter ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET = 8'h 10;
- parameter ALERT_HANDLER_ALERT_EN_OFFSET = 8'h 14;
- parameter ALERT_HANDLER_ALERT_CLASS_OFFSET = 8'h 18;
- parameter ALERT_HANDLER_ALERT_CAUSE_OFFSET = 8'h 1c;
- parameter ALERT_HANDLER_LOC_ALERT_EN_OFFSET = 8'h 20;
- parameter ALERT_HANDLER_LOC_ALERT_CLASS_OFFSET = 8'h 24;
- parameter ALERT_HANDLER_LOC_ALERT_CAUSE_OFFSET = 8'h 28;
- parameter ALERT_HANDLER_CLASSA_CTRL_OFFSET = 8'h 2c;
- parameter ALERT_HANDLER_CLASSA_CLREN_OFFSET = 8'h 30;
- parameter ALERT_HANDLER_CLASSA_CLR_OFFSET = 8'h 34;
- parameter ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 8'h 38;
- parameter ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 8'h 3c;
- parameter ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 8'h 40;
- parameter ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 8'h 44;
- parameter ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 8'h 48;
- parameter ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 8'h 4c;
- parameter ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 8'h 50;
- parameter ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 8'h 54;
- parameter ALERT_HANDLER_CLASSA_STATE_OFFSET = 8'h 58;
- parameter ALERT_HANDLER_CLASSB_CTRL_OFFSET = 8'h 5c;
- parameter ALERT_HANDLER_CLASSB_CLREN_OFFSET = 8'h 60;
- parameter ALERT_HANDLER_CLASSB_CLR_OFFSET = 8'h 64;
- parameter ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 8'h 68;
- parameter ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 8'h 6c;
- parameter ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 8'h 70;
- parameter ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 8'h 74;
- parameter ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 8'h 78;
- parameter ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 8'h 7c;
- parameter ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 8'h 80;
- parameter ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 8'h 84;
- parameter ALERT_HANDLER_CLASSB_STATE_OFFSET = 8'h 88;
- parameter ALERT_HANDLER_CLASSC_CTRL_OFFSET = 8'h 8c;
- parameter ALERT_HANDLER_CLASSC_CLREN_OFFSET = 8'h 90;
- parameter ALERT_HANDLER_CLASSC_CLR_OFFSET = 8'h 94;
- parameter ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 8'h 98;
- parameter ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 8'h 9c;
- parameter ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 8'h a0;
- parameter ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 8'h a4;
- parameter ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 8'h a8;
- parameter ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 8'h ac;
- parameter ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 8'h b0;
- parameter ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 8'h b4;
- parameter ALERT_HANDLER_CLASSC_STATE_OFFSET = 8'h b8;
- parameter ALERT_HANDLER_CLASSD_CTRL_OFFSET = 8'h bc;
- parameter ALERT_HANDLER_CLASSD_CLREN_OFFSET = 8'h c0;
- parameter ALERT_HANDLER_CLASSD_CLR_OFFSET = 8'h c4;
- parameter ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 8'h c8;
- parameter ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 8'h cc;
- parameter ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 8'h d0;
- parameter ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 8'h d4;
- parameter ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 8'h d8;
- parameter ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 8'h dc;
- parameter ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 8'h e0;
- parameter ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 8'h e4;
- parameter ALERT_HANDLER_CLASSD_STATE_OFFSET = 8'h e8;
+ parameter logic [7:0] ALERT_HANDLER_INTR_STATE_OFFSET = 8'h 0;
+ parameter logic [7:0] ALERT_HANDLER_INTR_ENABLE_OFFSET = 8'h 4;
+ parameter logic [7:0] ALERT_HANDLER_INTR_TEST_OFFSET = 8'h 8;
+ parameter logic [7:0] ALERT_HANDLER_REGEN_OFFSET = 8'h c;
+ parameter logic [7:0] ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET = 8'h 10;
+ parameter logic [7:0] ALERT_HANDLER_ALERT_EN_OFFSET = 8'h 14;
+ parameter logic [7:0] ALERT_HANDLER_ALERT_CLASS_OFFSET = 8'h 18;
+ parameter logic [7:0] ALERT_HANDLER_ALERT_CAUSE_OFFSET = 8'h 1c;
+ parameter logic [7:0] ALERT_HANDLER_LOC_ALERT_EN_OFFSET = 8'h 20;
+ parameter logic [7:0] ALERT_HANDLER_LOC_ALERT_CLASS_OFFSET = 8'h 24;
+ parameter logic [7:0] ALERT_HANDLER_LOC_ALERT_CAUSE_OFFSET = 8'h 28;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 8'h 2c;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_CLREN_OFFSET = 8'h 30;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 8'h 34;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 8'h 38;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 8'h 3c;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 8'h 40;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 8'h 44;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 8'h 48;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 8'h 4c;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 8'h 50;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 8'h 54;
+ parameter logic [7:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 8'h 58;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 8'h 5c;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_CLREN_OFFSET = 8'h 60;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 8'h 64;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 8'h 68;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 8'h 6c;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 8'h 70;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 8'h 74;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 8'h 78;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 8'h 7c;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 8'h 80;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 8'h 84;
+ parameter logic [7:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 8'h 88;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 8'h 8c;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_CLREN_OFFSET = 8'h 90;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 8'h 94;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 8'h 98;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 8'h 9c;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 8'h a0;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 8'h a4;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 8'h a8;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 8'h ac;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 8'h b0;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 8'h b4;
+ parameter logic [7:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 8'h b8;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 8'h bc;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_CLREN_OFFSET = 8'h c0;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 8'h c4;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 8'h c8;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 8'h cc;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 8'h d0;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 8'h d4;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 8'h d8;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 8'h dc;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 8'h e0;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 8'h e4;
+ parameter logic [7:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 8'h e8;
// Register Index
@@ -651,7 +651,7 @@
} alert_handler_id_e;
// Register width information to check illegal writes
- localparam logic [3:0] ALERT_HANDLER_PERMIT [59] = '{
+ parameter logic [3:0] ALERT_HANDLER_PERMIT [59] = '{
4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE
4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE
4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index b267bb6..0194ed8 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -21,9 +21,9 @@
import alert_handler_reg_pkg::* ;
- localparam AW = 8;
- localparam DW = 32;
- localparam DBW = DW/8; // Byte Width
+ localparam int AW = 8;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
// register signals
logic reg_we;
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
index a157c1a..e5199d3 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
@@ -7,9 +7,9 @@
package pinmux_reg_pkg;
// Param list
- localparam int NPeriphIn = 32;
- localparam int NPeriphOut = 32;
- localparam int NMioPads = 32;
+ parameter int NPeriphIn = 32;
+ parameter int NPeriphOut = 32;
+ parameter int NMioPads = 32;
////////////////////////////
// Typedefs for registers //
@@ -37,21 +37,21 @@
///////////////////////////////////////
// Register Address
- parameter PINMUX_REGEN_OFFSET = 6'h 0;
- parameter PINMUX_PERIPH_INSEL0_OFFSET = 6'h 4;
- parameter PINMUX_PERIPH_INSEL1_OFFSET = 6'h 8;
- parameter PINMUX_PERIPH_INSEL2_OFFSET = 6'h c;
- parameter PINMUX_PERIPH_INSEL3_OFFSET = 6'h 10;
- parameter PINMUX_PERIPH_INSEL4_OFFSET = 6'h 14;
- parameter PINMUX_PERIPH_INSEL5_OFFSET = 6'h 18;
- parameter PINMUX_PERIPH_INSEL6_OFFSET = 6'h 1c;
- parameter PINMUX_MIO_OUTSEL0_OFFSET = 6'h 20;
- parameter PINMUX_MIO_OUTSEL1_OFFSET = 6'h 24;
- parameter PINMUX_MIO_OUTSEL2_OFFSET = 6'h 28;
- parameter PINMUX_MIO_OUTSEL3_OFFSET = 6'h 2c;
- parameter PINMUX_MIO_OUTSEL4_OFFSET = 6'h 30;
- parameter PINMUX_MIO_OUTSEL5_OFFSET = 6'h 34;
- parameter PINMUX_MIO_OUTSEL6_OFFSET = 6'h 38;
+ parameter logic [5:0] PINMUX_REGEN_OFFSET = 6'h 0;
+ parameter logic [5:0] PINMUX_PERIPH_INSEL0_OFFSET = 6'h 4;
+ parameter logic [5:0] PINMUX_PERIPH_INSEL1_OFFSET = 6'h 8;
+ parameter logic [5:0] PINMUX_PERIPH_INSEL2_OFFSET = 6'h c;
+ parameter logic [5:0] PINMUX_PERIPH_INSEL3_OFFSET = 6'h 10;
+ parameter logic [5:0] PINMUX_PERIPH_INSEL4_OFFSET = 6'h 14;
+ parameter logic [5:0] PINMUX_PERIPH_INSEL5_OFFSET = 6'h 18;
+ parameter logic [5:0] PINMUX_PERIPH_INSEL6_OFFSET = 6'h 1c;
+ parameter logic [5:0] PINMUX_MIO_OUTSEL0_OFFSET = 6'h 20;
+ parameter logic [5:0] PINMUX_MIO_OUTSEL1_OFFSET = 6'h 24;
+ parameter logic [5:0] PINMUX_MIO_OUTSEL2_OFFSET = 6'h 28;
+ parameter logic [5:0] PINMUX_MIO_OUTSEL3_OFFSET = 6'h 2c;
+ parameter logic [5:0] PINMUX_MIO_OUTSEL4_OFFSET = 6'h 30;
+ parameter logic [5:0] PINMUX_MIO_OUTSEL5_OFFSET = 6'h 34;
+ parameter logic [5:0] PINMUX_MIO_OUTSEL6_OFFSET = 6'h 38;
// Register Index
@@ -74,7 +74,7 @@
} pinmux_id_e;
// Register width information to check illegal writes
- localparam logic [3:0] PINMUX_PERMIT [15] = '{
+ parameter logic [3:0] PINMUX_PERMIT [15] = '{
4'b 0001, // index[ 0] PINMUX_REGEN
4'b 1111, // index[ 1] PINMUX_PERIPH_INSEL0
4'b 1111, // index[ 2] PINMUX_PERIPH_INSEL1
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
index 984d096..58f3a5d 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -20,9 +20,9 @@
import pinmux_reg_pkg::* ;
- localparam AW = 6;
- localparam DW = 32;
- localparam DBW = DW/8; // Byte Width
+ localparam int AW = 6;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
// register signals
logic reg_we;
diff --git a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
index 2106f27..111e014 100644
--- a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
+++ b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
@@ -25,7 +25,7 @@
{ name: "NumSrc",
desc: "Number of interrupt sources",
type: "int",
- default: "63",
+ default: "79",
local: "true"
},
{ name: "NumTarget",
@@ -565,6 +565,134 @@
{ bits: "1:0" }
],
}
+ { name: "PRIO63",
+ desc: "Interrupt Source 63 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO64",
+ desc: "Interrupt Source 64 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO65",
+ desc: "Interrupt Source 65 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO66",
+ desc: "Interrupt Source 66 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO67",
+ desc: "Interrupt Source 67 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO68",
+ desc: "Interrupt Source 68 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO69",
+ desc: "Interrupt Source 69 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO70",
+ desc: "Interrupt Source 70 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO71",
+ desc: "Interrupt Source 71 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO72",
+ desc: "Interrupt Source 72 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO73",
+ desc: "Interrupt Source 73 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO74",
+ desc: "Interrupt Source 74 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO75",
+ desc: "Interrupt Source 75 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO76",
+ desc: "Interrupt Source 76 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO77",
+ desc: "Interrupt Source 77 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO78",
+ desc: "Interrupt Source 78 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
{ skipto: "512" }
{ multireg: {
name: "IE0",
@@ -595,7 +723,7 @@
hwqe: "true",
hwre: "true",
fields: [
- { bits: "5:0" }
+ { bits: "6:0" }
],
}
{ name: "MSIP0",
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
index 28acb95..22acd2b 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
@@ -159,11 +159,27 @@
assign prio[60] = reg2hw.prio60.q;
assign prio[61] = reg2hw.prio61.q;
assign prio[62] = reg2hw.prio62.q;
+ assign prio[63] = reg2hw.prio63.q;
+ assign prio[64] = reg2hw.prio64.q;
+ assign prio[65] = reg2hw.prio65.q;
+ assign prio[66] = reg2hw.prio66.q;
+ assign prio[67] = reg2hw.prio67.q;
+ assign prio[68] = reg2hw.prio68.q;
+ assign prio[69] = reg2hw.prio69.q;
+ assign prio[70] = reg2hw.prio70.q;
+ assign prio[71] = reg2hw.prio71.q;
+ assign prio[72] = reg2hw.prio72.q;
+ assign prio[73] = reg2hw.prio73.q;
+ assign prio[74] = reg2hw.prio74.q;
+ assign prio[75] = reg2hw.prio75.q;
+ assign prio[76] = reg2hw.prio76.q;
+ assign prio[77] = reg2hw.prio77.q;
+ assign prio[78] = reg2hw.prio78.q;
//////////////////////
// Interrupt Enable //
//////////////////////
- for (genvar s = 0; s < 63; s++) begin : gen_ie0
+ for (genvar s = 0; s < 79; s++) begin : gen_ie0
assign ie[0][s] = reg2hw.ie0[s].q;
end
@@ -189,7 +205,7 @@
////////
// IP //
////////
- for (genvar s = 0; s < 63; s++) begin : gen_ip
+ for (genvar s = 0; s < 79; s++) begin : gen_ip
assign hw2reg.ip[s].de = 1'b1; // Always write
assign hw2reg.ip[s].d = ip[s];
end
@@ -197,7 +213,7 @@
///////////////////////////////////
// Detection:: 0: Level, 1: Edge //
///////////////////////////////////
- for (genvar s = 0; s < 63; s++) begin : gen_le
+ for (genvar s = 0; s < 79; s++) begin : gen_le
assign le[s] = reg2hw.le[s].q;
end
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
index dabca79..265daf1 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
@@ -7,8 +7,8 @@
package rv_plic_reg_pkg;
// Param list
- localparam int NumSrc = 63;
- localparam int NumTarget = 1;
+ parameter int NumSrc = 79;
+ parameter int NumTarget = 1;
////////////////////////////
// Typedefs for registers //
@@ -270,6 +270,70 @@
} rv_plic_reg2hw_prio62_reg_t;
typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio63_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio64_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio65_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio66_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio67_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio68_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio69_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio70_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio71_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio72_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio73_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio74_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio75_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio76_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio77_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio78_reg_t;
+
+ typedef struct packed {
logic q;
} rv_plic_reg2hw_ie0_mreg_t;
@@ -278,7 +342,7 @@
} rv_plic_reg2hw_threshold0_reg_t;
typedef struct packed {
- logic [5:0] q;
+ logic [6:0] q;
logic qe;
logic re;
} rv_plic_reg2hw_cc0_reg_t;
@@ -294,7 +358,7 @@
} rv_plic_hw2reg_ip_mreg_t;
typedef struct packed {
- logic [5:0] d;
+ logic [6:0] d;
} rv_plic_hw2reg_cc0_reg_t;
@@ -302,73 +366,89 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- rv_plic_reg2hw_le_mreg_t [62:0] le; // [262:200]
- rv_plic_reg2hw_prio0_reg_t prio0; // [199:198]
- rv_plic_reg2hw_prio1_reg_t prio1; // [197:196]
- rv_plic_reg2hw_prio2_reg_t prio2; // [195:194]
- rv_plic_reg2hw_prio3_reg_t prio3; // [193:192]
- rv_plic_reg2hw_prio4_reg_t prio4; // [191:190]
- rv_plic_reg2hw_prio5_reg_t prio5; // [189:188]
- rv_plic_reg2hw_prio6_reg_t prio6; // [187:186]
- rv_plic_reg2hw_prio7_reg_t prio7; // [185:184]
- rv_plic_reg2hw_prio8_reg_t prio8; // [183:182]
- rv_plic_reg2hw_prio9_reg_t prio9; // [181:180]
- rv_plic_reg2hw_prio10_reg_t prio10; // [179:178]
- rv_plic_reg2hw_prio11_reg_t prio11; // [177:176]
- rv_plic_reg2hw_prio12_reg_t prio12; // [175:174]
- rv_plic_reg2hw_prio13_reg_t prio13; // [173:172]
- rv_plic_reg2hw_prio14_reg_t prio14; // [171:170]
- rv_plic_reg2hw_prio15_reg_t prio15; // [169:168]
- rv_plic_reg2hw_prio16_reg_t prio16; // [167:166]
- rv_plic_reg2hw_prio17_reg_t prio17; // [165:164]
- rv_plic_reg2hw_prio18_reg_t prio18; // [163:162]
- rv_plic_reg2hw_prio19_reg_t prio19; // [161:160]
- rv_plic_reg2hw_prio20_reg_t prio20; // [159:158]
- rv_plic_reg2hw_prio21_reg_t prio21; // [157:156]
- rv_plic_reg2hw_prio22_reg_t prio22; // [155:154]
- rv_plic_reg2hw_prio23_reg_t prio23; // [153:152]
- rv_plic_reg2hw_prio24_reg_t prio24; // [151:150]
- rv_plic_reg2hw_prio25_reg_t prio25; // [149:148]
- rv_plic_reg2hw_prio26_reg_t prio26; // [147:146]
- rv_plic_reg2hw_prio27_reg_t prio27; // [145:144]
- rv_plic_reg2hw_prio28_reg_t prio28; // [143:142]
- rv_plic_reg2hw_prio29_reg_t prio29; // [141:140]
- rv_plic_reg2hw_prio30_reg_t prio30; // [139:138]
- rv_plic_reg2hw_prio31_reg_t prio31; // [137:136]
- rv_plic_reg2hw_prio32_reg_t prio32; // [135:134]
- rv_plic_reg2hw_prio33_reg_t prio33; // [133:132]
- rv_plic_reg2hw_prio34_reg_t prio34; // [131:130]
- rv_plic_reg2hw_prio35_reg_t prio35; // [129:128]
- rv_plic_reg2hw_prio36_reg_t prio36; // [127:126]
- rv_plic_reg2hw_prio37_reg_t prio37; // [125:124]
- rv_plic_reg2hw_prio38_reg_t prio38; // [123:122]
- rv_plic_reg2hw_prio39_reg_t prio39; // [121:120]
- rv_plic_reg2hw_prio40_reg_t prio40; // [119:118]
- rv_plic_reg2hw_prio41_reg_t prio41; // [117:116]
- rv_plic_reg2hw_prio42_reg_t prio42; // [115:114]
- rv_plic_reg2hw_prio43_reg_t prio43; // [113:112]
- rv_plic_reg2hw_prio44_reg_t prio44; // [111:110]
- rv_plic_reg2hw_prio45_reg_t prio45; // [109:108]
- rv_plic_reg2hw_prio46_reg_t prio46; // [107:106]
- rv_plic_reg2hw_prio47_reg_t prio47; // [105:104]
- rv_plic_reg2hw_prio48_reg_t prio48; // [103:102]
- rv_plic_reg2hw_prio49_reg_t prio49; // [101:100]
- rv_plic_reg2hw_prio50_reg_t prio50; // [99:98]
- rv_plic_reg2hw_prio51_reg_t prio51; // [97:96]
- rv_plic_reg2hw_prio52_reg_t prio52; // [95:94]
- rv_plic_reg2hw_prio53_reg_t prio53; // [93:92]
- rv_plic_reg2hw_prio54_reg_t prio54; // [91:90]
- rv_plic_reg2hw_prio55_reg_t prio55; // [89:88]
- rv_plic_reg2hw_prio56_reg_t prio56; // [87:86]
- rv_plic_reg2hw_prio57_reg_t prio57; // [85:84]
- rv_plic_reg2hw_prio58_reg_t prio58; // [83:82]
- rv_plic_reg2hw_prio59_reg_t prio59; // [81:80]
- rv_plic_reg2hw_prio60_reg_t prio60; // [79:78]
- rv_plic_reg2hw_prio61_reg_t prio61; // [77:76]
- rv_plic_reg2hw_prio62_reg_t prio62; // [75:74]
- rv_plic_reg2hw_ie0_mreg_t [62:0] ie0; // [73:11]
- rv_plic_reg2hw_threshold0_reg_t threshold0; // [10:9]
- rv_plic_reg2hw_cc0_reg_t cc0; // [8:1]
+ rv_plic_reg2hw_le_mreg_t [78:0] le; // [327:249]
+ rv_plic_reg2hw_prio0_reg_t prio0; // [248:247]
+ rv_plic_reg2hw_prio1_reg_t prio1; // [246:245]
+ rv_plic_reg2hw_prio2_reg_t prio2; // [244:243]
+ rv_plic_reg2hw_prio3_reg_t prio3; // [242:241]
+ rv_plic_reg2hw_prio4_reg_t prio4; // [240:239]
+ rv_plic_reg2hw_prio5_reg_t prio5; // [238:237]
+ rv_plic_reg2hw_prio6_reg_t prio6; // [236:235]
+ rv_plic_reg2hw_prio7_reg_t prio7; // [234:233]
+ rv_plic_reg2hw_prio8_reg_t prio8; // [232:231]
+ rv_plic_reg2hw_prio9_reg_t prio9; // [230:229]
+ rv_plic_reg2hw_prio10_reg_t prio10; // [228:227]
+ rv_plic_reg2hw_prio11_reg_t prio11; // [226:225]
+ rv_plic_reg2hw_prio12_reg_t prio12; // [224:223]
+ rv_plic_reg2hw_prio13_reg_t prio13; // [222:221]
+ rv_plic_reg2hw_prio14_reg_t prio14; // [220:219]
+ rv_plic_reg2hw_prio15_reg_t prio15; // [218:217]
+ rv_plic_reg2hw_prio16_reg_t prio16; // [216:215]
+ rv_plic_reg2hw_prio17_reg_t prio17; // [214:213]
+ rv_plic_reg2hw_prio18_reg_t prio18; // [212:211]
+ rv_plic_reg2hw_prio19_reg_t prio19; // [210:209]
+ rv_plic_reg2hw_prio20_reg_t prio20; // [208:207]
+ rv_plic_reg2hw_prio21_reg_t prio21; // [206:205]
+ rv_plic_reg2hw_prio22_reg_t prio22; // [204:203]
+ rv_plic_reg2hw_prio23_reg_t prio23; // [202:201]
+ rv_plic_reg2hw_prio24_reg_t prio24; // [200:199]
+ rv_plic_reg2hw_prio25_reg_t prio25; // [198:197]
+ rv_plic_reg2hw_prio26_reg_t prio26; // [196:195]
+ rv_plic_reg2hw_prio27_reg_t prio27; // [194:193]
+ rv_plic_reg2hw_prio28_reg_t prio28; // [192:191]
+ rv_plic_reg2hw_prio29_reg_t prio29; // [190:189]
+ rv_plic_reg2hw_prio30_reg_t prio30; // [188:187]
+ rv_plic_reg2hw_prio31_reg_t prio31; // [186:185]
+ rv_plic_reg2hw_prio32_reg_t prio32; // [184:183]
+ rv_plic_reg2hw_prio33_reg_t prio33; // [182:181]
+ rv_plic_reg2hw_prio34_reg_t prio34; // [180:179]
+ rv_plic_reg2hw_prio35_reg_t prio35; // [178:177]
+ rv_plic_reg2hw_prio36_reg_t prio36; // [176:175]
+ rv_plic_reg2hw_prio37_reg_t prio37; // [174:173]
+ rv_plic_reg2hw_prio38_reg_t prio38; // [172:171]
+ rv_plic_reg2hw_prio39_reg_t prio39; // [170:169]
+ rv_plic_reg2hw_prio40_reg_t prio40; // [168:167]
+ rv_plic_reg2hw_prio41_reg_t prio41; // [166:165]
+ rv_plic_reg2hw_prio42_reg_t prio42; // [164:163]
+ rv_plic_reg2hw_prio43_reg_t prio43; // [162:161]
+ rv_plic_reg2hw_prio44_reg_t prio44; // [160:159]
+ rv_plic_reg2hw_prio45_reg_t prio45; // [158:157]
+ rv_plic_reg2hw_prio46_reg_t prio46; // [156:155]
+ rv_plic_reg2hw_prio47_reg_t prio47; // [154:153]
+ rv_plic_reg2hw_prio48_reg_t prio48; // [152:151]
+ rv_plic_reg2hw_prio49_reg_t prio49; // [150:149]
+ rv_plic_reg2hw_prio50_reg_t prio50; // [148:147]
+ rv_plic_reg2hw_prio51_reg_t prio51; // [146:145]
+ rv_plic_reg2hw_prio52_reg_t prio52; // [144:143]
+ rv_plic_reg2hw_prio53_reg_t prio53; // [142:141]
+ rv_plic_reg2hw_prio54_reg_t prio54; // [140:139]
+ rv_plic_reg2hw_prio55_reg_t prio55; // [138:137]
+ rv_plic_reg2hw_prio56_reg_t prio56; // [136:135]
+ rv_plic_reg2hw_prio57_reg_t prio57; // [134:133]
+ rv_plic_reg2hw_prio58_reg_t prio58; // [132:131]
+ rv_plic_reg2hw_prio59_reg_t prio59; // [130:129]
+ rv_plic_reg2hw_prio60_reg_t prio60; // [128:127]
+ rv_plic_reg2hw_prio61_reg_t prio61; // [126:125]
+ rv_plic_reg2hw_prio62_reg_t prio62; // [124:123]
+ rv_plic_reg2hw_prio63_reg_t prio63; // [122:121]
+ rv_plic_reg2hw_prio64_reg_t prio64; // [120:119]
+ rv_plic_reg2hw_prio65_reg_t prio65; // [118:117]
+ rv_plic_reg2hw_prio66_reg_t prio66; // [116:115]
+ rv_plic_reg2hw_prio67_reg_t prio67; // [114:113]
+ rv_plic_reg2hw_prio68_reg_t prio68; // [112:111]
+ rv_plic_reg2hw_prio69_reg_t prio69; // [110:109]
+ rv_plic_reg2hw_prio70_reg_t prio70; // [108:107]
+ rv_plic_reg2hw_prio71_reg_t prio71; // [106:105]
+ rv_plic_reg2hw_prio72_reg_t prio72; // [104:103]
+ rv_plic_reg2hw_prio73_reg_t prio73; // [102:101]
+ rv_plic_reg2hw_prio74_reg_t prio74; // [100:99]
+ rv_plic_reg2hw_prio75_reg_t prio75; // [98:97]
+ rv_plic_reg2hw_prio76_reg_t prio76; // [96:95]
+ rv_plic_reg2hw_prio77_reg_t prio77; // [94:93]
+ rv_plic_reg2hw_prio78_reg_t prio78; // [92:91]
+ rv_plic_reg2hw_ie0_mreg_t [78:0] ie0; // [90:12]
+ rv_plic_reg2hw_threshold0_reg_t threshold0; // [11:10]
+ rv_plic_reg2hw_cc0_reg_t cc0; // [9:1]
rv_plic_reg2hw_msip0_reg_t msip0; // [0:0]
} rv_plic_reg2hw_t;
@@ -376,91 +456,112 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- rv_plic_hw2reg_ip_mreg_t [62:0] ip; // [131:6]
- rv_plic_hw2reg_cc0_reg_t cc0; // [5:-2]
+ rv_plic_hw2reg_ip_mreg_t [78:0] ip; // [164:7]
+ rv_plic_hw2reg_cc0_reg_t cc0; // [6:-2]
} rv_plic_hw2reg_t;
// Register Address
- parameter RV_PLIC_IP0_OFFSET = 10'h 0;
- parameter RV_PLIC_IP1_OFFSET = 10'h 4;
- parameter RV_PLIC_LE0_OFFSET = 10'h 8;
- parameter RV_PLIC_LE1_OFFSET = 10'h c;
- parameter RV_PLIC_PRIO0_OFFSET = 10'h 10;
- parameter RV_PLIC_PRIO1_OFFSET = 10'h 14;
- parameter RV_PLIC_PRIO2_OFFSET = 10'h 18;
- parameter RV_PLIC_PRIO3_OFFSET = 10'h 1c;
- parameter RV_PLIC_PRIO4_OFFSET = 10'h 20;
- parameter RV_PLIC_PRIO5_OFFSET = 10'h 24;
- parameter RV_PLIC_PRIO6_OFFSET = 10'h 28;
- parameter RV_PLIC_PRIO7_OFFSET = 10'h 2c;
- parameter RV_PLIC_PRIO8_OFFSET = 10'h 30;
- parameter RV_PLIC_PRIO9_OFFSET = 10'h 34;
- parameter RV_PLIC_PRIO10_OFFSET = 10'h 38;
- parameter RV_PLIC_PRIO11_OFFSET = 10'h 3c;
- parameter RV_PLIC_PRIO12_OFFSET = 10'h 40;
- parameter RV_PLIC_PRIO13_OFFSET = 10'h 44;
- parameter RV_PLIC_PRIO14_OFFSET = 10'h 48;
- parameter RV_PLIC_PRIO15_OFFSET = 10'h 4c;
- parameter RV_PLIC_PRIO16_OFFSET = 10'h 50;
- parameter RV_PLIC_PRIO17_OFFSET = 10'h 54;
- parameter RV_PLIC_PRIO18_OFFSET = 10'h 58;
- parameter RV_PLIC_PRIO19_OFFSET = 10'h 5c;
- parameter RV_PLIC_PRIO20_OFFSET = 10'h 60;
- parameter RV_PLIC_PRIO21_OFFSET = 10'h 64;
- parameter RV_PLIC_PRIO22_OFFSET = 10'h 68;
- parameter RV_PLIC_PRIO23_OFFSET = 10'h 6c;
- parameter RV_PLIC_PRIO24_OFFSET = 10'h 70;
- parameter RV_PLIC_PRIO25_OFFSET = 10'h 74;
- parameter RV_PLIC_PRIO26_OFFSET = 10'h 78;
- parameter RV_PLIC_PRIO27_OFFSET = 10'h 7c;
- parameter RV_PLIC_PRIO28_OFFSET = 10'h 80;
- parameter RV_PLIC_PRIO29_OFFSET = 10'h 84;
- parameter RV_PLIC_PRIO30_OFFSET = 10'h 88;
- parameter RV_PLIC_PRIO31_OFFSET = 10'h 8c;
- parameter RV_PLIC_PRIO32_OFFSET = 10'h 90;
- parameter RV_PLIC_PRIO33_OFFSET = 10'h 94;
- parameter RV_PLIC_PRIO34_OFFSET = 10'h 98;
- parameter RV_PLIC_PRIO35_OFFSET = 10'h 9c;
- parameter RV_PLIC_PRIO36_OFFSET = 10'h a0;
- parameter RV_PLIC_PRIO37_OFFSET = 10'h a4;
- parameter RV_PLIC_PRIO38_OFFSET = 10'h a8;
- parameter RV_PLIC_PRIO39_OFFSET = 10'h ac;
- parameter RV_PLIC_PRIO40_OFFSET = 10'h b0;
- parameter RV_PLIC_PRIO41_OFFSET = 10'h b4;
- parameter RV_PLIC_PRIO42_OFFSET = 10'h b8;
- parameter RV_PLIC_PRIO43_OFFSET = 10'h bc;
- parameter RV_PLIC_PRIO44_OFFSET = 10'h c0;
- parameter RV_PLIC_PRIO45_OFFSET = 10'h c4;
- parameter RV_PLIC_PRIO46_OFFSET = 10'h c8;
- parameter RV_PLIC_PRIO47_OFFSET = 10'h cc;
- parameter RV_PLIC_PRIO48_OFFSET = 10'h d0;
- parameter RV_PLIC_PRIO49_OFFSET = 10'h d4;
- parameter RV_PLIC_PRIO50_OFFSET = 10'h d8;
- parameter RV_PLIC_PRIO51_OFFSET = 10'h dc;
- parameter RV_PLIC_PRIO52_OFFSET = 10'h e0;
- parameter RV_PLIC_PRIO53_OFFSET = 10'h e4;
- parameter RV_PLIC_PRIO54_OFFSET = 10'h e8;
- parameter RV_PLIC_PRIO55_OFFSET = 10'h ec;
- parameter RV_PLIC_PRIO56_OFFSET = 10'h f0;
- parameter RV_PLIC_PRIO57_OFFSET = 10'h f4;
- parameter RV_PLIC_PRIO58_OFFSET = 10'h f8;
- parameter RV_PLIC_PRIO59_OFFSET = 10'h fc;
- parameter RV_PLIC_PRIO60_OFFSET = 10'h 100;
- parameter RV_PLIC_PRIO61_OFFSET = 10'h 104;
- parameter RV_PLIC_PRIO62_OFFSET = 10'h 108;
- parameter RV_PLIC_IE00_OFFSET = 10'h 200;
- parameter RV_PLIC_IE01_OFFSET = 10'h 204;
- parameter RV_PLIC_THRESHOLD0_OFFSET = 10'h 208;
- parameter RV_PLIC_CC0_OFFSET = 10'h 20c;
- parameter RV_PLIC_MSIP0_OFFSET = 10'h 210;
+ parameter logic [9:0] RV_PLIC_IP0_OFFSET = 10'h 0;
+ parameter logic [9:0] RV_PLIC_IP1_OFFSET = 10'h 4;
+ parameter logic [9:0] RV_PLIC_IP2_OFFSET = 10'h 8;
+ parameter logic [9:0] RV_PLIC_LE0_OFFSET = 10'h c;
+ parameter logic [9:0] RV_PLIC_LE1_OFFSET = 10'h 10;
+ parameter logic [9:0] RV_PLIC_LE2_OFFSET = 10'h 14;
+ parameter logic [9:0] RV_PLIC_PRIO0_OFFSET = 10'h 18;
+ parameter logic [9:0] RV_PLIC_PRIO1_OFFSET = 10'h 1c;
+ parameter logic [9:0] RV_PLIC_PRIO2_OFFSET = 10'h 20;
+ parameter logic [9:0] RV_PLIC_PRIO3_OFFSET = 10'h 24;
+ parameter logic [9:0] RV_PLIC_PRIO4_OFFSET = 10'h 28;
+ parameter logic [9:0] RV_PLIC_PRIO5_OFFSET = 10'h 2c;
+ parameter logic [9:0] RV_PLIC_PRIO6_OFFSET = 10'h 30;
+ parameter logic [9:0] RV_PLIC_PRIO7_OFFSET = 10'h 34;
+ parameter logic [9:0] RV_PLIC_PRIO8_OFFSET = 10'h 38;
+ parameter logic [9:0] RV_PLIC_PRIO9_OFFSET = 10'h 3c;
+ parameter logic [9:0] RV_PLIC_PRIO10_OFFSET = 10'h 40;
+ parameter logic [9:0] RV_PLIC_PRIO11_OFFSET = 10'h 44;
+ parameter logic [9:0] RV_PLIC_PRIO12_OFFSET = 10'h 48;
+ parameter logic [9:0] RV_PLIC_PRIO13_OFFSET = 10'h 4c;
+ parameter logic [9:0] RV_PLIC_PRIO14_OFFSET = 10'h 50;
+ parameter logic [9:0] RV_PLIC_PRIO15_OFFSET = 10'h 54;
+ parameter logic [9:0] RV_PLIC_PRIO16_OFFSET = 10'h 58;
+ parameter logic [9:0] RV_PLIC_PRIO17_OFFSET = 10'h 5c;
+ parameter logic [9:0] RV_PLIC_PRIO18_OFFSET = 10'h 60;
+ parameter logic [9:0] RV_PLIC_PRIO19_OFFSET = 10'h 64;
+ parameter logic [9:0] RV_PLIC_PRIO20_OFFSET = 10'h 68;
+ parameter logic [9:0] RV_PLIC_PRIO21_OFFSET = 10'h 6c;
+ parameter logic [9:0] RV_PLIC_PRIO22_OFFSET = 10'h 70;
+ parameter logic [9:0] RV_PLIC_PRIO23_OFFSET = 10'h 74;
+ parameter logic [9:0] RV_PLIC_PRIO24_OFFSET = 10'h 78;
+ parameter logic [9:0] RV_PLIC_PRIO25_OFFSET = 10'h 7c;
+ parameter logic [9:0] RV_PLIC_PRIO26_OFFSET = 10'h 80;
+ parameter logic [9:0] RV_PLIC_PRIO27_OFFSET = 10'h 84;
+ parameter logic [9:0] RV_PLIC_PRIO28_OFFSET = 10'h 88;
+ parameter logic [9:0] RV_PLIC_PRIO29_OFFSET = 10'h 8c;
+ parameter logic [9:0] RV_PLIC_PRIO30_OFFSET = 10'h 90;
+ parameter logic [9:0] RV_PLIC_PRIO31_OFFSET = 10'h 94;
+ parameter logic [9:0] RV_PLIC_PRIO32_OFFSET = 10'h 98;
+ parameter logic [9:0] RV_PLIC_PRIO33_OFFSET = 10'h 9c;
+ parameter logic [9:0] RV_PLIC_PRIO34_OFFSET = 10'h a0;
+ parameter logic [9:0] RV_PLIC_PRIO35_OFFSET = 10'h a4;
+ parameter logic [9:0] RV_PLIC_PRIO36_OFFSET = 10'h a8;
+ parameter logic [9:0] RV_PLIC_PRIO37_OFFSET = 10'h ac;
+ parameter logic [9:0] RV_PLIC_PRIO38_OFFSET = 10'h b0;
+ parameter logic [9:0] RV_PLIC_PRIO39_OFFSET = 10'h b4;
+ parameter logic [9:0] RV_PLIC_PRIO40_OFFSET = 10'h b8;
+ parameter logic [9:0] RV_PLIC_PRIO41_OFFSET = 10'h bc;
+ parameter logic [9:0] RV_PLIC_PRIO42_OFFSET = 10'h c0;
+ parameter logic [9:0] RV_PLIC_PRIO43_OFFSET = 10'h c4;
+ parameter logic [9:0] RV_PLIC_PRIO44_OFFSET = 10'h c8;
+ parameter logic [9:0] RV_PLIC_PRIO45_OFFSET = 10'h cc;
+ parameter logic [9:0] RV_PLIC_PRIO46_OFFSET = 10'h d0;
+ parameter logic [9:0] RV_PLIC_PRIO47_OFFSET = 10'h d4;
+ parameter logic [9:0] RV_PLIC_PRIO48_OFFSET = 10'h d8;
+ parameter logic [9:0] RV_PLIC_PRIO49_OFFSET = 10'h dc;
+ parameter logic [9:0] RV_PLIC_PRIO50_OFFSET = 10'h e0;
+ parameter logic [9:0] RV_PLIC_PRIO51_OFFSET = 10'h e4;
+ parameter logic [9:0] RV_PLIC_PRIO52_OFFSET = 10'h e8;
+ parameter logic [9:0] RV_PLIC_PRIO53_OFFSET = 10'h ec;
+ parameter logic [9:0] RV_PLIC_PRIO54_OFFSET = 10'h f0;
+ parameter logic [9:0] RV_PLIC_PRIO55_OFFSET = 10'h f4;
+ parameter logic [9:0] RV_PLIC_PRIO56_OFFSET = 10'h f8;
+ parameter logic [9:0] RV_PLIC_PRIO57_OFFSET = 10'h fc;
+ parameter logic [9:0] RV_PLIC_PRIO58_OFFSET = 10'h 100;
+ parameter logic [9:0] RV_PLIC_PRIO59_OFFSET = 10'h 104;
+ parameter logic [9:0] RV_PLIC_PRIO60_OFFSET = 10'h 108;
+ parameter logic [9:0] RV_PLIC_PRIO61_OFFSET = 10'h 10c;
+ parameter logic [9:0] RV_PLIC_PRIO62_OFFSET = 10'h 110;
+ parameter logic [9:0] RV_PLIC_PRIO63_OFFSET = 10'h 114;
+ parameter logic [9:0] RV_PLIC_PRIO64_OFFSET = 10'h 118;
+ parameter logic [9:0] RV_PLIC_PRIO65_OFFSET = 10'h 11c;
+ parameter logic [9:0] RV_PLIC_PRIO66_OFFSET = 10'h 120;
+ parameter logic [9:0] RV_PLIC_PRIO67_OFFSET = 10'h 124;
+ parameter logic [9:0] RV_PLIC_PRIO68_OFFSET = 10'h 128;
+ parameter logic [9:0] RV_PLIC_PRIO69_OFFSET = 10'h 12c;
+ parameter logic [9:0] RV_PLIC_PRIO70_OFFSET = 10'h 130;
+ parameter logic [9:0] RV_PLIC_PRIO71_OFFSET = 10'h 134;
+ parameter logic [9:0] RV_PLIC_PRIO72_OFFSET = 10'h 138;
+ parameter logic [9:0] RV_PLIC_PRIO73_OFFSET = 10'h 13c;
+ parameter logic [9:0] RV_PLIC_PRIO74_OFFSET = 10'h 140;
+ parameter logic [9:0] RV_PLIC_PRIO75_OFFSET = 10'h 144;
+ parameter logic [9:0] RV_PLIC_PRIO76_OFFSET = 10'h 148;
+ parameter logic [9:0] RV_PLIC_PRIO77_OFFSET = 10'h 14c;
+ parameter logic [9:0] RV_PLIC_PRIO78_OFFSET = 10'h 150;
+ parameter logic [9:0] RV_PLIC_IE00_OFFSET = 10'h 200;
+ parameter logic [9:0] RV_PLIC_IE01_OFFSET = 10'h 204;
+ parameter logic [9:0] RV_PLIC_IE02_OFFSET = 10'h 208;
+ parameter logic [9:0] RV_PLIC_THRESHOLD0_OFFSET = 10'h 20c;
+ parameter logic [9:0] RV_PLIC_CC0_OFFSET = 10'h 210;
+ parameter logic [9:0] RV_PLIC_MSIP0_OFFSET = 10'h 214;
// Register Index
typedef enum int {
RV_PLIC_IP0,
RV_PLIC_IP1,
+ RV_PLIC_IP2,
RV_PLIC_LE0,
RV_PLIC_LE1,
+ RV_PLIC_LE2,
RV_PLIC_PRIO0,
RV_PLIC_PRIO1,
RV_PLIC_PRIO2,
@@ -524,87 +625,123 @@
RV_PLIC_PRIO60,
RV_PLIC_PRIO61,
RV_PLIC_PRIO62,
+ RV_PLIC_PRIO63,
+ RV_PLIC_PRIO64,
+ RV_PLIC_PRIO65,
+ RV_PLIC_PRIO66,
+ RV_PLIC_PRIO67,
+ RV_PLIC_PRIO68,
+ RV_PLIC_PRIO69,
+ RV_PLIC_PRIO70,
+ RV_PLIC_PRIO71,
+ RV_PLIC_PRIO72,
+ RV_PLIC_PRIO73,
+ RV_PLIC_PRIO74,
+ RV_PLIC_PRIO75,
+ RV_PLIC_PRIO76,
+ RV_PLIC_PRIO77,
+ RV_PLIC_PRIO78,
RV_PLIC_IE00,
RV_PLIC_IE01,
+ RV_PLIC_IE02,
RV_PLIC_THRESHOLD0,
RV_PLIC_CC0,
RV_PLIC_MSIP0
} rv_plic_id_e;
// Register width information to check illegal writes
- localparam logic [3:0] RV_PLIC_PERMIT [72] = '{
+ parameter logic [3:0] RV_PLIC_PERMIT [91] = '{
4'b 1111, // index[ 0] RV_PLIC_IP0
4'b 1111, // index[ 1] RV_PLIC_IP1
- 4'b 1111, // index[ 2] RV_PLIC_LE0
- 4'b 1111, // index[ 3] RV_PLIC_LE1
- 4'b 0001, // index[ 4] RV_PLIC_PRIO0
- 4'b 0001, // index[ 5] RV_PLIC_PRIO1
- 4'b 0001, // index[ 6] RV_PLIC_PRIO2
- 4'b 0001, // index[ 7] RV_PLIC_PRIO3
- 4'b 0001, // index[ 8] RV_PLIC_PRIO4
- 4'b 0001, // index[ 9] RV_PLIC_PRIO5
- 4'b 0001, // index[10] RV_PLIC_PRIO6
- 4'b 0001, // index[11] RV_PLIC_PRIO7
- 4'b 0001, // index[12] RV_PLIC_PRIO8
- 4'b 0001, // index[13] RV_PLIC_PRIO9
- 4'b 0001, // index[14] RV_PLIC_PRIO10
- 4'b 0001, // index[15] RV_PLIC_PRIO11
- 4'b 0001, // index[16] RV_PLIC_PRIO12
- 4'b 0001, // index[17] RV_PLIC_PRIO13
- 4'b 0001, // index[18] RV_PLIC_PRIO14
- 4'b 0001, // index[19] RV_PLIC_PRIO15
- 4'b 0001, // index[20] RV_PLIC_PRIO16
- 4'b 0001, // index[21] RV_PLIC_PRIO17
- 4'b 0001, // index[22] RV_PLIC_PRIO18
- 4'b 0001, // index[23] RV_PLIC_PRIO19
- 4'b 0001, // index[24] RV_PLIC_PRIO20
- 4'b 0001, // index[25] RV_PLIC_PRIO21
- 4'b 0001, // index[26] RV_PLIC_PRIO22
- 4'b 0001, // index[27] RV_PLIC_PRIO23
- 4'b 0001, // index[28] RV_PLIC_PRIO24
- 4'b 0001, // index[29] RV_PLIC_PRIO25
- 4'b 0001, // index[30] RV_PLIC_PRIO26
- 4'b 0001, // index[31] RV_PLIC_PRIO27
- 4'b 0001, // index[32] RV_PLIC_PRIO28
- 4'b 0001, // index[33] RV_PLIC_PRIO29
- 4'b 0001, // index[34] RV_PLIC_PRIO30
- 4'b 0001, // index[35] RV_PLIC_PRIO31
- 4'b 0001, // index[36] RV_PLIC_PRIO32
- 4'b 0001, // index[37] RV_PLIC_PRIO33
- 4'b 0001, // index[38] RV_PLIC_PRIO34
- 4'b 0001, // index[39] RV_PLIC_PRIO35
- 4'b 0001, // index[40] RV_PLIC_PRIO36
- 4'b 0001, // index[41] RV_PLIC_PRIO37
- 4'b 0001, // index[42] RV_PLIC_PRIO38
- 4'b 0001, // index[43] RV_PLIC_PRIO39
- 4'b 0001, // index[44] RV_PLIC_PRIO40
- 4'b 0001, // index[45] RV_PLIC_PRIO41
- 4'b 0001, // index[46] RV_PLIC_PRIO42
- 4'b 0001, // index[47] RV_PLIC_PRIO43
- 4'b 0001, // index[48] RV_PLIC_PRIO44
- 4'b 0001, // index[49] RV_PLIC_PRIO45
- 4'b 0001, // index[50] RV_PLIC_PRIO46
- 4'b 0001, // index[51] RV_PLIC_PRIO47
- 4'b 0001, // index[52] RV_PLIC_PRIO48
- 4'b 0001, // index[53] RV_PLIC_PRIO49
- 4'b 0001, // index[54] RV_PLIC_PRIO50
- 4'b 0001, // index[55] RV_PLIC_PRIO51
- 4'b 0001, // index[56] RV_PLIC_PRIO52
- 4'b 0001, // index[57] RV_PLIC_PRIO53
- 4'b 0001, // index[58] RV_PLIC_PRIO54
- 4'b 0001, // index[59] RV_PLIC_PRIO55
- 4'b 0001, // index[60] RV_PLIC_PRIO56
- 4'b 0001, // index[61] RV_PLIC_PRIO57
- 4'b 0001, // index[62] RV_PLIC_PRIO58
- 4'b 0001, // index[63] RV_PLIC_PRIO59
- 4'b 0001, // index[64] RV_PLIC_PRIO60
- 4'b 0001, // index[65] RV_PLIC_PRIO61
- 4'b 0001, // index[66] RV_PLIC_PRIO62
- 4'b 1111, // index[67] RV_PLIC_IE00
- 4'b 1111, // index[68] RV_PLIC_IE01
- 4'b 0001, // index[69] RV_PLIC_THRESHOLD0
- 4'b 0001, // index[70] RV_PLIC_CC0
- 4'b 0001 // index[71] RV_PLIC_MSIP0
+ 4'b 0011, // index[ 2] RV_PLIC_IP2
+ 4'b 1111, // index[ 3] RV_PLIC_LE0
+ 4'b 1111, // index[ 4] RV_PLIC_LE1
+ 4'b 0011, // index[ 5] RV_PLIC_LE2
+ 4'b 0001, // index[ 6] RV_PLIC_PRIO0
+ 4'b 0001, // index[ 7] RV_PLIC_PRIO1
+ 4'b 0001, // index[ 8] RV_PLIC_PRIO2
+ 4'b 0001, // index[ 9] RV_PLIC_PRIO3
+ 4'b 0001, // index[10] RV_PLIC_PRIO4
+ 4'b 0001, // index[11] RV_PLIC_PRIO5
+ 4'b 0001, // index[12] RV_PLIC_PRIO6
+ 4'b 0001, // index[13] RV_PLIC_PRIO7
+ 4'b 0001, // index[14] RV_PLIC_PRIO8
+ 4'b 0001, // index[15] RV_PLIC_PRIO9
+ 4'b 0001, // index[16] RV_PLIC_PRIO10
+ 4'b 0001, // index[17] RV_PLIC_PRIO11
+ 4'b 0001, // index[18] RV_PLIC_PRIO12
+ 4'b 0001, // index[19] RV_PLIC_PRIO13
+ 4'b 0001, // index[20] RV_PLIC_PRIO14
+ 4'b 0001, // index[21] RV_PLIC_PRIO15
+ 4'b 0001, // index[22] RV_PLIC_PRIO16
+ 4'b 0001, // index[23] RV_PLIC_PRIO17
+ 4'b 0001, // index[24] RV_PLIC_PRIO18
+ 4'b 0001, // index[25] RV_PLIC_PRIO19
+ 4'b 0001, // index[26] RV_PLIC_PRIO20
+ 4'b 0001, // index[27] RV_PLIC_PRIO21
+ 4'b 0001, // index[28] RV_PLIC_PRIO22
+ 4'b 0001, // index[29] RV_PLIC_PRIO23
+ 4'b 0001, // index[30] RV_PLIC_PRIO24
+ 4'b 0001, // index[31] RV_PLIC_PRIO25
+ 4'b 0001, // index[32] RV_PLIC_PRIO26
+ 4'b 0001, // index[33] RV_PLIC_PRIO27
+ 4'b 0001, // index[34] RV_PLIC_PRIO28
+ 4'b 0001, // index[35] RV_PLIC_PRIO29
+ 4'b 0001, // index[36] RV_PLIC_PRIO30
+ 4'b 0001, // index[37] RV_PLIC_PRIO31
+ 4'b 0001, // index[38] RV_PLIC_PRIO32
+ 4'b 0001, // index[39] RV_PLIC_PRIO33
+ 4'b 0001, // index[40] RV_PLIC_PRIO34
+ 4'b 0001, // index[41] RV_PLIC_PRIO35
+ 4'b 0001, // index[42] RV_PLIC_PRIO36
+ 4'b 0001, // index[43] RV_PLIC_PRIO37
+ 4'b 0001, // index[44] RV_PLIC_PRIO38
+ 4'b 0001, // index[45] RV_PLIC_PRIO39
+ 4'b 0001, // index[46] RV_PLIC_PRIO40
+ 4'b 0001, // index[47] RV_PLIC_PRIO41
+ 4'b 0001, // index[48] RV_PLIC_PRIO42
+ 4'b 0001, // index[49] RV_PLIC_PRIO43
+ 4'b 0001, // index[50] RV_PLIC_PRIO44
+ 4'b 0001, // index[51] RV_PLIC_PRIO45
+ 4'b 0001, // index[52] RV_PLIC_PRIO46
+ 4'b 0001, // index[53] RV_PLIC_PRIO47
+ 4'b 0001, // index[54] RV_PLIC_PRIO48
+ 4'b 0001, // index[55] RV_PLIC_PRIO49
+ 4'b 0001, // index[56] RV_PLIC_PRIO50
+ 4'b 0001, // index[57] RV_PLIC_PRIO51
+ 4'b 0001, // index[58] RV_PLIC_PRIO52
+ 4'b 0001, // index[59] RV_PLIC_PRIO53
+ 4'b 0001, // index[60] RV_PLIC_PRIO54
+ 4'b 0001, // index[61] RV_PLIC_PRIO55
+ 4'b 0001, // index[62] RV_PLIC_PRIO56
+ 4'b 0001, // index[63] RV_PLIC_PRIO57
+ 4'b 0001, // index[64] RV_PLIC_PRIO58
+ 4'b 0001, // index[65] RV_PLIC_PRIO59
+ 4'b 0001, // index[66] RV_PLIC_PRIO60
+ 4'b 0001, // index[67] RV_PLIC_PRIO61
+ 4'b 0001, // index[68] RV_PLIC_PRIO62
+ 4'b 0001, // index[69] RV_PLIC_PRIO63
+ 4'b 0001, // index[70] RV_PLIC_PRIO64
+ 4'b 0001, // index[71] RV_PLIC_PRIO65
+ 4'b 0001, // index[72] RV_PLIC_PRIO66
+ 4'b 0001, // index[73] RV_PLIC_PRIO67
+ 4'b 0001, // index[74] RV_PLIC_PRIO68
+ 4'b 0001, // index[75] RV_PLIC_PRIO69
+ 4'b 0001, // index[76] RV_PLIC_PRIO70
+ 4'b 0001, // index[77] RV_PLIC_PRIO71
+ 4'b 0001, // index[78] RV_PLIC_PRIO72
+ 4'b 0001, // index[79] RV_PLIC_PRIO73
+ 4'b 0001, // index[80] RV_PLIC_PRIO74
+ 4'b 0001, // index[81] RV_PLIC_PRIO75
+ 4'b 0001, // index[82] RV_PLIC_PRIO76
+ 4'b 0001, // index[83] RV_PLIC_PRIO77
+ 4'b 0001, // index[84] RV_PLIC_PRIO78
+ 4'b 1111, // index[85] RV_PLIC_IE00
+ 4'b 1111, // index[86] RV_PLIC_IE01
+ 4'b 0011, // index[87] RV_PLIC_IE02
+ 4'b 0001, // index[88] RV_PLIC_THRESHOLD0
+ 4'b 0001, // index[89] RV_PLIC_CC0
+ 4'b 0001 // index[90] RV_PLIC_MSIP0
};
endpackage
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
index f9138ae..b3659bd 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
@@ -21,9 +21,9 @@
import rv_plic_reg_pkg::* ;
- localparam AW = 10;
- localparam DW = 32;
- localparam DBW = DW/8; // Byte Width
+ localparam int AW = 10;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
// register signals
logic reg_we;
@@ -132,6 +132,22 @@
logic ip1_p60_qs;
logic ip1_p61_qs;
logic ip1_p62_qs;
+ logic ip1_p63_qs;
+ logic ip2_p64_qs;
+ logic ip2_p65_qs;
+ logic ip2_p66_qs;
+ logic ip2_p67_qs;
+ logic ip2_p68_qs;
+ logic ip2_p69_qs;
+ logic ip2_p70_qs;
+ logic ip2_p71_qs;
+ logic ip2_p72_qs;
+ logic ip2_p73_qs;
+ logic ip2_p74_qs;
+ logic ip2_p75_qs;
+ logic ip2_p76_qs;
+ logic ip2_p77_qs;
+ logic ip2_p78_qs;
logic le0_le0_qs;
logic le0_le0_wd;
logic le0_le0_we;
@@ -321,6 +337,54 @@
logic le1_le62_qs;
logic le1_le62_wd;
logic le1_le62_we;
+ logic le1_le63_qs;
+ logic le1_le63_wd;
+ logic le1_le63_we;
+ logic le2_le64_qs;
+ logic le2_le64_wd;
+ logic le2_le64_we;
+ logic le2_le65_qs;
+ logic le2_le65_wd;
+ logic le2_le65_we;
+ logic le2_le66_qs;
+ logic le2_le66_wd;
+ logic le2_le66_we;
+ logic le2_le67_qs;
+ logic le2_le67_wd;
+ logic le2_le67_we;
+ logic le2_le68_qs;
+ logic le2_le68_wd;
+ logic le2_le68_we;
+ logic le2_le69_qs;
+ logic le2_le69_wd;
+ logic le2_le69_we;
+ logic le2_le70_qs;
+ logic le2_le70_wd;
+ logic le2_le70_we;
+ logic le2_le71_qs;
+ logic le2_le71_wd;
+ logic le2_le71_we;
+ logic le2_le72_qs;
+ logic le2_le72_wd;
+ logic le2_le72_we;
+ logic le2_le73_qs;
+ logic le2_le73_wd;
+ logic le2_le73_we;
+ logic le2_le74_qs;
+ logic le2_le74_wd;
+ logic le2_le74_we;
+ logic le2_le75_qs;
+ logic le2_le75_wd;
+ logic le2_le75_we;
+ logic le2_le76_qs;
+ logic le2_le76_wd;
+ logic le2_le76_we;
+ logic le2_le77_qs;
+ logic le2_le77_wd;
+ logic le2_le77_we;
+ logic le2_le78_qs;
+ logic le2_le78_wd;
+ logic le2_le78_we;
logic [1:0] prio0_qs;
logic [1:0] prio0_wd;
logic prio0_we;
@@ -510,6 +574,54 @@
logic [1:0] prio62_qs;
logic [1:0] prio62_wd;
logic prio62_we;
+ logic [1:0] prio63_qs;
+ logic [1:0] prio63_wd;
+ logic prio63_we;
+ logic [1:0] prio64_qs;
+ logic [1:0] prio64_wd;
+ logic prio64_we;
+ logic [1:0] prio65_qs;
+ logic [1:0] prio65_wd;
+ logic prio65_we;
+ logic [1:0] prio66_qs;
+ logic [1:0] prio66_wd;
+ logic prio66_we;
+ logic [1:0] prio67_qs;
+ logic [1:0] prio67_wd;
+ logic prio67_we;
+ logic [1:0] prio68_qs;
+ logic [1:0] prio68_wd;
+ logic prio68_we;
+ logic [1:0] prio69_qs;
+ logic [1:0] prio69_wd;
+ logic prio69_we;
+ logic [1:0] prio70_qs;
+ logic [1:0] prio70_wd;
+ logic prio70_we;
+ logic [1:0] prio71_qs;
+ logic [1:0] prio71_wd;
+ logic prio71_we;
+ logic [1:0] prio72_qs;
+ logic [1:0] prio72_wd;
+ logic prio72_we;
+ logic [1:0] prio73_qs;
+ logic [1:0] prio73_wd;
+ logic prio73_we;
+ logic [1:0] prio74_qs;
+ logic [1:0] prio74_wd;
+ logic prio74_we;
+ logic [1:0] prio75_qs;
+ logic [1:0] prio75_wd;
+ logic prio75_we;
+ logic [1:0] prio76_qs;
+ logic [1:0] prio76_wd;
+ logic prio76_we;
+ logic [1:0] prio77_qs;
+ logic [1:0] prio77_wd;
+ logic prio77_we;
+ logic [1:0] prio78_qs;
+ logic [1:0] prio78_wd;
+ logic prio78_we;
logic ie00_e0_qs;
logic ie00_e0_wd;
logic ie00_e0_we;
@@ -699,11 +811,59 @@
logic ie01_e62_qs;
logic ie01_e62_wd;
logic ie01_e62_we;
+ logic ie01_e63_qs;
+ logic ie01_e63_wd;
+ logic ie01_e63_we;
+ logic ie02_e64_qs;
+ logic ie02_e64_wd;
+ logic ie02_e64_we;
+ logic ie02_e65_qs;
+ logic ie02_e65_wd;
+ logic ie02_e65_we;
+ logic ie02_e66_qs;
+ logic ie02_e66_wd;
+ logic ie02_e66_we;
+ logic ie02_e67_qs;
+ logic ie02_e67_wd;
+ logic ie02_e67_we;
+ logic ie02_e68_qs;
+ logic ie02_e68_wd;
+ logic ie02_e68_we;
+ logic ie02_e69_qs;
+ logic ie02_e69_wd;
+ logic ie02_e69_we;
+ logic ie02_e70_qs;
+ logic ie02_e70_wd;
+ logic ie02_e70_we;
+ logic ie02_e71_qs;
+ logic ie02_e71_wd;
+ logic ie02_e71_we;
+ logic ie02_e72_qs;
+ logic ie02_e72_wd;
+ logic ie02_e72_we;
+ logic ie02_e73_qs;
+ logic ie02_e73_wd;
+ logic ie02_e73_we;
+ logic ie02_e74_qs;
+ logic ie02_e74_wd;
+ logic ie02_e74_we;
+ logic ie02_e75_qs;
+ logic ie02_e75_wd;
+ logic ie02_e75_we;
+ logic ie02_e76_qs;
+ logic ie02_e76_wd;
+ logic ie02_e76_we;
+ logic ie02_e77_qs;
+ logic ie02_e77_wd;
+ logic ie02_e77_we;
+ logic ie02_e78_qs;
+ logic ie02_e78_wd;
+ logic ie02_e78_we;
logic [1:0] threshold0_qs;
logic [1:0] threshold0_wd;
logic threshold0_we;
- logic [5:0] cc0_qs;
- logic [5:0] cc0_wd;
+ logic [6:0] cc0_qs;
+ logic [6:0] cc0_wd;
logic cc0_we;
logic cc0_re;
logic msip0_qs;
@@ -2293,6 +2453,409 @@
);
+ // F[p63]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip1_p63 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[63].de),
+ .d (hw2reg.ip[63].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip1_p63_qs)
+ );
+
+
+ // Subregister 64 of Multireg ip
+ // R[ip2]: V(False)
+
+ // F[p64]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p64 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[64].de),
+ .d (hw2reg.ip[64].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p64_qs)
+ );
+
+
+ // F[p65]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p65 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[65].de),
+ .d (hw2reg.ip[65].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p65_qs)
+ );
+
+
+ // F[p66]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p66 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[66].de),
+ .d (hw2reg.ip[66].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p66_qs)
+ );
+
+
+ // F[p67]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p67 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[67].de),
+ .d (hw2reg.ip[67].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p67_qs)
+ );
+
+
+ // F[p68]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p68 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[68].de),
+ .d (hw2reg.ip[68].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p68_qs)
+ );
+
+
+ // F[p69]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p69 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[69].de),
+ .d (hw2reg.ip[69].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p69_qs)
+ );
+
+
+ // F[p70]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p70 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[70].de),
+ .d (hw2reg.ip[70].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p70_qs)
+ );
+
+
+ // F[p71]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p71 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[71].de),
+ .d (hw2reg.ip[71].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p71_qs)
+ );
+
+
+ // F[p72]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p72 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[72].de),
+ .d (hw2reg.ip[72].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p72_qs)
+ );
+
+
+ // F[p73]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p73 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[73].de),
+ .d (hw2reg.ip[73].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p73_qs)
+ );
+
+
+ // F[p74]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p74 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[74].de),
+ .d (hw2reg.ip[74].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p74_qs)
+ );
+
+
+ // F[p75]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p75 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[75].de),
+ .d (hw2reg.ip[75].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p75_qs)
+ );
+
+
+ // F[p76]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p76 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[76].de),
+ .d (hw2reg.ip[76].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p76_qs)
+ );
+
+
+ // F[p77]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p77 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[77].de),
+ .d (hw2reg.ip[77].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p77_qs)
+ );
+
+
+ // F[p78]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip2_p78 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[78].de),
+ .d (hw2reg.ip[78].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip2_p78_qs)
+ );
+
+
// Subregister 0 of Multireg le
@@ -3939,6 +4502,425 @@
);
+ // F[le63]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le1_le63 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le1_le63_we),
+ .wd (le1_le63_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[63].q ),
+
+ // to register interface (read)
+ .qs (le1_le63_qs)
+ );
+
+
+ // Subregister 64 of Multireg le
+ // R[le2]: V(False)
+
+ // F[le64]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le64 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le64_we),
+ .wd (le2_le64_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[64].q ),
+
+ // to register interface (read)
+ .qs (le2_le64_qs)
+ );
+
+
+ // F[le65]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le65 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le65_we),
+ .wd (le2_le65_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[65].q ),
+
+ // to register interface (read)
+ .qs (le2_le65_qs)
+ );
+
+
+ // F[le66]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le66 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le66_we),
+ .wd (le2_le66_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[66].q ),
+
+ // to register interface (read)
+ .qs (le2_le66_qs)
+ );
+
+
+ // F[le67]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le67 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le67_we),
+ .wd (le2_le67_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[67].q ),
+
+ // to register interface (read)
+ .qs (le2_le67_qs)
+ );
+
+
+ // F[le68]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le68 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le68_we),
+ .wd (le2_le68_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[68].q ),
+
+ // to register interface (read)
+ .qs (le2_le68_qs)
+ );
+
+
+ // F[le69]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le69 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le69_we),
+ .wd (le2_le69_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[69].q ),
+
+ // to register interface (read)
+ .qs (le2_le69_qs)
+ );
+
+
+ // F[le70]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le70 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le70_we),
+ .wd (le2_le70_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[70].q ),
+
+ // to register interface (read)
+ .qs (le2_le70_qs)
+ );
+
+
+ // F[le71]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le71 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le71_we),
+ .wd (le2_le71_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[71].q ),
+
+ // to register interface (read)
+ .qs (le2_le71_qs)
+ );
+
+
+ // F[le72]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le72 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le72_we),
+ .wd (le2_le72_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[72].q ),
+
+ // to register interface (read)
+ .qs (le2_le72_qs)
+ );
+
+
+ // F[le73]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le73 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le73_we),
+ .wd (le2_le73_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[73].q ),
+
+ // to register interface (read)
+ .qs (le2_le73_qs)
+ );
+
+
+ // F[le74]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le74 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le74_we),
+ .wd (le2_le74_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[74].q ),
+
+ // to register interface (read)
+ .qs (le2_le74_qs)
+ );
+
+
+ // F[le75]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le75 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le75_we),
+ .wd (le2_le75_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[75].q ),
+
+ // to register interface (read)
+ .qs (le2_le75_qs)
+ );
+
+
+ // F[le76]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le76 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le76_we),
+ .wd (le2_le76_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[76].q ),
+
+ // to register interface (read)
+ .qs (le2_le76_qs)
+ );
+
+
+ // F[le77]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le77 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le77_we),
+ .wd (le2_le77_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[77].q ),
+
+ // to register interface (read)
+ .qs (le2_le77_qs)
+ );
+
+
+ // F[le78]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le2_le78 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le2_le78_we),
+ .wd (le2_le78_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[78].q ),
+
+ // to register interface (read)
+ .qs (le2_le78_qs)
+ );
+
+
// R[prio0]: V(False)
@@ -5641,6 +6623,438 @@
);
+ // R[prio63]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio63 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio63_we),
+ .wd (prio63_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio63.q ),
+
+ // to register interface (read)
+ .qs (prio63_qs)
+ );
+
+
+ // R[prio64]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio64 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio64_we),
+ .wd (prio64_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio64.q ),
+
+ // to register interface (read)
+ .qs (prio64_qs)
+ );
+
+
+ // R[prio65]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio65 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio65_we),
+ .wd (prio65_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio65.q ),
+
+ // to register interface (read)
+ .qs (prio65_qs)
+ );
+
+
+ // R[prio66]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio66 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio66_we),
+ .wd (prio66_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio66.q ),
+
+ // to register interface (read)
+ .qs (prio66_qs)
+ );
+
+
+ // R[prio67]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio67 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio67_we),
+ .wd (prio67_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio67.q ),
+
+ // to register interface (read)
+ .qs (prio67_qs)
+ );
+
+
+ // R[prio68]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio68 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio68_we),
+ .wd (prio68_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio68.q ),
+
+ // to register interface (read)
+ .qs (prio68_qs)
+ );
+
+
+ // R[prio69]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio69 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio69_we),
+ .wd (prio69_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio69.q ),
+
+ // to register interface (read)
+ .qs (prio69_qs)
+ );
+
+
+ // R[prio70]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio70 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio70_we),
+ .wd (prio70_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio70.q ),
+
+ // to register interface (read)
+ .qs (prio70_qs)
+ );
+
+
+ // R[prio71]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio71 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio71_we),
+ .wd (prio71_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio71.q ),
+
+ // to register interface (read)
+ .qs (prio71_qs)
+ );
+
+
+ // R[prio72]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio72 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio72_we),
+ .wd (prio72_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio72.q ),
+
+ // to register interface (read)
+ .qs (prio72_qs)
+ );
+
+
+ // R[prio73]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio73 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio73_we),
+ .wd (prio73_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio73.q ),
+
+ // to register interface (read)
+ .qs (prio73_qs)
+ );
+
+
+ // R[prio74]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio74 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio74_we),
+ .wd (prio74_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio74.q ),
+
+ // to register interface (read)
+ .qs (prio74_qs)
+ );
+
+
+ // R[prio75]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio75 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio75_we),
+ .wd (prio75_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio75.q ),
+
+ // to register interface (read)
+ .qs (prio75_qs)
+ );
+
+
+ // R[prio76]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio76 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio76_we),
+ .wd (prio76_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio76.q ),
+
+ // to register interface (read)
+ .qs (prio76_qs)
+ );
+
+
+ // R[prio77]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio77 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio77_we),
+ .wd (prio77_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio77.q ),
+
+ // to register interface (read)
+ .qs (prio77_qs)
+ );
+
+
+ // R[prio78]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio78 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio78_we),
+ .wd (prio78_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio78.q ),
+
+ // to register interface (read)
+ .qs (prio78_qs)
+ );
+
+
// Subregister 0 of Multireg ie0
// R[ie00]: V(False)
@@ -7286,6 +8700,425 @@
);
+ // F[e63]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie01_e63 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie01_e63_we),
+ .wd (ie01_e63_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[63].q ),
+
+ // to register interface (read)
+ .qs (ie01_e63_qs)
+ );
+
+
+ // Subregister 64 of Multireg ie0
+ // R[ie02]: V(False)
+
+ // F[e64]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e64 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e64_we),
+ .wd (ie02_e64_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[64].q ),
+
+ // to register interface (read)
+ .qs (ie02_e64_qs)
+ );
+
+
+ // F[e65]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e65 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e65_we),
+ .wd (ie02_e65_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[65].q ),
+
+ // to register interface (read)
+ .qs (ie02_e65_qs)
+ );
+
+
+ // F[e66]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e66 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e66_we),
+ .wd (ie02_e66_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[66].q ),
+
+ // to register interface (read)
+ .qs (ie02_e66_qs)
+ );
+
+
+ // F[e67]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e67 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e67_we),
+ .wd (ie02_e67_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[67].q ),
+
+ // to register interface (read)
+ .qs (ie02_e67_qs)
+ );
+
+
+ // F[e68]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e68 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e68_we),
+ .wd (ie02_e68_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[68].q ),
+
+ // to register interface (read)
+ .qs (ie02_e68_qs)
+ );
+
+
+ // F[e69]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e69 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e69_we),
+ .wd (ie02_e69_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[69].q ),
+
+ // to register interface (read)
+ .qs (ie02_e69_qs)
+ );
+
+
+ // F[e70]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e70 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e70_we),
+ .wd (ie02_e70_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[70].q ),
+
+ // to register interface (read)
+ .qs (ie02_e70_qs)
+ );
+
+
+ // F[e71]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e71 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e71_we),
+ .wd (ie02_e71_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[71].q ),
+
+ // to register interface (read)
+ .qs (ie02_e71_qs)
+ );
+
+
+ // F[e72]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e72 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e72_we),
+ .wd (ie02_e72_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[72].q ),
+
+ // to register interface (read)
+ .qs (ie02_e72_qs)
+ );
+
+
+ // F[e73]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e73 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e73_we),
+ .wd (ie02_e73_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[73].q ),
+
+ // to register interface (read)
+ .qs (ie02_e73_qs)
+ );
+
+
+ // F[e74]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e74 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e74_we),
+ .wd (ie02_e74_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[74].q ),
+
+ // to register interface (read)
+ .qs (ie02_e74_qs)
+ );
+
+
+ // F[e75]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e75 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e75_we),
+ .wd (ie02_e75_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[75].q ),
+
+ // to register interface (read)
+ .qs (ie02_e75_qs)
+ );
+
+
+ // F[e76]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e76 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e76_we),
+ .wd (ie02_e76_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[76].q ),
+
+ // to register interface (read)
+ .qs (ie02_e76_qs)
+ );
+
+
+ // F[e77]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e77 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e77_we),
+ .wd (ie02_e77_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[77].q ),
+
+ // to register interface (read)
+ .qs (ie02_e77_qs)
+ );
+
+
+ // F[e78]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie02_e78 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie02_e78_we),
+ .wd (ie02_e78_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[78].q ),
+
+ // to register interface (read)
+ .qs (ie02_e78_qs)
+ );
+
+
// R[threshold0]: V(False)
@@ -7317,7 +9150,7 @@
// R[cc0]: V(True)
prim_subreg_ext #(
- .DW (6)
+ .DW (7)
) u_cc0 (
.re (cc0_re),
.we (cc0_we),
@@ -7359,81 +9192,100 @@
- logic [71:0] addr_hit;
+ logic [90:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == RV_PLIC_IP0_OFFSET);
addr_hit[ 1] = (reg_addr == RV_PLIC_IP1_OFFSET);
- addr_hit[ 2] = (reg_addr == RV_PLIC_LE0_OFFSET);
- addr_hit[ 3] = (reg_addr == RV_PLIC_LE1_OFFSET);
- addr_hit[ 4] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
- addr_hit[ 5] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
- addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
- addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
- addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
- addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
- addr_hit[10] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
- addr_hit[11] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
- addr_hit[12] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
- addr_hit[13] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
- addr_hit[14] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
- addr_hit[15] = (reg_addr == RV_PLIC_PRIO11_OFFSET);
- addr_hit[16] = (reg_addr == RV_PLIC_PRIO12_OFFSET);
- addr_hit[17] = (reg_addr == RV_PLIC_PRIO13_OFFSET);
- addr_hit[18] = (reg_addr == RV_PLIC_PRIO14_OFFSET);
- addr_hit[19] = (reg_addr == RV_PLIC_PRIO15_OFFSET);
- addr_hit[20] = (reg_addr == RV_PLIC_PRIO16_OFFSET);
- addr_hit[21] = (reg_addr == RV_PLIC_PRIO17_OFFSET);
- addr_hit[22] = (reg_addr == RV_PLIC_PRIO18_OFFSET);
- addr_hit[23] = (reg_addr == RV_PLIC_PRIO19_OFFSET);
- addr_hit[24] = (reg_addr == RV_PLIC_PRIO20_OFFSET);
- addr_hit[25] = (reg_addr == RV_PLIC_PRIO21_OFFSET);
- addr_hit[26] = (reg_addr == RV_PLIC_PRIO22_OFFSET);
- addr_hit[27] = (reg_addr == RV_PLIC_PRIO23_OFFSET);
- addr_hit[28] = (reg_addr == RV_PLIC_PRIO24_OFFSET);
- addr_hit[29] = (reg_addr == RV_PLIC_PRIO25_OFFSET);
- addr_hit[30] = (reg_addr == RV_PLIC_PRIO26_OFFSET);
- addr_hit[31] = (reg_addr == RV_PLIC_PRIO27_OFFSET);
- addr_hit[32] = (reg_addr == RV_PLIC_PRIO28_OFFSET);
- addr_hit[33] = (reg_addr == RV_PLIC_PRIO29_OFFSET);
- addr_hit[34] = (reg_addr == RV_PLIC_PRIO30_OFFSET);
- addr_hit[35] = (reg_addr == RV_PLIC_PRIO31_OFFSET);
- addr_hit[36] = (reg_addr == RV_PLIC_PRIO32_OFFSET);
- addr_hit[37] = (reg_addr == RV_PLIC_PRIO33_OFFSET);
- addr_hit[38] = (reg_addr == RV_PLIC_PRIO34_OFFSET);
- addr_hit[39] = (reg_addr == RV_PLIC_PRIO35_OFFSET);
- addr_hit[40] = (reg_addr == RV_PLIC_PRIO36_OFFSET);
- addr_hit[41] = (reg_addr == RV_PLIC_PRIO37_OFFSET);
- addr_hit[42] = (reg_addr == RV_PLIC_PRIO38_OFFSET);
- addr_hit[43] = (reg_addr == RV_PLIC_PRIO39_OFFSET);
- addr_hit[44] = (reg_addr == RV_PLIC_PRIO40_OFFSET);
- addr_hit[45] = (reg_addr == RV_PLIC_PRIO41_OFFSET);
- addr_hit[46] = (reg_addr == RV_PLIC_PRIO42_OFFSET);
- addr_hit[47] = (reg_addr == RV_PLIC_PRIO43_OFFSET);
- addr_hit[48] = (reg_addr == RV_PLIC_PRIO44_OFFSET);
- addr_hit[49] = (reg_addr == RV_PLIC_PRIO45_OFFSET);
- addr_hit[50] = (reg_addr == RV_PLIC_PRIO46_OFFSET);
- addr_hit[51] = (reg_addr == RV_PLIC_PRIO47_OFFSET);
- addr_hit[52] = (reg_addr == RV_PLIC_PRIO48_OFFSET);
- addr_hit[53] = (reg_addr == RV_PLIC_PRIO49_OFFSET);
- addr_hit[54] = (reg_addr == RV_PLIC_PRIO50_OFFSET);
- addr_hit[55] = (reg_addr == RV_PLIC_PRIO51_OFFSET);
- addr_hit[56] = (reg_addr == RV_PLIC_PRIO52_OFFSET);
- addr_hit[57] = (reg_addr == RV_PLIC_PRIO53_OFFSET);
- addr_hit[58] = (reg_addr == RV_PLIC_PRIO54_OFFSET);
- addr_hit[59] = (reg_addr == RV_PLIC_PRIO55_OFFSET);
- addr_hit[60] = (reg_addr == RV_PLIC_PRIO56_OFFSET);
- addr_hit[61] = (reg_addr == RV_PLIC_PRIO57_OFFSET);
- addr_hit[62] = (reg_addr == RV_PLIC_PRIO58_OFFSET);
- addr_hit[63] = (reg_addr == RV_PLIC_PRIO59_OFFSET);
- addr_hit[64] = (reg_addr == RV_PLIC_PRIO60_OFFSET);
- addr_hit[65] = (reg_addr == RV_PLIC_PRIO61_OFFSET);
- addr_hit[66] = (reg_addr == RV_PLIC_PRIO62_OFFSET);
- addr_hit[67] = (reg_addr == RV_PLIC_IE00_OFFSET);
- addr_hit[68] = (reg_addr == RV_PLIC_IE01_OFFSET);
- addr_hit[69] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
- addr_hit[70] = (reg_addr == RV_PLIC_CC0_OFFSET);
- addr_hit[71] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
+ addr_hit[ 2] = (reg_addr == RV_PLIC_IP2_OFFSET);
+ addr_hit[ 3] = (reg_addr == RV_PLIC_LE0_OFFSET);
+ addr_hit[ 4] = (reg_addr == RV_PLIC_LE1_OFFSET);
+ addr_hit[ 5] = (reg_addr == RV_PLIC_LE2_OFFSET);
+ addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
+ addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
+ addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
+ addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
+ addr_hit[10] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
+ addr_hit[11] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
+ addr_hit[12] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
+ addr_hit[13] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
+ addr_hit[14] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
+ addr_hit[15] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
+ addr_hit[16] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
+ addr_hit[17] = (reg_addr == RV_PLIC_PRIO11_OFFSET);
+ addr_hit[18] = (reg_addr == RV_PLIC_PRIO12_OFFSET);
+ addr_hit[19] = (reg_addr == RV_PLIC_PRIO13_OFFSET);
+ addr_hit[20] = (reg_addr == RV_PLIC_PRIO14_OFFSET);
+ addr_hit[21] = (reg_addr == RV_PLIC_PRIO15_OFFSET);
+ addr_hit[22] = (reg_addr == RV_PLIC_PRIO16_OFFSET);
+ addr_hit[23] = (reg_addr == RV_PLIC_PRIO17_OFFSET);
+ addr_hit[24] = (reg_addr == RV_PLIC_PRIO18_OFFSET);
+ addr_hit[25] = (reg_addr == RV_PLIC_PRIO19_OFFSET);
+ addr_hit[26] = (reg_addr == RV_PLIC_PRIO20_OFFSET);
+ addr_hit[27] = (reg_addr == RV_PLIC_PRIO21_OFFSET);
+ addr_hit[28] = (reg_addr == RV_PLIC_PRIO22_OFFSET);
+ addr_hit[29] = (reg_addr == RV_PLIC_PRIO23_OFFSET);
+ addr_hit[30] = (reg_addr == RV_PLIC_PRIO24_OFFSET);
+ addr_hit[31] = (reg_addr == RV_PLIC_PRIO25_OFFSET);
+ addr_hit[32] = (reg_addr == RV_PLIC_PRIO26_OFFSET);
+ addr_hit[33] = (reg_addr == RV_PLIC_PRIO27_OFFSET);
+ addr_hit[34] = (reg_addr == RV_PLIC_PRIO28_OFFSET);
+ addr_hit[35] = (reg_addr == RV_PLIC_PRIO29_OFFSET);
+ addr_hit[36] = (reg_addr == RV_PLIC_PRIO30_OFFSET);
+ addr_hit[37] = (reg_addr == RV_PLIC_PRIO31_OFFSET);
+ addr_hit[38] = (reg_addr == RV_PLIC_PRIO32_OFFSET);
+ addr_hit[39] = (reg_addr == RV_PLIC_PRIO33_OFFSET);
+ addr_hit[40] = (reg_addr == RV_PLIC_PRIO34_OFFSET);
+ addr_hit[41] = (reg_addr == RV_PLIC_PRIO35_OFFSET);
+ addr_hit[42] = (reg_addr == RV_PLIC_PRIO36_OFFSET);
+ addr_hit[43] = (reg_addr == RV_PLIC_PRIO37_OFFSET);
+ addr_hit[44] = (reg_addr == RV_PLIC_PRIO38_OFFSET);
+ addr_hit[45] = (reg_addr == RV_PLIC_PRIO39_OFFSET);
+ addr_hit[46] = (reg_addr == RV_PLIC_PRIO40_OFFSET);
+ addr_hit[47] = (reg_addr == RV_PLIC_PRIO41_OFFSET);
+ addr_hit[48] = (reg_addr == RV_PLIC_PRIO42_OFFSET);
+ addr_hit[49] = (reg_addr == RV_PLIC_PRIO43_OFFSET);
+ addr_hit[50] = (reg_addr == RV_PLIC_PRIO44_OFFSET);
+ addr_hit[51] = (reg_addr == RV_PLIC_PRIO45_OFFSET);
+ addr_hit[52] = (reg_addr == RV_PLIC_PRIO46_OFFSET);
+ addr_hit[53] = (reg_addr == RV_PLIC_PRIO47_OFFSET);
+ addr_hit[54] = (reg_addr == RV_PLIC_PRIO48_OFFSET);
+ addr_hit[55] = (reg_addr == RV_PLIC_PRIO49_OFFSET);
+ addr_hit[56] = (reg_addr == RV_PLIC_PRIO50_OFFSET);
+ addr_hit[57] = (reg_addr == RV_PLIC_PRIO51_OFFSET);
+ addr_hit[58] = (reg_addr == RV_PLIC_PRIO52_OFFSET);
+ addr_hit[59] = (reg_addr == RV_PLIC_PRIO53_OFFSET);
+ addr_hit[60] = (reg_addr == RV_PLIC_PRIO54_OFFSET);
+ addr_hit[61] = (reg_addr == RV_PLIC_PRIO55_OFFSET);
+ addr_hit[62] = (reg_addr == RV_PLIC_PRIO56_OFFSET);
+ addr_hit[63] = (reg_addr == RV_PLIC_PRIO57_OFFSET);
+ addr_hit[64] = (reg_addr == RV_PLIC_PRIO58_OFFSET);
+ addr_hit[65] = (reg_addr == RV_PLIC_PRIO59_OFFSET);
+ addr_hit[66] = (reg_addr == RV_PLIC_PRIO60_OFFSET);
+ addr_hit[67] = (reg_addr == RV_PLIC_PRIO61_OFFSET);
+ addr_hit[68] = (reg_addr == RV_PLIC_PRIO62_OFFSET);
+ addr_hit[69] = (reg_addr == RV_PLIC_PRIO63_OFFSET);
+ addr_hit[70] = (reg_addr == RV_PLIC_PRIO64_OFFSET);
+ addr_hit[71] = (reg_addr == RV_PLIC_PRIO65_OFFSET);
+ addr_hit[72] = (reg_addr == RV_PLIC_PRIO66_OFFSET);
+ addr_hit[73] = (reg_addr == RV_PLIC_PRIO67_OFFSET);
+ addr_hit[74] = (reg_addr == RV_PLIC_PRIO68_OFFSET);
+ addr_hit[75] = (reg_addr == RV_PLIC_PRIO69_OFFSET);
+ addr_hit[76] = (reg_addr == RV_PLIC_PRIO70_OFFSET);
+ addr_hit[77] = (reg_addr == RV_PLIC_PRIO71_OFFSET);
+ addr_hit[78] = (reg_addr == RV_PLIC_PRIO72_OFFSET);
+ addr_hit[79] = (reg_addr == RV_PLIC_PRIO73_OFFSET);
+ addr_hit[80] = (reg_addr == RV_PLIC_PRIO74_OFFSET);
+ addr_hit[81] = (reg_addr == RV_PLIC_PRIO75_OFFSET);
+ addr_hit[82] = (reg_addr == RV_PLIC_PRIO76_OFFSET);
+ addr_hit[83] = (reg_addr == RV_PLIC_PRIO77_OFFSET);
+ addr_hit[84] = (reg_addr == RV_PLIC_PRIO78_OFFSET);
+ addr_hit[85] = (reg_addr == RV_PLIC_IE00_OFFSET);
+ addr_hit[86] = (reg_addr == RV_PLIC_IE01_OFFSET);
+ addr_hit[87] = (reg_addr == RV_PLIC_IE02_OFFSET);
+ addr_hit[88] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
+ addr_hit[89] = (reg_addr == RV_PLIC_CC0_OFFSET);
+ addr_hit[90] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -7513,6 +9365,25 @@
if (addr_hit[69] && reg_we && (RV_PLIC_PERMIT[69] != (RV_PLIC_PERMIT[69] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[70] && reg_we && (RV_PLIC_PERMIT[70] != (RV_PLIC_PERMIT[70] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[71] && reg_we && (RV_PLIC_PERMIT[71] != (RV_PLIC_PERMIT[71] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[72] && reg_we && (RV_PLIC_PERMIT[72] != (RV_PLIC_PERMIT[72] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[73] && reg_we && (RV_PLIC_PERMIT[73] != (RV_PLIC_PERMIT[73] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[74] && reg_we && (RV_PLIC_PERMIT[74] != (RV_PLIC_PERMIT[74] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[75] && reg_we && (RV_PLIC_PERMIT[75] != (RV_PLIC_PERMIT[75] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[76] && reg_we && (RV_PLIC_PERMIT[76] != (RV_PLIC_PERMIT[76] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[77] && reg_we && (RV_PLIC_PERMIT[77] != (RV_PLIC_PERMIT[77] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[78] && reg_we && (RV_PLIC_PERMIT[78] != (RV_PLIC_PERMIT[78] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[79] && reg_we && (RV_PLIC_PERMIT[79] != (RV_PLIC_PERMIT[79] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[80] && reg_we && (RV_PLIC_PERMIT[80] != (RV_PLIC_PERMIT[80] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[81] && reg_we && (RV_PLIC_PERMIT[81] != (RV_PLIC_PERMIT[81] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[82] && reg_we && (RV_PLIC_PERMIT[82] != (RV_PLIC_PERMIT[82] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[83] && reg_we && (RV_PLIC_PERMIT[83] != (RV_PLIC_PERMIT[83] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[84] && reg_we && (RV_PLIC_PERMIT[84] != (RV_PLIC_PERMIT[84] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[85] && reg_we && (RV_PLIC_PERMIT[85] != (RV_PLIC_PERMIT[85] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[86] && reg_we && (RV_PLIC_PERMIT[86] != (RV_PLIC_PERMIT[86] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[87] && reg_we && (RV_PLIC_PERMIT[87] != (RV_PLIC_PERMIT[87] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[88] && reg_we && (RV_PLIC_PERMIT[88] != (RV_PLIC_PERMIT[88] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[89] && reg_we && (RV_PLIC_PERMIT[89] != (RV_PLIC_PERMIT[89] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[90] && reg_we && (RV_PLIC_PERMIT[90] != (RV_PLIC_PERMIT[90] & reg_be))) wr_err = 1'b1 ;
end
@@ -7578,581 +9449,741 @@
- assign le0_le0_we = addr_hit[2] & reg_we & ~wr_err;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ assign le0_le0_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le0_wd = reg_wdata[0];
- assign le0_le1_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le1_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le1_wd = reg_wdata[1];
- assign le0_le2_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le2_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le2_wd = reg_wdata[2];
- assign le0_le3_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le3_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le3_wd = reg_wdata[3];
- assign le0_le4_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le4_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le4_wd = reg_wdata[4];
- assign le0_le5_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le5_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le5_wd = reg_wdata[5];
- assign le0_le6_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le6_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le6_wd = reg_wdata[6];
- assign le0_le7_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le7_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le7_wd = reg_wdata[7];
- assign le0_le8_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le8_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le8_wd = reg_wdata[8];
- assign le0_le9_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le9_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le9_wd = reg_wdata[9];
- assign le0_le10_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le10_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le10_wd = reg_wdata[10];
- assign le0_le11_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le11_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le11_wd = reg_wdata[11];
- assign le0_le12_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le12_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le12_wd = reg_wdata[12];
- assign le0_le13_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le13_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le13_wd = reg_wdata[13];
- assign le0_le14_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le14_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le14_wd = reg_wdata[14];
- assign le0_le15_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le15_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le15_wd = reg_wdata[15];
- assign le0_le16_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le16_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le16_wd = reg_wdata[16];
- assign le0_le17_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le17_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le17_wd = reg_wdata[17];
- assign le0_le18_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le18_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le18_wd = reg_wdata[18];
- assign le0_le19_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le19_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le19_wd = reg_wdata[19];
- assign le0_le20_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le20_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le20_wd = reg_wdata[20];
- assign le0_le21_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le21_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le21_wd = reg_wdata[21];
- assign le0_le22_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le22_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le22_wd = reg_wdata[22];
- assign le0_le23_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le23_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le23_wd = reg_wdata[23];
- assign le0_le24_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le24_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le24_wd = reg_wdata[24];
- assign le0_le25_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le25_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le25_wd = reg_wdata[25];
- assign le0_le26_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le26_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le26_wd = reg_wdata[26];
- assign le0_le27_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le27_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le27_wd = reg_wdata[27];
- assign le0_le28_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le28_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le28_wd = reg_wdata[28];
- assign le0_le29_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le29_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le29_wd = reg_wdata[29];
- assign le0_le30_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le30_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le30_wd = reg_wdata[30];
- assign le0_le31_we = addr_hit[2] & reg_we & ~wr_err;
+ assign le0_le31_we = addr_hit[3] & reg_we & ~wr_err;
assign le0_le31_wd = reg_wdata[31];
- assign le1_le32_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le32_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le32_wd = reg_wdata[0];
- assign le1_le33_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le33_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le33_wd = reg_wdata[1];
- assign le1_le34_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le34_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le34_wd = reg_wdata[2];
- assign le1_le35_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le35_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le35_wd = reg_wdata[3];
- assign le1_le36_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le36_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le36_wd = reg_wdata[4];
- assign le1_le37_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le37_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le37_wd = reg_wdata[5];
- assign le1_le38_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le38_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le38_wd = reg_wdata[6];
- assign le1_le39_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le39_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le39_wd = reg_wdata[7];
- assign le1_le40_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le40_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le40_wd = reg_wdata[8];
- assign le1_le41_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le41_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le41_wd = reg_wdata[9];
- assign le1_le42_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le42_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le42_wd = reg_wdata[10];
- assign le1_le43_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le43_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le43_wd = reg_wdata[11];
- assign le1_le44_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le44_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le44_wd = reg_wdata[12];
- assign le1_le45_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le45_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le45_wd = reg_wdata[13];
- assign le1_le46_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le46_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le46_wd = reg_wdata[14];
- assign le1_le47_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le47_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le47_wd = reg_wdata[15];
- assign le1_le48_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le48_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le48_wd = reg_wdata[16];
- assign le1_le49_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le49_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le49_wd = reg_wdata[17];
- assign le1_le50_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le50_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le50_wd = reg_wdata[18];
- assign le1_le51_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le51_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le51_wd = reg_wdata[19];
- assign le1_le52_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le52_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le52_wd = reg_wdata[20];
- assign le1_le53_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le53_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le53_wd = reg_wdata[21];
- assign le1_le54_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le54_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le54_wd = reg_wdata[22];
- assign le1_le55_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le55_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le55_wd = reg_wdata[23];
- assign le1_le56_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le56_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le56_wd = reg_wdata[24];
- assign le1_le57_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le57_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le57_wd = reg_wdata[25];
- assign le1_le58_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le58_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le58_wd = reg_wdata[26];
- assign le1_le59_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le59_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le59_wd = reg_wdata[27];
- assign le1_le60_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le60_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le60_wd = reg_wdata[28];
- assign le1_le61_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le61_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le61_wd = reg_wdata[29];
- assign le1_le62_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le1_le62_we = addr_hit[4] & reg_we & ~wr_err;
assign le1_le62_wd = reg_wdata[30];
- assign prio0_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le1_le63_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le1_le63_wd = reg_wdata[31];
+
+ assign le2_le64_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le64_wd = reg_wdata[0];
+
+ assign le2_le65_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le65_wd = reg_wdata[1];
+
+ assign le2_le66_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le66_wd = reg_wdata[2];
+
+ assign le2_le67_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le67_wd = reg_wdata[3];
+
+ assign le2_le68_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le68_wd = reg_wdata[4];
+
+ assign le2_le69_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le69_wd = reg_wdata[5];
+
+ assign le2_le70_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le70_wd = reg_wdata[6];
+
+ assign le2_le71_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le71_wd = reg_wdata[7];
+
+ assign le2_le72_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le72_wd = reg_wdata[8];
+
+ assign le2_le73_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le73_wd = reg_wdata[9];
+
+ assign le2_le74_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le74_wd = reg_wdata[10];
+
+ assign le2_le75_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le75_wd = reg_wdata[11];
+
+ assign le2_le76_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le76_wd = reg_wdata[12];
+
+ assign le2_le77_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le77_wd = reg_wdata[13];
+
+ assign le2_le78_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le2_le78_wd = reg_wdata[14];
+
+ assign prio0_we = addr_hit[6] & reg_we & ~wr_err;
assign prio0_wd = reg_wdata[1:0];
- assign prio1_we = addr_hit[5] & reg_we & ~wr_err;
+ assign prio1_we = addr_hit[7] & reg_we & ~wr_err;
assign prio1_wd = reg_wdata[1:0];
- assign prio2_we = addr_hit[6] & reg_we & ~wr_err;
+ assign prio2_we = addr_hit[8] & reg_we & ~wr_err;
assign prio2_wd = reg_wdata[1:0];
- assign prio3_we = addr_hit[7] & reg_we & ~wr_err;
+ assign prio3_we = addr_hit[9] & reg_we & ~wr_err;
assign prio3_wd = reg_wdata[1:0];
- assign prio4_we = addr_hit[8] & reg_we & ~wr_err;
+ assign prio4_we = addr_hit[10] & reg_we & ~wr_err;
assign prio4_wd = reg_wdata[1:0];
- assign prio5_we = addr_hit[9] & reg_we & ~wr_err;
+ assign prio5_we = addr_hit[11] & reg_we & ~wr_err;
assign prio5_wd = reg_wdata[1:0];
- assign prio6_we = addr_hit[10] & reg_we & ~wr_err;
+ assign prio6_we = addr_hit[12] & reg_we & ~wr_err;
assign prio6_wd = reg_wdata[1:0];
- assign prio7_we = addr_hit[11] & reg_we & ~wr_err;
+ assign prio7_we = addr_hit[13] & reg_we & ~wr_err;
assign prio7_wd = reg_wdata[1:0];
- assign prio8_we = addr_hit[12] & reg_we & ~wr_err;
+ assign prio8_we = addr_hit[14] & reg_we & ~wr_err;
assign prio8_wd = reg_wdata[1:0];
- assign prio9_we = addr_hit[13] & reg_we & ~wr_err;
+ assign prio9_we = addr_hit[15] & reg_we & ~wr_err;
assign prio9_wd = reg_wdata[1:0];
- assign prio10_we = addr_hit[14] & reg_we & ~wr_err;
+ assign prio10_we = addr_hit[16] & reg_we & ~wr_err;
assign prio10_wd = reg_wdata[1:0];
- assign prio11_we = addr_hit[15] & reg_we & ~wr_err;
+ assign prio11_we = addr_hit[17] & reg_we & ~wr_err;
assign prio11_wd = reg_wdata[1:0];
- assign prio12_we = addr_hit[16] & reg_we & ~wr_err;
+ assign prio12_we = addr_hit[18] & reg_we & ~wr_err;
assign prio12_wd = reg_wdata[1:0];
- assign prio13_we = addr_hit[17] & reg_we & ~wr_err;
+ assign prio13_we = addr_hit[19] & reg_we & ~wr_err;
assign prio13_wd = reg_wdata[1:0];
- assign prio14_we = addr_hit[18] & reg_we & ~wr_err;
+ assign prio14_we = addr_hit[20] & reg_we & ~wr_err;
assign prio14_wd = reg_wdata[1:0];
- assign prio15_we = addr_hit[19] & reg_we & ~wr_err;
+ assign prio15_we = addr_hit[21] & reg_we & ~wr_err;
assign prio15_wd = reg_wdata[1:0];
- assign prio16_we = addr_hit[20] & reg_we & ~wr_err;
+ assign prio16_we = addr_hit[22] & reg_we & ~wr_err;
assign prio16_wd = reg_wdata[1:0];
- assign prio17_we = addr_hit[21] & reg_we & ~wr_err;
+ assign prio17_we = addr_hit[23] & reg_we & ~wr_err;
assign prio17_wd = reg_wdata[1:0];
- assign prio18_we = addr_hit[22] & reg_we & ~wr_err;
+ assign prio18_we = addr_hit[24] & reg_we & ~wr_err;
assign prio18_wd = reg_wdata[1:0];
- assign prio19_we = addr_hit[23] & reg_we & ~wr_err;
+ assign prio19_we = addr_hit[25] & reg_we & ~wr_err;
assign prio19_wd = reg_wdata[1:0];
- assign prio20_we = addr_hit[24] & reg_we & ~wr_err;
+ assign prio20_we = addr_hit[26] & reg_we & ~wr_err;
assign prio20_wd = reg_wdata[1:0];
- assign prio21_we = addr_hit[25] & reg_we & ~wr_err;
+ assign prio21_we = addr_hit[27] & reg_we & ~wr_err;
assign prio21_wd = reg_wdata[1:0];
- assign prio22_we = addr_hit[26] & reg_we & ~wr_err;
+ assign prio22_we = addr_hit[28] & reg_we & ~wr_err;
assign prio22_wd = reg_wdata[1:0];
- assign prio23_we = addr_hit[27] & reg_we & ~wr_err;
+ assign prio23_we = addr_hit[29] & reg_we & ~wr_err;
assign prio23_wd = reg_wdata[1:0];
- assign prio24_we = addr_hit[28] & reg_we & ~wr_err;
+ assign prio24_we = addr_hit[30] & reg_we & ~wr_err;
assign prio24_wd = reg_wdata[1:0];
- assign prio25_we = addr_hit[29] & reg_we & ~wr_err;
+ assign prio25_we = addr_hit[31] & reg_we & ~wr_err;
assign prio25_wd = reg_wdata[1:0];
- assign prio26_we = addr_hit[30] & reg_we & ~wr_err;
+ assign prio26_we = addr_hit[32] & reg_we & ~wr_err;
assign prio26_wd = reg_wdata[1:0];
- assign prio27_we = addr_hit[31] & reg_we & ~wr_err;
+ assign prio27_we = addr_hit[33] & reg_we & ~wr_err;
assign prio27_wd = reg_wdata[1:0];
- assign prio28_we = addr_hit[32] & reg_we & ~wr_err;
+ assign prio28_we = addr_hit[34] & reg_we & ~wr_err;
assign prio28_wd = reg_wdata[1:0];
- assign prio29_we = addr_hit[33] & reg_we & ~wr_err;
+ assign prio29_we = addr_hit[35] & reg_we & ~wr_err;
assign prio29_wd = reg_wdata[1:0];
- assign prio30_we = addr_hit[34] & reg_we & ~wr_err;
+ assign prio30_we = addr_hit[36] & reg_we & ~wr_err;
assign prio30_wd = reg_wdata[1:0];
- assign prio31_we = addr_hit[35] & reg_we & ~wr_err;
+ assign prio31_we = addr_hit[37] & reg_we & ~wr_err;
assign prio31_wd = reg_wdata[1:0];
- assign prio32_we = addr_hit[36] & reg_we & ~wr_err;
+ assign prio32_we = addr_hit[38] & reg_we & ~wr_err;
assign prio32_wd = reg_wdata[1:0];
- assign prio33_we = addr_hit[37] & reg_we & ~wr_err;
+ assign prio33_we = addr_hit[39] & reg_we & ~wr_err;
assign prio33_wd = reg_wdata[1:0];
- assign prio34_we = addr_hit[38] & reg_we & ~wr_err;
+ assign prio34_we = addr_hit[40] & reg_we & ~wr_err;
assign prio34_wd = reg_wdata[1:0];
- assign prio35_we = addr_hit[39] & reg_we & ~wr_err;
+ assign prio35_we = addr_hit[41] & reg_we & ~wr_err;
assign prio35_wd = reg_wdata[1:0];
- assign prio36_we = addr_hit[40] & reg_we & ~wr_err;
+ assign prio36_we = addr_hit[42] & reg_we & ~wr_err;
assign prio36_wd = reg_wdata[1:0];
- assign prio37_we = addr_hit[41] & reg_we & ~wr_err;
+ assign prio37_we = addr_hit[43] & reg_we & ~wr_err;
assign prio37_wd = reg_wdata[1:0];
- assign prio38_we = addr_hit[42] & reg_we & ~wr_err;
+ assign prio38_we = addr_hit[44] & reg_we & ~wr_err;
assign prio38_wd = reg_wdata[1:0];
- assign prio39_we = addr_hit[43] & reg_we & ~wr_err;
+ assign prio39_we = addr_hit[45] & reg_we & ~wr_err;
assign prio39_wd = reg_wdata[1:0];
- assign prio40_we = addr_hit[44] & reg_we & ~wr_err;
+ assign prio40_we = addr_hit[46] & reg_we & ~wr_err;
assign prio40_wd = reg_wdata[1:0];
- assign prio41_we = addr_hit[45] & reg_we & ~wr_err;
+ assign prio41_we = addr_hit[47] & reg_we & ~wr_err;
assign prio41_wd = reg_wdata[1:0];
- assign prio42_we = addr_hit[46] & reg_we & ~wr_err;
+ assign prio42_we = addr_hit[48] & reg_we & ~wr_err;
assign prio42_wd = reg_wdata[1:0];
- assign prio43_we = addr_hit[47] & reg_we & ~wr_err;
+ assign prio43_we = addr_hit[49] & reg_we & ~wr_err;
assign prio43_wd = reg_wdata[1:0];
- assign prio44_we = addr_hit[48] & reg_we & ~wr_err;
+ assign prio44_we = addr_hit[50] & reg_we & ~wr_err;
assign prio44_wd = reg_wdata[1:0];
- assign prio45_we = addr_hit[49] & reg_we & ~wr_err;
+ assign prio45_we = addr_hit[51] & reg_we & ~wr_err;
assign prio45_wd = reg_wdata[1:0];
- assign prio46_we = addr_hit[50] & reg_we & ~wr_err;
+ assign prio46_we = addr_hit[52] & reg_we & ~wr_err;
assign prio46_wd = reg_wdata[1:0];
- assign prio47_we = addr_hit[51] & reg_we & ~wr_err;
+ assign prio47_we = addr_hit[53] & reg_we & ~wr_err;
assign prio47_wd = reg_wdata[1:0];
- assign prio48_we = addr_hit[52] & reg_we & ~wr_err;
+ assign prio48_we = addr_hit[54] & reg_we & ~wr_err;
assign prio48_wd = reg_wdata[1:0];
- assign prio49_we = addr_hit[53] & reg_we & ~wr_err;
+ assign prio49_we = addr_hit[55] & reg_we & ~wr_err;
assign prio49_wd = reg_wdata[1:0];
- assign prio50_we = addr_hit[54] & reg_we & ~wr_err;
+ assign prio50_we = addr_hit[56] & reg_we & ~wr_err;
assign prio50_wd = reg_wdata[1:0];
- assign prio51_we = addr_hit[55] & reg_we & ~wr_err;
+ assign prio51_we = addr_hit[57] & reg_we & ~wr_err;
assign prio51_wd = reg_wdata[1:0];
- assign prio52_we = addr_hit[56] & reg_we & ~wr_err;
+ assign prio52_we = addr_hit[58] & reg_we & ~wr_err;
assign prio52_wd = reg_wdata[1:0];
- assign prio53_we = addr_hit[57] & reg_we & ~wr_err;
+ assign prio53_we = addr_hit[59] & reg_we & ~wr_err;
assign prio53_wd = reg_wdata[1:0];
- assign prio54_we = addr_hit[58] & reg_we & ~wr_err;
+ assign prio54_we = addr_hit[60] & reg_we & ~wr_err;
assign prio54_wd = reg_wdata[1:0];
- assign prio55_we = addr_hit[59] & reg_we & ~wr_err;
+ assign prio55_we = addr_hit[61] & reg_we & ~wr_err;
assign prio55_wd = reg_wdata[1:0];
- assign prio56_we = addr_hit[60] & reg_we & ~wr_err;
+ assign prio56_we = addr_hit[62] & reg_we & ~wr_err;
assign prio56_wd = reg_wdata[1:0];
- assign prio57_we = addr_hit[61] & reg_we & ~wr_err;
+ assign prio57_we = addr_hit[63] & reg_we & ~wr_err;
assign prio57_wd = reg_wdata[1:0];
- assign prio58_we = addr_hit[62] & reg_we & ~wr_err;
+ assign prio58_we = addr_hit[64] & reg_we & ~wr_err;
assign prio58_wd = reg_wdata[1:0];
- assign prio59_we = addr_hit[63] & reg_we & ~wr_err;
+ assign prio59_we = addr_hit[65] & reg_we & ~wr_err;
assign prio59_wd = reg_wdata[1:0];
- assign prio60_we = addr_hit[64] & reg_we & ~wr_err;
+ assign prio60_we = addr_hit[66] & reg_we & ~wr_err;
assign prio60_wd = reg_wdata[1:0];
- assign prio61_we = addr_hit[65] & reg_we & ~wr_err;
+ assign prio61_we = addr_hit[67] & reg_we & ~wr_err;
assign prio61_wd = reg_wdata[1:0];
- assign prio62_we = addr_hit[66] & reg_we & ~wr_err;
+ assign prio62_we = addr_hit[68] & reg_we & ~wr_err;
assign prio62_wd = reg_wdata[1:0];
- assign ie00_e0_we = addr_hit[67] & reg_we & ~wr_err;
+ assign prio63_we = addr_hit[69] & reg_we & ~wr_err;
+ assign prio63_wd = reg_wdata[1:0];
+
+ assign prio64_we = addr_hit[70] & reg_we & ~wr_err;
+ assign prio64_wd = reg_wdata[1:0];
+
+ assign prio65_we = addr_hit[71] & reg_we & ~wr_err;
+ assign prio65_wd = reg_wdata[1:0];
+
+ assign prio66_we = addr_hit[72] & reg_we & ~wr_err;
+ assign prio66_wd = reg_wdata[1:0];
+
+ assign prio67_we = addr_hit[73] & reg_we & ~wr_err;
+ assign prio67_wd = reg_wdata[1:0];
+
+ assign prio68_we = addr_hit[74] & reg_we & ~wr_err;
+ assign prio68_wd = reg_wdata[1:0];
+
+ assign prio69_we = addr_hit[75] & reg_we & ~wr_err;
+ assign prio69_wd = reg_wdata[1:0];
+
+ assign prio70_we = addr_hit[76] & reg_we & ~wr_err;
+ assign prio70_wd = reg_wdata[1:0];
+
+ assign prio71_we = addr_hit[77] & reg_we & ~wr_err;
+ assign prio71_wd = reg_wdata[1:0];
+
+ assign prio72_we = addr_hit[78] & reg_we & ~wr_err;
+ assign prio72_wd = reg_wdata[1:0];
+
+ assign prio73_we = addr_hit[79] & reg_we & ~wr_err;
+ assign prio73_wd = reg_wdata[1:0];
+
+ assign prio74_we = addr_hit[80] & reg_we & ~wr_err;
+ assign prio74_wd = reg_wdata[1:0];
+
+ assign prio75_we = addr_hit[81] & reg_we & ~wr_err;
+ assign prio75_wd = reg_wdata[1:0];
+
+ assign prio76_we = addr_hit[82] & reg_we & ~wr_err;
+ assign prio76_wd = reg_wdata[1:0];
+
+ assign prio77_we = addr_hit[83] & reg_we & ~wr_err;
+ assign prio77_wd = reg_wdata[1:0];
+
+ assign prio78_we = addr_hit[84] & reg_we & ~wr_err;
+ assign prio78_wd = reg_wdata[1:0];
+
+ assign ie00_e0_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e0_wd = reg_wdata[0];
- assign ie00_e1_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e1_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e1_wd = reg_wdata[1];
- assign ie00_e2_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e2_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e2_wd = reg_wdata[2];
- assign ie00_e3_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e3_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e3_wd = reg_wdata[3];
- assign ie00_e4_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e4_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e4_wd = reg_wdata[4];
- assign ie00_e5_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e5_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e5_wd = reg_wdata[5];
- assign ie00_e6_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e6_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e6_wd = reg_wdata[6];
- assign ie00_e7_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e7_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e7_wd = reg_wdata[7];
- assign ie00_e8_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e8_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e8_wd = reg_wdata[8];
- assign ie00_e9_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e9_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e9_wd = reg_wdata[9];
- assign ie00_e10_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e10_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e10_wd = reg_wdata[10];
- assign ie00_e11_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e11_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e11_wd = reg_wdata[11];
- assign ie00_e12_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e12_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e12_wd = reg_wdata[12];
- assign ie00_e13_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e13_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e13_wd = reg_wdata[13];
- assign ie00_e14_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e14_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e14_wd = reg_wdata[14];
- assign ie00_e15_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e15_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e15_wd = reg_wdata[15];
- assign ie00_e16_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e16_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e16_wd = reg_wdata[16];
- assign ie00_e17_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e17_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e17_wd = reg_wdata[17];
- assign ie00_e18_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e18_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e18_wd = reg_wdata[18];
- assign ie00_e19_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e19_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e19_wd = reg_wdata[19];
- assign ie00_e20_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e20_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e20_wd = reg_wdata[20];
- assign ie00_e21_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e21_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e21_wd = reg_wdata[21];
- assign ie00_e22_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e22_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e22_wd = reg_wdata[22];
- assign ie00_e23_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e23_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e23_wd = reg_wdata[23];
- assign ie00_e24_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e24_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e24_wd = reg_wdata[24];
- assign ie00_e25_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e25_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e25_wd = reg_wdata[25];
- assign ie00_e26_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e26_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e26_wd = reg_wdata[26];
- assign ie00_e27_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e27_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e27_wd = reg_wdata[27];
- assign ie00_e28_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e28_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e28_wd = reg_wdata[28];
- assign ie00_e29_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e29_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e29_wd = reg_wdata[29];
- assign ie00_e30_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e30_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e30_wd = reg_wdata[30];
- assign ie00_e31_we = addr_hit[67] & reg_we & ~wr_err;
+ assign ie00_e31_we = addr_hit[85] & reg_we & ~wr_err;
assign ie00_e31_wd = reg_wdata[31];
- assign ie01_e32_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e32_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e32_wd = reg_wdata[0];
- assign ie01_e33_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e33_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e33_wd = reg_wdata[1];
- assign ie01_e34_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e34_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e34_wd = reg_wdata[2];
- assign ie01_e35_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e35_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e35_wd = reg_wdata[3];
- assign ie01_e36_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e36_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e36_wd = reg_wdata[4];
- assign ie01_e37_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e37_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e37_wd = reg_wdata[5];
- assign ie01_e38_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e38_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e38_wd = reg_wdata[6];
- assign ie01_e39_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e39_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e39_wd = reg_wdata[7];
- assign ie01_e40_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e40_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e40_wd = reg_wdata[8];
- assign ie01_e41_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e41_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e41_wd = reg_wdata[9];
- assign ie01_e42_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e42_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e42_wd = reg_wdata[10];
- assign ie01_e43_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e43_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e43_wd = reg_wdata[11];
- assign ie01_e44_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e44_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e44_wd = reg_wdata[12];
- assign ie01_e45_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e45_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e45_wd = reg_wdata[13];
- assign ie01_e46_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e46_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e46_wd = reg_wdata[14];
- assign ie01_e47_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e47_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e47_wd = reg_wdata[15];
- assign ie01_e48_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e48_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e48_wd = reg_wdata[16];
- assign ie01_e49_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e49_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e49_wd = reg_wdata[17];
- assign ie01_e50_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e50_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e50_wd = reg_wdata[18];
- assign ie01_e51_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e51_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e51_wd = reg_wdata[19];
- assign ie01_e52_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e52_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e52_wd = reg_wdata[20];
- assign ie01_e53_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e53_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e53_wd = reg_wdata[21];
- assign ie01_e54_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e54_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e54_wd = reg_wdata[22];
- assign ie01_e55_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e55_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e55_wd = reg_wdata[23];
- assign ie01_e56_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e56_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e56_wd = reg_wdata[24];
- assign ie01_e57_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e57_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e57_wd = reg_wdata[25];
- assign ie01_e58_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e58_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e58_wd = reg_wdata[26];
- assign ie01_e59_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e59_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e59_wd = reg_wdata[27];
- assign ie01_e60_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e60_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e60_wd = reg_wdata[28];
- assign ie01_e61_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e61_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e61_wd = reg_wdata[29];
- assign ie01_e62_we = addr_hit[68] & reg_we & ~wr_err;
+ assign ie01_e62_we = addr_hit[86] & reg_we & ~wr_err;
assign ie01_e62_wd = reg_wdata[30];
- assign threshold0_we = addr_hit[69] & reg_we & ~wr_err;
+ assign ie01_e63_we = addr_hit[86] & reg_we & ~wr_err;
+ assign ie01_e63_wd = reg_wdata[31];
+
+ assign ie02_e64_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e64_wd = reg_wdata[0];
+
+ assign ie02_e65_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e65_wd = reg_wdata[1];
+
+ assign ie02_e66_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e66_wd = reg_wdata[2];
+
+ assign ie02_e67_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e67_wd = reg_wdata[3];
+
+ assign ie02_e68_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e68_wd = reg_wdata[4];
+
+ assign ie02_e69_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e69_wd = reg_wdata[5];
+
+ assign ie02_e70_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e70_wd = reg_wdata[6];
+
+ assign ie02_e71_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e71_wd = reg_wdata[7];
+
+ assign ie02_e72_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e72_wd = reg_wdata[8];
+
+ assign ie02_e73_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e73_wd = reg_wdata[9];
+
+ assign ie02_e74_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e74_wd = reg_wdata[10];
+
+ assign ie02_e75_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e75_wd = reg_wdata[11];
+
+ assign ie02_e76_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e76_wd = reg_wdata[12];
+
+ assign ie02_e77_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e77_wd = reg_wdata[13];
+
+ assign ie02_e78_we = addr_hit[87] & reg_we & ~wr_err;
+ assign ie02_e78_wd = reg_wdata[14];
+
+ assign threshold0_we = addr_hit[88] & reg_we & ~wr_err;
assign threshold0_wd = reg_wdata[1:0];
- assign cc0_we = addr_hit[70] & reg_we & ~wr_err;
- assign cc0_wd = reg_wdata[5:0];
- assign cc0_re = addr_hit[70] && reg_re;
+ assign cc0_we = addr_hit[89] & reg_we & ~wr_err;
+ assign cc0_wd = reg_wdata[6:0];
+ assign cc0_re = addr_hit[89] && reg_re;
- assign msip0_we = addr_hit[71] & reg_we & ~wr_err;
+ assign msip0_we = addr_hit[90] & reg_we & ~wr_err;
assign msip0_wd = reg_wdata[0];
// Read data return
@@ -8226,9 +10257,28 @@
reg_rdata_next[28] = ip1_p60_qs;
reg_rdata_next[29] = ip1_p61_qs;
reg_rdata_next[30] = ip1_p62_qs;
+ reg_rdata_next[31] = ip1_p63_qs;
end
addr_hit[2]: begin
+ reg_rdata_next[0] = ip2_p64_qs;
+ reg_rdata_next[1] = ip2_p65_qs;
+ reg_rdata_next[2] = ip2_p66_qs;
+ reg_rdata_next[3] = ip2_p67_qs;
+ reg_rdata_next[4] = ip2_p68_qs;
+ reg_rdata_next[5] = ip2_p69_qs;
+ reg_rdata_next[6] = ip2_p70_qs;
+ reg_rdata_next[7] = ip2_p71_qs;
+ reg_rdata_next[8] = ip2_p72_qs;
+ reg_rdata_next[9] = ip2_p73_qs;
+ reg_rdata_next[10] = ip2_p74_qs;
+ reg_rdata_next[11] = ip2_p75_qs;
+ reg_rdata_next[12] = ip2_p76_qs;
+ reg_rdata_next[13] = ip2_p77_qs;
+ reg_rdata_next[14] = ip2_p78_qs;
+ end
+
+ addr_hit[3]: begin
reg_rdata_next[0] = le0_le0_qs;
reg_rdata_next[1] = le0_le1_qs;
reg_rdata_next[2] = le0_le2_qs;
@@ -8263,7 +10313,7 @@
reg_rdata_next[31] = le0_le31_qs;
end
- addr_hit[3]: begin
+ addr_hit[4]: begin
reg_rdata_next[0] = le1_le32_qs;
reg_rdata_next[1] = le1_le33_qs;
reg_rdata_next[2] = le1_le34_qs;
@@ -8295,261 +10345,344 @@
reg_rdata_next[28] = le1_le60_qs;
reg_rdata_next[29] = le1_le61_qs;
reg_rdata_next[30] = le1_le62_qs;
- end
-
- addr_hit[4]: begin
- reg_rdata_next[1:0] = prio0_qs;
+ reg_rdata_next[31] = le1_le63_qs;
end
addr_hit[5]: begin
- reg_rdata_next[1:0] = prio1_qs;
+ reg_rdata_next[0] = le2_le64_qs;
+ reg_rdata_next[1] = le2_le65_qs;
+ reg_rdata_next[2] = le2_le66_qs;
+ reg_rdata_next[3] = le2_le67_qs;
+ reg_rdata_next[4] = le2_le68_qs;
+ reg_rdata_next[5] = le2_le69_qs;
+ reg_rdata_next[6] = le2_le70_qs;
+ reg_rdata_next[7] = le2_le71_qs;
+ reg_rdata_next[8] = le2_le72_qs;
+ reg_rdata_next[9] = le2_le73_qs;
+ reg_rdata_next[10] = le2_le74_qs;
+ reg_rdata_next[11] = le2_le75_qs;
+ reg_rdata_next[12] = le2_le76_qs;
+ reg_rdata_next[13] = le2_le77_qs;
+ reg_rdata_next[14] = le2_le78_qs;
end
addr_hit[6]: begin
- reg_rdata_next[1:0] = prio2_qs;
+ reg_rdata_next[1:0] = prio0_qs;
end
addr_hit[7]: begin
- reg_rdata_next[1:0] = prio3_qs;
+ reg_rdata_next[1:0] = prio1_qs;
end
addr_hit[8]: begin
- reg_rdata_next[1:0] = prio4_qs;
+ reg_rdata_next[1:0] = prio2_qs;
end
addr_hit[9]: begin
- reg_rdata_next[1:0] = prio5_qs;
+ reg_rdata_next[1:0] = prio3_qs;
end
addr_hit[10]: begin
- reg_rdata_next[1:0] = prio6_qs;
+ reg_rdata_next[1:0] = prio4_qs;
end
addr_hit[11]: begin
- reg_rdata_next[1:0] = prio7_qs;
+ reg_rdata_next[1:0] = prio5_qs;
end
addr_hit[12]: begin
- reg_rdata_next[1:0] = prio8_qs;
+ reg_rdata_next[1:0] = prio6_qs;
end
addr_hit[13]: begin
- reg_rdata_next[1:0] = prio9_qs;
+ reg_rdata_next[1:0] = prio7_qs;
end
addr_hit[14]: begin
- reg_rdata_next[1:0] = prio10_qs;
+ reg_rdata_next[1:0] = prio8_qs;
end
addr_hit[15]: begin
- reg_rdata_next[1:0] = prio11_qs;
+ reg_rdata_next[1:0] = prio9_qs;
end
addr_hit[16]: begin
- reg_rdata_next[1:0] = prio12_qs;
+ reg_rdata_next[1:0] = prio10_qs;
end
addr_hit[17]: begin
- reg_rdata_next[1:0] = prio13_qs;
+ reg_rdata_next[1:0] = prio11_qs;
end
addr_hit[18]: begin
- reg_rdata_next[1:0] = prio14_qs;
+ reg_rdata_next[1:0] = prio12_qs;
end
addr_hit[19]: begin
- reg_rdata_next[1:0] = prio15_qs;
+ reg_rdata_next[1:0] = prio13_qs;
end
addr_hit[20]: begin
- reg_rdata_next[1:0] = prio16_qs;
+ reg_rdata_next[1:0] = prio14_qs;
end
addr_hit[21]: begin
- reg_rdata_next[1:0] = prio17_qs;
+ reg_rdata_next[1:0] = prio15_qs;
end
addr_hit[22]: begin
- reg_rdata_next[1:0] = prio18_qs;
+ reg_rdata_next[1:0] = prio16_qs;
end
addr_hit[23]: begin
- reg_rdata_next[1:0] = prio19_qs;
+ reg_rdata_next[1:0] = prio17_qs;
end
addr_hit[24]: begin
- reg_rdata_next[1:0] = prio20_qs;
+ reg_rdata_next[1:0] = prio18_qs;
end
addr_hit[25]: begin
- reg_rdata_next[1:0] = prio21_qs;
+ reg_rdata_next[1:0] = prio19_qs;
end
addr_hit[26]: begin
- reg_rdata_next[1:0] = prio22_qs;
+ reg_rdata_next[1:0] = prio20_qs;
end
addr_hit[27]: begin
- reg_rdata_next[1:0] = prio23_qs;
+ reg_rdata_next[1:0] = prio21_qs;
end
addr_hit[28]: begin
- reg_rdata_next[1:0] = prio24_qs;
+ reg_rdata_next[1:0] = prio22_qs;
end
addr_hit[29]: begin
- reg_rdata_next[1:0] = prio25_qs;
+ reg_rdata_next[1:0] = prio23_qs;
end
addr_hit[30]: begin
- reg_rdata_next[1:0] = prio26_qs;
+ reg_rdata_next[1:0] = prio24_qs;
end
addr_hit[31]: begin
- reg_rdata_next[1:0] = prio27_qs;
+ reg_rdata_next[1:0] = prio25_qs;
end
addr_hit[32]: begin
- reg_rdata_next[1:0] = prio28_qs;
+ reg_rdata_next[1:0] = prio26_qs;
end
addr_hit[33]: begin
- reg_rdata_next[1:0] = prio29_qs;
+ reg_rdata_next[1:0] = prio27_qs;
end
addr_hit[34]: begin
- reg_rdata_next[1:0] = prio30_qs;
+ reg_rdata_next[1:0] = prio28_qs;
end
addr_hit[35]: begin
- reg_rdata_next[1:0] = prio31_qs;
+ reg_rdata_next[1:0] = prio29_qs;
end
addr_hit[36]: begin
- reg_rdata_next[1:0] = prio32_qs;
+ reg_rdata_next[1:0] = prio30_qs;
end
addr_hit[37]: begin
- reg_rdata_next[1:0] = prio33_qs;
+ reg_rdata_next[1:0] = prio31_qs;
end
addr_hit[38]: begin
- reg_rdata_next[1:0] = prio34_qs;
+ reg_rdata_next[1:0] = prio32_qs;
end
addr_hit[39]: begin
- reg_rdata_next[1:0] = prio35_qs;
+ reg_rdata_next[1:0] = prio33_qs;
end
addr_hit[40]: begin
- reg_rdata_next[1:0] = prio36_qs;
+ reg_rdata_next[1:0] = prio34_qs;
end
addr_hit[41]: begin
- reg_rdata_next[1:0] = prio37_qs;
+ reg_rdata_next[1:0] = prio35_qs;
end
addr_hit[42]: begin
- reg_rdata_next[1:0] = prio38_qs;
+ reg_rdata_next[1:0] = prio36_qs;
end
addr_hit[43]: begin
- reg_rdata_next[1:0] = prio39_qs;
+ reg_rdata_next[1:0] = prio37_qs;
end
addr_hit[44]: begin
- reg_rdata_next[1:0] = prio40_qs;
+ reg_rdata_next[1:0] = prio38_qs;
end
addr_hit[45]: begin
- reg_rdata_next[1:0] = prio41_qs;
+ reg_rdata_next[1:0] = prio39_qs;
end
addr_hit[46]: begin
- reg_rdata_next[1:0] = prio42_qs;
+ reg_rdata_next[1:0] = prio40_qs;
end
addr_hit[47]: begin
- reg_rdata_next[1:0] = prio43_qs;
+ reg_rdata_next[1:0] = prio41_qs;
end
addr_hit[48]: begin
- reg_rdata_next[1:0] = prio44_qs;
+ reg_rdata_next[1:0] = prio42_qs;
end
addr_hit[49]: begin
- reg_rdata_next[1:0] = prio45_qs;
+ reg_rdata_next[1:0] = prio43_qs;
end
addr_hit[50]: begin
- reg_rdata_next[1:0] = prio46_qs;
+ reg_rdata_next[1:0] = prio44_qs;
end
addr_hit[51]: begin
- reg_rdata_next[1:0] = prio47_qs;
+ reg_rdata_next[1:0] = prio45_qs;
end
addr_hit[52]: begin
- reg_rdata_next[1:0] = prio48_qs;
+ reg_rdata_next[1:0] = prio46_qs;
end
addr_hit[53]: begin
- reg_rdata_next[1:0] = prio49_qs;
+ reg_rdata_next[1:0] = prio47_qs;
end
addr_hit[54]: begin
- reg_rdata_next[1:0] = prio50_qs;
+ reg_rdata_next[1:0] = prio48_qs;
end
addr_hit[55]: begin
- reg_rdata_next[1:0] = prio51_qs;
+ reg_rdata_next[1:0] = prio49_qs;
end
addr_hit[56]: begin
- reg_rdata_next[1:0] = prio52_qs;
+ reg_rdata_next[1:0] = prio50_qs;
end
addr_hit[57]: begin
- reg_rdata_next[1:0] = prio53_qs;
+ reg_rdata_next[1:0] = prio51_qs;
end
addr_hit[58]: begin
- reg_rdata_next[1:0] = prio54_qs;
+ reg_rdata_next[1:0] = prio52_qs;
end
addr_hit[59]: begin
- reg_rdata_next[1:0] = prio55_qs;
+ reg_rdata_next[1:0] = prio53_qs;
end
addr_hit[60]: begin
- reg_rdata_next[1:0] = prio56_qs;
+ reg_rdata_next[1:0] = prio54_qs;
end
addr_hit[61]: begin
- reg_rdata_next[1:0] = prio57_qs;
+ reg_rdata_next[1:0] = prio55_qs;
end
addr_hit[62]: begin
- reg_rdata_next[1:0] = prio58_qs;
+ reg_rdata_next[1:0] = prio56_qs;
end
addr_hit[63]: begin
- reg_rdata_next[1:0] = prio59_qs;
+ reg_rdata_next[1:0] = prio57_qs;
end
addr_hit[64]: begin
- reg_rdata_next[1:0] = prio60_qs;
+ reg_rdata_next[1:0] = prio58_qs;
end
addr_hit[65]: begin
- reg_rdata_next[1:0] = prio61_qs;
+ reg_rdata_next[1:0] = prio59_qs;
end
addr_hit[66]: begin
- reg_rdata_next[1:0] = prio62_qs;
+ reg_rdata_next[1:0] = prio60_qs;
end
addr_hit[67]: begin
+ reg_rdata_next[1:0] = prio61_qs;
+ end
+
+ addr_hit[68]: begin
+ reg_rdata_next[1:0] = prio62_qs;
+ end
+
+ addr_hit[69]: begin
+ reg_rdata_next[1:0] = prio63_qs;
+ end
+
+ addr_hit[70]: begin
+ reg_rdata_next[1:0] = prio64_qs;
+ end
+
+ addr_hit[71]: begin
+ reg_rdata_next[1:0] = prio65_qs;
+ end
+
+ addr_hit[72]: begin
+ reg_rdata_next[1:0] = prio66_qs;
+ end
+
+ addr_hit[73]: begin
+ reg_rdata_next[1:0] = prio67_qs;
+ end
+
+ addr_hit[74]: begin
+ reg_rdata_next[1:0] = prio68_qs;
+ end
+
+ addr_hit[75]: begin
+ reg_rdata_next[1:0] = prio69_qs;
+ end
+
+ addr_hit[76]: begin
+ reg_rdata_next[1:0] = prio70_qs;
+ end
+
+ addr_hit[77]: begin
+ reg_rdata_next[1:0] = prio71_qs;
+ end
+
+ addr_hit[78]: begin
+ reg_rdata_next[1:0] = prio72_qs;
+ end
+
+ addr_hit[79]: begin
+ reg_rdata_next[1:0] = prio73_qs;
+ end
+
+ addr_hit[80]: begin
+ reg_rdata_next[1:0] = prio74_qs;
+ end
+
+ addr_hit[81]: begin
+ reg_rdata_next[1:0] = prio75_qs;
+ end
+
+ addr_hit[82]: begin
+ reg_rdata_next[1:0] = prio76_qs;
+ end
+
+ addr_hit[83]: begin
+ reg_rdata_next[1:0] = prio77_qs;
+ end
+
+ addr_hit[84]: begin
+ reg_rdata_next[1:0] = prio78_qs;
+ end
+
+ addr_hit[85]: begin
reg_rdata_next[0] = ie00_e0_qs;
reg_rdata_next[1] = ie00_e1_qs;
reg_rdata_next[2] = ie00_e2_qs;
@@ -8584,7 +10717,7 @@
reg_rdata_next[31] = ie00_e31_qs;
end
- addr_hit[68]: begin
+ addr_hit[86]: begin
reg_rdata_next[0] = ie01_e32_qs;
reg_rdata_next[1] = ie01_e33_qs;
reg_rdata_next[2] = ie01_e34_qs;
@@ -8616,17 +10749,36 @@
reg_rdata_next[28] = ie01_e60_qs;
reg_rdata_next[29] = ie01_e61_qs;
reg_rdata_next[30] = ie01_e62_qs;
+ reg_rdata_next[31] = ie01_e63_qs;
end
- addr_hit[69]: begin
+ addr_hit[87]: begin
+ reg_rdata_next[0] = ie02_e64_qs;
+ reg_rdata_next[1] = ie02_e65_qs;
+ reg_rdata_next[2] = ie02_e66_qs;
+ reg_rdata_next[3] = ie02_e67_qs;
+ reg_rdata_next[4] = ie02_e68_qs;
+ reg_rdata_next[5] = ie02_e69_qs;
+ reg_rdata_next[6] = ie02_e70_qs;
+ reg_rdata_next[7] = ie02_e71_qs;
+ reg_rdata_next[8] = ie02_e72_qs;
+ reg_rdata_next[9] = ie02_e73_qs;
+ reg_rdata_next[10] = ie02_e74_qs;
+ reg_rdata_next[11] = ie02_e75_qs;
+ reg_rdata_next[12] = ie02_e76_qs;
+ reg_rdata_next[13] = ie02_e77_qs;
+ reg_rdata_next[14] = ie02_e78_qs;
+ end
+
+ addr_hit[88]: begin
reg_rdata_next[1:0] = threshold0_qs;
end
- addr_hit[70]: begin
- reg_rdata_next[5:0] = cc0_qs;
+ addr_hit[89]: begin
+ reg_rdata_next[6:0] = cc0_qs;
end
- addr_hit[71]: begin
+ addr_hit[90]: begin
reg_rdata_next[0] = msip0_qs;
end
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
index c75e474..2688c3f 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -176,6 +176,10 @@
base_addr: 0x40080000
size_byte: 0x1000
}
+ {
+ base_addr: 0x40150000
+ size_byte: 0x1000
+ }
]
}
{
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
index 73ef87d..3bf0637 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
@@ -21,7 +21,8 @@
}},
'{"peri", '{
'{32'h40000000, 32'h40020fff},
- '{32'h40080000, 32'h40080fff}
+ '{32'h40080000, 32'h40080fff},
+ '{32'h40150000, 32'h40150fff}
}},
'{"flash_ctrl", '{
'{32'h40030000, 32'h40030fff}
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
index 15573dd..84f3b59 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -10,9 +10,10 @@
localparam logic [31:0] ADDR_SPACE_DEBUG_MEM = 32'h 1a110000;
localparam logic [31:0] ADDR_SPACE_RAM_MAIN = 32'h 10000000;
localparam logic [31:0] ADDR_SPACE_EFLASH = 32'h 20000000;
- localparam logic [1:0][31:0] ADDR_SPACE_PERI = {
+ localparam logic [2:0][31:0] ADDR_SPACE_PERI = {
32'h 40000000,
- 32'h 40080000
+ 32'h 40080000,
+ 32'h 40150000
};
localparam logic [31:0] ADDR_SPACE_FLASH_CTRL = 32'h 40030000;
localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 40120000;
@@ -26,8 +27,9 @@
localparam logic [31:0] ADDR_MASK_DEBUG_MEM = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_RAM_MAIN = 32'h 0000ffff;
localparam logic [31:0] ADDR_MASK_EFLASH = 32'h 0007ffff;
- localparam logic [1:0][31:0] ADDR_MASK_PERI = {
+ localparam logic [2:0][31:0] ADDR_MASK_PERI = {
32'h 00020fff,
+ 32'h 00000fff,
32'h 00000fff
};
localparam logic [31:0] ADDR_MASK_FLASH_CTRL = 32'h 00000fff;
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
index 592566e..b091744 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -406,7 +406,9 @@
((tl_s1n_20_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) &&
(tl_s1n_20_us_h2d.a_address >= ADDR_SPACE_PERI[0])) ||
((tl_s1n_20_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
- (tl_s1n_20_us_h2d.a_address >= ADDR_SPACE_PERI[1]))
+ (tl_s1n_20_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
+ ((tl_s1n_20_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
+ (tl_s1n_20_us_h2d.a_address >= ADDR_SPACE_PERI[2]))
) begin
dev_sel_s1n_20 = 4'd4;
@@ -449,7 +451,9 @@
((tl_s1n_30_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) &&
(tl_s1n_30_us_h2d.a_address >= ADDR_SPACE_PERI[0])) ||
((tl_s1n_30_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
- (tl_s1n_30_us_h2d.a_address >= ADDR_SPACE_PERI[1]))
+ (tl_s1n_30_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
+ ((tl_s1n_30_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
+ (tl_s1n_30_us_h2d.a_address >= ADDR_SPACE_PERI[2]))
) begin
dev_sel_s1n_30 = 4'd3;
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
index 01d05a4..0f79f6f 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -25,6 +25,7 @@
gpio
spi_device
rv_timer
+ usbdev
]
}
nodes:
@@ -107,6 +108,23 @@
xbar: false
pipeline_byp: "true"
}
+ {
+ name: usbdev
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: usbdev
+ addr_range:
+ [
+ {
+ base_addr: 0x40150000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ pipeline_byp: "true"
+ }
]
clock: clk_peri_i
type: xbar
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
index 740f688..cf39b07 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
@@ -19,3 +19,4 @@
`CONNECT_TL_DEVICE_IF(gpio)
`CONNECT_TL_DEVICE_IF(spi_device)
`CONNECT_TL_DEVICE_IF(rv_timer)
+`CONNECT_TL_DEVICE_IF(usbdev)
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
index 6c40c09..82ac3aa 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -18,6 +18,9 @@
}},
'{"rv_timer", '{
'{32'h40080000, 32'h40080fff}
+ }},
+ '{"usbdev", '{
+ '{32'h40150000, 32'h40150fff}
}}};
// List of Xbar hosts
@@ -26,5 +29,6 @@
"uart",
"gpio",
"spi_device",
- "rv_timer"}}
+ "rv_timer",
+ "usbdev"}}
};
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
index 380c458..4df62a7 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
@@ -38,5 +38,11 @@
.h2d (tl_rv_timer_o),
.d2h (tl_rv_timer_i)
);
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_usbdev (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_usbdev_o),
+ .d2h (tl_usbdev_i)
+ );
endmodule
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
index 3f303fa..f95de98 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -10,20 +10,23 @@
localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40010000;
localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40020000;
localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40080000;
+ localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 40150000;
localparam logic [31:0] ADDR_MASK_UART = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_GPIO = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_USBDEV = 32'h 00000fff;
localparam int N_HOST = 1;
- localparam int N_DEVICE = 4;
+ localparam int N_DEVICE = 5;
typedef enum int {
TlUart = 0,
TlGpio = 1,
TlSpiDevice = 2,
- TlRvTimer = 3
+ TlRvTimer = 3,
+ TlUsbdev = 4
} tl_device_e;
typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
index 4ee2010..d1775af 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
@@ -7,11 +7,12 @@
//
// Interconnect
// main
-// -> s1n_5
+// -> s1n_6
// -> uart
// -> gpio
// -> spi_device
// -> rv_timer
+// -> usbdev
module xbar_peri (
input clk_peri_i,
@@ -30,6 +31,8 @@
input tlul_pkg::tl_d2h_t tl_spi_device_i,
output tlul_pkg::tl_h2d_t tl_rv_timer_o,
input tlul_pkg::tl_d2h_t tl_rv_timer_i,
+ output tlul_pkg::tl_h2d_t tl_usbdev_o,
+ input tlul_pkg::tl_d2h_t tl_usbdev_i,
input scanmode_i
);
@@ -42,47 +45,53 @@
logic unused_scanmode;
assign unused_scanmode = scanmode_i;
- tl_h2d_t tl_s1n_5_us_h2d ;
- tl_d2h_t tl_s1n_5_us_d2h ;
+ tl_h2d_t tl_s1n_6_us_h2d ;
+ tl_d2h_t tl_s1n_6_us_d2h ;
- tl_h2d_t tl_s1n_5_ds_h2d [4];
- tl_d2h_t tl_s1n_5_ds_d2h [4];
+ tl_h2d_t tl_s1n_6_ds_h2d [5];
+ tl_d2h_t tl_s1n_6_ds_d2h [5];
// Create steering signal
- logic [2:0] dev_sel_s1n_5;
+ logic [2:0] dev_sel_s1n_6;
- assign tl_uart_o = tl_s1n_5_ds_h2d[0];
- assign tl_s1n_5_ds_d2h[0] = tl_uart_i;
+ assign tl_uart_o = tl_s1n_6_ds_h2d[0];
+ assign tl_s1n_6_ds_d2h[0] = tl_uart_i;
- assign tl_gpio_o = tl_s1n_5_ds_h2d[1];
- assign tl_s1n_5_ds_d2h[1] = tl_gpio_i;
+ assign tl_gpio_o = tl_s1n_6_ds_h2d[1];
+ assign tl_s1n_6_ds_d2h[1] = tl_gpio_i;
- assign tl_spi_device_o = tl_s1n_5_ds_h2d[2];
- assign tl_s1n_5_ds_d2h[2] = tl_spi_device_i;
+ assign tl_spi_device_o = tl_s1n_6_ds_h2d[2];
+ assign tl_s1n_6_ds_d2h[2] = tl_spi_device_i;
- assign tl_rv_timer_o = tl_s1n_5_ds_h2d[3];
- assign tl_s1n_5_ds_d2h[3] = tl_rv_timer_i;
+ assign tl_rv_timer_o = tl_s1n_6_ds_h2d[3];
+ assign tl_s1n_6_ds_d2h[3] = tl_rv_timer_i;
- assign tl_s1n_5_us_h2d = tl_main_i;
- assign tl_main_o = tl_s1n_5_us_d2h;
+ assign tl_usbdev_o = tl_s1n_6_ds_h2d[4];
+ assign tl_s1n_6_ds_d2h[4] = tl_usbdev_i;
+
+ assign tl_s1n_6_us_h2d = tl_main_i;
+ assign tl_main_o = tl_s1n_6_us_d2h;
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_5 = 3'd4;
- if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
- dev_sel_s1n_5 = 3'd0;
+ dev_sel_s1n_6 = 3'd5;
+ if ((tl_s1n_6_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
+ dev_sel_s1n_6 = 3'd0;
- end else if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
- dev_sel_s1n_5 = 3'd1;
+ end else if ((tl_s1n_6_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
+ dev_sel_s1n_6 = 3'd1;
- end else if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
- dev_sel_s1n_5 = 3'd2;
+ end else if ((tl_s1n_6_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
+ dev_sel_s1n_6 = 3'd2;
- end else if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
- dev_sel_s1n_5 = 3'd3;
+ end else if ((tl_s1n_6_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
+ dev_sel_s1n_6 = 3'd3;
+
+ end else if ((tl_s1n_6_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
+ dev_sel_s1n_6 = 3'd4;
end
end
@@ -91,17 +100,17 @@
tlul_socket_1n #(
.HReqDepth (4'h0),
.HRspDepth (4'h0),
- .DReqDepth ({4{4'h0}}),
- .DRspDepth ({4{4'h0}}),
- .N (4)
- ) u_s1n_5 (
+ .DReqDepth ({5{4'h0}}),
+ .DRspDepth ({5{4'h0}}),
+ .N (5)
+ ) u_s1n_6 (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .tl_h_i (tl_s1n_5_us_h2d),
- .tl_h_o (tl_s1n_5_us_d2h),
- .tl_d_o (tl_s1n_5_ds_h2d),
- .tl_d_i (tl_s1n_5_ds_d2h),
- .dev_select (dev_sel_s1n_5)
+ .tl_h_i (tl_s1n_6_us_h2d),
+ .tl_h_o (tl_s1n_6_us_d2h),
+ .tl_d_o (tl_s1n_6_ds_h2d),
+ .tl_d_i (tl_s1n_6_ds_d2h),
+ .dev_select (dev_sel_s1n_6)
);
endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 73d19d4..5ced781 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -9,6 +9,9 @@
input clk_i,
input rst_ni,
+ // USB clock
+ input clk_usb_48mhz_i,
+
// JTAG interface
input jtag_tck_i,
input jtag_tms_i,
@@ -30,6 +33,15 @@
input dio_uart_rx_i,
output logic dio_uart_tx_o,
output logic dio_uart_tx_en_o,
+ input dio_usbdev_sense_i,
+ output logic dio_usbdev_pullup_o,
+ output logic dio_usbdev_pullup_en_o,
+ input dio_usbdev_dp_i,
+ output logic dio_usbdev_dp_o,
+ output logic dio_usbdev_dp_en_o,
+ input dio_usbdev_dn_i,
+ output logic dio_usbdev_dn_o,
+ output logic dio_usbdev_dn_en_o,
input scanmode_i // 1 for Scan
);
@@ -85,6 +97,8 @@
tl_d2h_t tl_alert_handler_d_d2h;
tl_h2d_t tl_nmi_gen_d_h2d;
tl_d2h_t tl_nmi_gen_d_d2h;
+ tl_h2d_t tl_usbdev_d_h2d;
+ tl_d2h_t tl_usbdev_d_d2h;
tl_h2d_t tl_rom_d_h2d;
tl_d2h_t tl_rom_d_d2h;
@@ -106,10 +120,12 @@
logic sys_rst_n;
logic sys_fixed_rst_n;
logic spi_device_rst_n;
+ logic usb_rst_n;
//clock wires declaration
logic main_clk;
logic fixed_clk;
+ logic usb_clk;
// Signals
logic [31:0] m2p;
@@ -137,9 +153,19 @@
// pinmux
// alert_handler
// nmi_gen
+ // usbdev
+ logic cio_usbdev_sense_p2d;
+ logic cio_usbdev_dp_p2d;
+ logic cio_usbdev_dn_p2d;
+ logic cio_usbdev_pullup_d2p;
+ logic cio_usbdev_pullup_en_d2p;
+ logic cio_usbdev_dp_d2p;
+ logic cio_usbdev_dp_en_d2p;
+ logic cio_usbdev_dn_d2p;
+ logic cio_usbdev_dn_en_d2p;
- logic [62:0] intr_vector;
+ logic [78:0] intr_vector;
// Interrupt source list
logic intr_uart_tx_watermark;
logic intr_uart_rx_watermark;
@@ -174,13 +200,29 @@
logic intr_nmi_gen_esc1;
logic intr_nmi_gen_esc2;
logic intr_nmi_gen_esc3;
+ logic intr_usbdev_pkt_received;
+ logic intr_usbdev_pkt_sent;
+ logic intr_usbdev_disconnected;
+ logic intr_usbdev_host_lost;
+ logic intr_usbdev_link_reset;
+ logic intr_usbdev_link_suspend;
+ logic intr_usbdev_link_resume;
+ logic intr_usbdev_av_empty;
+ logic intr_usbdev_rx_full;
+ logic intr_usbdev_av_overflow;
+ logic intr_usbdev_link_in_err;
+ logic intr_usbdev_rx_crc_err;
+ logic intr_usbdev_rx_pid_err;
+ logic intr_usbdev_rx_bitstuff_err;
+ logic intr_usbdev_frame;
+ logic intr_usbdev_connected;
logic [0:0] irq_plic;
logic [0:0] msip;
- logic [5:0] irq_id[1];
- logic [5:0] unused_irq_id[1];
+ logic [6:0] irq_id[1];
+ logic [6:0] unused_irq_id[1];
// this avoids lint errors
assign unused_irq_id = irq_id;
@@ -193,10 +235,13 @@
prim_pkg::esc_rx_t [alert_pkg::N_ESC_SEV-1:0] esc_rx;
- // clock assignments
+ // Clock assignments
assign main_clk = clk_i;
assign fixed_clk = clk_i;
+ // Separate clock input for USB clock
+ assign usb_clk = clk_usb_48mhz_i;
+
// Non-debug module reset == reset for everything except for the debug module
logic ndmreset_req;
@@ -206,10 +251,17 @@
assign lc_rst_n = rst_ni;
assign sys_rst_n = (scanmode_i) ? lc_rst_n : ~ndmreset_req & lc_rst_n;
- //non-root reset assignments
+ // Non-root reset assignments
assign sys_fixed_rst_n = sys_rst_n;
assign spi_device_rst_n = sys_rst_n;
+ // Reset synchronizer for USB
+ logic [1:0] usb_rst_q;
+ always_ff @(posedge usb_clk) begin
+ usb_rst_q <= {usb_rst_q[0], sys_rst_n};
+ end
+ assign usb_rst_n = sys_rst_n & usb_rst_q[1];
+
// debug request from rv_dm to core
logic debug_req;
@@ -619,8 +671,74 @@
.rst_ni (sys_rst_n)
);
+ usbdev usbdev (
+ .tl_i (tl_usbdev_d_h2d),
+ .tl_o (tl_usbdev_d_d2h),
+
+ // Differential data - Currently not used.
+ .cio_d_i (1'b0),
+ .cio_d_o (),
+ .cio_se0_o (),
+
+ // Single-ended data
+ .cio_dp_i (cio_usbdev_dp_p2d),
+ .cio_dn_i (cio_usbdev_dn_p2d),
+ .cio_dp_o (cio_usbdev_dp_d2p),
+ .cio_dn_o (cio_usbdev_dn_d2p),
+
+ // Non-data I/O
+ .cio_sense_i (cio_usbdev_sense_p2d),
+ .cio_oe_o (cio_usbdev_dp_en_d2p),
+ .cio_tx_mode_se_o (),
+ .cio_pullup_en_o (cio_usbdev_pullup_en_d2p),
+ .cio_suspend_o (),
+
+ // Interrupt
+ .intr_pkt_received_o (intr_usbdev_pkt_received),
+ .intr_pkt_sent_o (intr_usbdev_pkt_sent),
+ .intr_disconnected_o (intr_usbdev_disconnected),
+ .intr_host_lost_o (intr_usbdev_host_lost),
+ .intr_link_reset_o (intr_usbdev_link_reset),
+ .intr_link_suspend_o (intr_usbdev_link_suspend),
+ .intr_link_resume_o (intr_usbdev_link_resume),
+ .intr_av_empty_o (intr_usbdev_av_empty),
+ .intr_rx_full_o (intr_usbdev_rx_full),
+ .intr_av_overflow_o (intr_usbdev_av_overflow),
+ .intr_link_in_err_o (intr_usbdev_link_in_err),
+ .intr_rx_crc_err_o (intr_usbdev_rx_crc_err),
+ .intr_rx_pid_err_o (intr_usbdev_rx_pid_err),
+ .intr_rx_bitstuff_err_o (intr_usbdev_rx_bitstuff_err),
+ .intr_frame_o (intr_usbdev_frame),
+ .intr_connected_o (intr_usbdev_connected),
+
+ .clk_i (fixed_clk),
+ .clk_usb_48mhz_i (usb_clk),
+ .rst_ni (sys_fixed_rst_n),
+ .rst_usb_48mhz_ni (usb_rst_n)
+ );
+
+ // USB assignments
+ assign cio_usbdev_dn_en_d2p = cio_usbdev_dp_en_d2p; // have a single output enable only
+ assign cio_usbdev_pullup_d2p = 1'b1;
+
// interrupt assignments
assign intr_vector = {
+ intr_usbdev_connected,
+ intr_usbdev_frame,
+ intr_usbdev_rx_bitstuff_err,
+ intr_usbdev_rx_pid_err,
+ intr_usbdev_rx_crc_err,
+ intr_usbdev_link_in_err,
+ intr_usbdev_av_overflow,
+ intr_usbdev_rx_full,
+ intr_usbdev_av_empty,
+ intr_usbdev_link_resume,
+ intr_usbdev_link_suspend,
+ intr_usbdev_link_reset,
+ intr_usbdev_host_lost,
+ intr_usbdev_disconnected,
+ intr_usbdev_pkt_sent,
+ intr_usbdev_pkt_received,
intr_nmi_gen_esc3,
intr_nmi_gen_esc2,
intr_nmi_gen_esc1,
@@ -707,6 +825,8 @@
.tl_spi_device_i (tl_spi_device_d_d2h),
.tl_rv_timer_o (tl_rv_timer_d_h2d),
.tl_rv_timer_i (tl_rv_timer_d_d2h),
+ .tl_usbdev_o (tl_usbdev_d_h2d),
+ .tl_usbdev_i (tl_usbdev_d_d2h),
.scanmode_i
);
@@ -730,6 +850,15 @@
assign cio_uart_rx_p2d = dio_uart_rx_i;
assign dio_uart_tx_o = cio_uart_tx_d2p;
assign dio_uart_tx_en_o = cio_uart_tx_en_d2p;
+ assign cio_usbdev_sense_p2d = dio_usbdev_sense_i;
+ assign dio_usbdev_pullup_o = cio_usbdev_pullup_d2p;
+ assign dio_usbdev_pullup_en_o = cio_usbdev_pullup_en_d2p;
+ assign cio_usbdev_dp_p2d = dio_usbdev_dp_i;
+ assign dio_usbdev_dp_o = cio_usbdev_dp_d2p;
+ assign dio_usbdev_dp_en_o = cio_usbdev_dp_en_d2p;
+ assign cio_usbdev_dn_p2d = dio_usbdev_dn_i;
+ assign dio_usbdev_dn_o = cio_usbdev_dn_d2p;
+ assign dio_usbdev_dn_en_o = cio_usbdev_dn_en_d2p;
// make sure scanmode_i is never X (including during reset)
`ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0)
diff --git a/hw/top_earlgrey/rtl/padctl.sv b/hw/top_earlgrey/rtl/padctl.sv
index bdef783..89f737d 100644
--- a/hw/top_earlgrey/rtl/padctl.sv
+++ b/hw/top_earlgrey/rtl/padctl.sv
@@ -31,6 +31,21 @@
inout IO_GP13,
inout IO_GP14,
inout IO_GP15,
+ // USB device side
+ output cio_usbdev_sense_p2d,
+ input cio_usbdev_pullup_d2p,
+ input cio_usbdev_pullup_en_d2p,
+ output cio_usbdev_dp_p2d,
+ input cio_usbdev_dp_d2p,
+ input cio_usbdev_dp_en_d2p,
+ output cio_usbdev_dn_p2d,
+ input cio_usbdev_dn_d2p,
+ input cio_usbdev_dn_en_d2p,
+ // USB pads
+ inout IO_USB_DP0,
+ inout IO_USB_DN0,
+ input IO_USB_SENSE0,
+ output IO_USB_PULLUP0,
// SPI device interface
output cio_spi_device_sck_p2d,
@@ -56,6 +71,19 @@
input IO_DPS7
);
+ // USB
+ assign cio_usbdev_sense_p2d = IO_USB_SENSE0;
+ assign IO_USB_PULLUP0 = cio_usbdev_pullup_en_d2p ? cio_usbdev_pullup_d2p : 1'bz;
+
+ assign IO_USB_DP0 = cio_usbdev_dp_en_d2p ? cio_usbdev_dp_d2p : 1'bz;
+ assign IO_USB_DN0 = cio_usbdev_dn_en_d2p ? cio_usbdev_dn_d2p : 1'bz;
+
+ // Note that while transmitting, the receive (p2d) line must be fixed.
+ // Otherwise you are trying to regenerate the bit clock from the bit
+ // clock you are regenerating, rather than just holding the phase.
+ assign cio_usbdev_dp_p2d = cio_usbdev_dp_en_d2p ? 1'b1 : IO_USB_DP0;
+ assign cio_usbdev_dn_p2d = cio_usbdev_dn_en_d2p ? 1'b0 : IO_USB_DN0;
+
// JTAG or SPI mux to the FTDI MSEE pins DPS0-DPS6
logic jtag_spi_n, dps2, dps2_en;
logic boot_strap;
diff --git a/hw/top_earlgrey/rtl/padctl_usb.sv b/hw/top_earlgrey/rtl/padctl_usb.sv
deleted file mode 100644
index d470c6e..0000000
--- a/hw/top_earlgrey/rtl/padctl_usb.sv
+++ /dev/null
@@ -1,158 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-module padctl_usb (
- // UART device side
- input cio_uart_tx_d2p,
- input cio_uart_tx_en_d2p,
- output cio_uart_rx_p2d,
- // USB device side
- output cio_usb_dp_p2d[2],
- input cio_usb_dp_d2p[2],
- input cio_usb_dp_en_d2p[2],
- output cio_usb_dn_p2d[2],
- input cio_usb_dn_d2p[2],
- input cio_usb_dn_en_d2p[2],
- output cio_usb_sense_p2d[2],
- input cio_usb_pullup_d2p[2],
- input cio_usb_pullup_en_d2p[2],
-
- // UART pads
- input IO_URX,
- output IO_UTX,
-
- // USB pads
- inout IO_USB_DP0,
- inout IO_USB_DN0,
- input IO_USB_SENSE0,
- output IO_USB_PULLUP0,
- inout IO_USB_DP1,
- inout IO_USB_DN1,
- input IO_USB_SENSE1,
- output IO_USB_PULLUP1,
- // GPIO device side
- input [31:0] cio_gpio_d2p,
- input [31:0] cio_gpio_en_d2p,
- output [31:0] cio_gpio_p2d,
- // GPIO pads
- inout IO_GP0,
- inout IO_GP1,
- inout IO_GP2,
- inout IO_GP3,
- inout IO_GP4,
- inout IO_GP5,
- inout IO_GP6,
- inout IO_GP7,
- inout IO_GP8,
- inout IO_GP9,
- inout IO_GP10,
- inout IO_GP11,
- inout IO_GP12,
- inout IO_GP13,
- inout IO_GP14,
- inout IO_GP15,
-
- // SPI device interface
- output cio_spi_device_sck_p2d,
- output cio_spi_device_csb_p2d,
- output cio_spi_device_mosi_p2d,
- input cio_spi_device_miso_d2p,
- input cio_spi_device_miso_en_d2p,
- // JTAG interface
- output cio_jtag_tck_p2d,
- output cio_jtag_tms_p2d,
- output cio_jtag_trst_n_p2d,
- output cio_jtag_srst_n_p2d,
- output cio_jtag_tdi_p2d,
- input cio_jtag_tdo_d2p,
- // FTDI MSEE pins shared between JTAG and SPI
- input IO_DPS0,
- input IO_DPS1,
- output IO_DPS2,
- input IO_DPS3,
- input IO_DPS4,
- input IO_DPS5,
- input IO_DPS6
-);
-
- // Important that the rx (p2d) line is fixed when transmitting
- // Otherwise you are trying to regenerate the bit clock from
- // the bit clock you are regenerating, rather than just holding the phase
- assign IO_USB_DP0 = cio_usb_dp_en_d2p[0] ? cio_usb_dp_d2p[0] : 1'bz;
- assign cio_usb_dp_p2d[0] = cio_usb_dp_en_d2p[0] ? 1'b1 : IO_USB_DP0;
-
- assign IO_USB_DN0 = cio_usb_dn_en_d2p[0] ? cio_usb_dn_d2p[0] : 1'bz;
- assign cio_usb_dn_p2d[0] = cio_usb_dn_en_d2p[0] ? 1'b0 : IO_USB_DN0;
-
- assign IO_USB_PULLUP0 = cio_usb_pullup_en_d2p[0] ? cio_usb_pullup_d2p[0] : 1'bz;
- assign cio_usb_sense_p2d[0] = IO_USB_SENSE0;
-
- assign IO_USB_DP1 = cio_usb_dp_en_d2p[1] ? cio_usb_dp_d2p[1] : 1'bz;
- assign cio_usb_dp_p2d[1] = cio_usb_dp_en_d2p[1] ? 1'b1 : IO_USB_DP1;
-
- assign IO_USB_DN1 = cio_usb_dn_en_d2p[1] ? cio_usb_dn_d2p[1] : 1'bz;
- assign cio_usb_dn_p2d[1] = cio_usb_dn_en_d2p[1] ? 1'b0 : IO_USB_DN1;
-
- assign IO_USB_PULLUP1 = cio_usb_pullup_en_d2p[1] ? cio_usb_pullup_d2p[1] : 1'bz;
- assign cio_usb_sense_p2d[1] = IO_USB_SENSE1;
-
- // JTAG or SPI mux to the FTDI MSEE pins DPS0-DPS6
- logic jtag_spi_n, dps2, dps2_en;
-
- assign cio_gpio_p2d = {
- 15'h0, // unpopulated
- jtag_spi_n, // Use GPIO16 to pass SPI/JTAG control flag
- IO_GP15,
- IO_GP14,
- IO_GP13,
- IO_GP12,
- IO_GP11,
- IO_GP10,
- IO_GP9,
- IO_GP8,
- IO_GP7,
- IO_GP6,
- IO_GP5,
- IO_GP4,
- IO_GP3,
- IO_GP2,
- IO_GP1,
- IO_GP0
- };
-
- assign IO_GP0 = cio_gpio_en_d2p[0] ? cio_gpio_d2p[0] : 1'bz;
- assign IO_GP1 = cio_gpio_en_d2p[1] ? cio_gpio_d2p[1] : 1'bz;
- assign IO_GP2 = cio_gpio_en_d2p[2] ? cio_gpio_d2p[2] : 1'bz;
- assign IO_GP3 = cio_gpio_en_d2p[3] ? cio_gpio_d2p[3] : 1'bz;
- assign IO_GP4 = cio_gpio_en_d2p[4] ? cio_gpio_d2p[4] : 1'bz;
- assign IO_GP5 = cio_gpio_en_d2p[5] ? cio_gpio_d2p[5] : 1'bz;
- assign IO_GP6 = cio_gpio_en_d2p[6] ? cio_gpio_d2p[6] : 1'bz;
- assign IO_GP7 = cio_gpio_en_d2p[7] ? cio_gpio_d2p[7] : 1'bz;
- assign IO_GP8 = cio_gpio_en_d2p[8] ? cio_gpio_d2p[8] : 1'bz;
- assign IO_GP9 = cio_gpio_en_d2p[9] ? cio_gpio_d2p[9] : 1'bz;
- assign IO_GP10 = cio_gpio_en_d2p[10] ? cio_gpio_d2p[10] : 1'bz;
- assign IO_GP11 = cio_gpio_en_d2p[11] ? cio_gpio_d2p[11] : 1'bz;
- assign IO_GP12 = cio_gpio_en_d2p[12] ? cio_gpio_d2p[12] : 1'bz;
- assign IO_GP13 = cio_gpio_en_d2p[13] ? cio_gpio_d2p[13] : 1'bz;
- assign IO_GP14 = cio_gpio_en_d2p[14] ? cio_gpio_d2p[14] : 1'bz;
- assign IO_GP15 = cio_gpio_en_d2p[15] ? cio_gpio_d2p[15] : 1'bz;
-
- assign jtag_spi_n = IO_DPS6;
-
- assign cio_spi_device_sck_p2d = jtag_spi_n ? 0 : IO_DPS0;
- assign cio_jtag_tck_p2d = jtag_spi_n ? IO_DPS0 : 0;
- assign cio_spi_device_mosi_p2d = jtag_spi_n ? 0 : IO_DPS1;
- assign cio_jtag_tdi_p2d = jtag_spi_n ? IO_DPS1 : 0;
-
- assign dps2 = jtag_spi_n ? cio_jtag_tdi_p2d : cio_spi_device_miso_d2p;
- assign dps2_en = jtag_spi_n ? 1 : cio_spi_device_miso_en_d2p;
- assign IO_DPS2 = dps2_en ? dps2 : 1'bz;
-
- assign cio_spi_device_csb_p2d = jtag_spi_n ? 1 : IO_DPS3;
- assign cio_jtag_tms_p2d = jtag_spi_n ? IO_DPS3 : 0;
-
- assign cio_jtag_trst_n_p2d = jtag_spi_n ? IO_DPS4 : 1;
- assign cio_jtag_srst_n_p2d = jtag_spi_n ? IO_DPS5 : 1;
-
-endmodule
diff --git a/hw/top_earlgrey/rtl/tlul_xbar_usb.sv b/hw/top_earlgrey/rtl/tlul_xbar_usb.sv
deleted file mode 100644
index 9440f6f..0000000
--- a/hw/top_earlgrey/rtl/tlul_xbar_usb.sv
+++ /dev/null
@@ -1,209 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-// TODO: Only here until code is ported to use top generator
-module tlul_xbar_usb (
- input clk_i,
- input rst_ni,
-
- // Host accepter
- input tlul_pkg::tl_h2d_t tl_h_i [tl_main_pkg::N_HOST],
- output tlul_pkg::tl_d2h_t tl_h_o [tl_main_pkg::N_HOST],
-
- // Device sender
- output tlul_pkg::tl_h2d_t tl_d_o [tl_main_pkg::N_DEVICE],
- input tlul_pkg::tl_d2h_t tl_d_i [tl_main_pkg::N_DEVICE]
-);
-
- import tlul_pkg::*;
- import tl_main_pkg::*;
-
- //
- // Core D interface connects to Sram, Uart, Gpio, DebugMem and error
- //
- localparam int unsigned N_CORE_D_DEVICE = 5;
-
- typedef enum logic [2:0] {
- CoreDToSram = 3'h0,
- CoreDToUart = 3'h1,
- CoreDToGpio = 3'h2,
- CoreDToDebugMem = 3'h3,
- CoreDToSpiDevice = 3'h4,
- CoreDToErr = 3'h5
- } core_d_dsp_e;
-
- core_d_dsp_e dev_select_core_d;
-
- tl_h2d_t tl_core_d_h2d [N_CORE_D_DEVICE];
- tl_d2h_t tl_core_d_d2h [N_CORE_D_DEVICE];
-
- tlul_socket_1n #(
- .N (N_CORE_D_DEVICE),
- .HReqPass (1'b0), // register just outside of core
- .HRspPass (1'b0), // register just outside of core
- .DReqPass ({N_CORE_D_DEVICE{1'b1}}), // unregistered
- .DRspPass ({N_CORE_D_DEVICE{1'b1}}), // unregistered
- .HReqDepth (4'h2), // some elasticity
- .HRspDepth (4'h2), // some elasticity
- .DReqDepth ({N_CORE_D_DEVICE{4'h1}}), // minimal elasticity
- .DRspDepth ({N_CORE_D_DEVICE{4'h1}}) // minimal elasticity
- ) core_d_socket_14 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .tl_h_i (tl_h_i[TlCored]),
- .tl_h_o (tl_h_o[TlCored]),
- .tl_d_o (tl_core_d_h2d),
- .tl_d_i (tl_core_d_d2h),
- .dev_select (dev_select_core_d)
- );
-
- // address map lookup, will eventually be automated via configuration
- assign dev_select_core_d =
- ((tl_h_i[TlCored].a_address & ~ADDR_MASK_RAM_MAIN) == ADDR_SPACE_RAM_MAIN) ? CoreDToSram :
- ((tl_h_i[TlCored].a_address & ~ADDR_MASK_UART) == ADDR_SPACE_UART) ? CoreDToUart :
- ((tl_h_i[TlCored].a_address & ~ADDR_MASK_GPIO) == ADDR_SPACE_GPIO) ? CoreDToGpio :
- ((tl_h_i[TlCored].a_address & ~ADDR_MASK_DEBUG_MEM) == ADDR_SPACE_DEBUG_MEM) ? CoreDToDebugMem :
- ((tl_h_i[TlCored].a_address & ~ADDR_MASK_SPI_DEVICE) == ADDR_SPACE_SPI_DEVICE) ? CoreDToSpiDevice :
- CoreDToErr; // indicate to socket to return error
-
-
- //
- // Core I connects to SRAM and Debug Memory and error
- // TODO: Add connection to bootrom
- //
- localparam int unsigned N_CORE_I_DEVICE = 2;
-
- typedef enum logic [1:0] {
- CoreIToSram = 2'h0,
- CoreIToDebugMem = 2'h1,
- CoreIToErr = 2'h2
- } core_i_dsp_e;
-
- core_i_dsp_e dev_select_core_i;
-
- tl_h2d_t tl_core_i_h2d [N_CORE_I_DEVICE];
- tl_d2h_t tl_core_i_d2h [N_CORE_I_DEVICE];
-
- tlul_socket_1n #(
- .N (N_CORE_I_DEVICE),
- .HReqPass (1'b0), // register just outside of core
- .HRspPass (1'b0), // register just outside of core
- .DReqPass ({N_CORE_I_DEVICE{1'b1}}), // unregistered
- .DRspPass ({N_CORE_I_DEVICE{1'b1}}), // unregistered
- .HReqDepth (4'h2), // some elasticity
- .HRspDepth (4'h2), // some elasticity
- .DReqDepth ({N_CORE_I_DEVICE{4'h1}}), // minimal elasticity
- .DRspDepth ({N_CORE_I_DEVICE{4'h1}}) // minimal elasticity
- ) core_i_socket_12 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .tl_h_i (tl_h_i[TlCorei]),
- .tl_h_o (tl_h_o[TlCorei]),
- .tl_d_o (tl_core_i_h2d),
- .tl_d_i (tl_core_i_d2h),
- .dev_select (dev_select_core_i)
- );
-
- // address map lookup, will eventually be automated via configuration
- assign dev_select_core_i =
- ((tl_h_i[TlCorei].a_address & ~ADDR_MASK_RAM_MAIN) == ADDR_SPACE_RAM_MAIN) ? CoreIToSram :
- ((tl_h_i[TlCorei].a_address & ~ADDR_MASK_DEBUG_MEM) == ADDR_SPACE_DEBUG_MEM) ? CoreIToDebugMem :
- CoreIToErr; // indicate to socket to return error
-
-
- //
- // SRAM connects to Core I, Core D and Debug SBA
- //
- localparam int unsigned N_SRAM_HOST = 3;
-
- typedef enum logic [1:0] {
- SramFromCoreI = 2'h0,
- SramFromCoreD = 2'h1,
- SramFromDebugSba = 2'h2
- } sram_host_e;
-
- tl_h2d_t tl_sram_h_h2d [N_SRAM_HOST];
- tl_d2h_t tl_sram_h_d2h [N_SRAM_HOST];
-
- assign tl_sram_h_h2d[SramFromCoreI] = tl_core_i_h2d[CoreIToSram];
- assign tl_sram_h_h2d[SramFromCoreD] = tl_core_d_h2d[CoreDToSram];
- assign tl_sram_h_h2d[SramFromDebugSba] = tl_h_i[TlDmSba];
-
- assign tl_core_i_d2h[CoreIToSram] = tl_sram_h_d2h[SramFromCoreI];
- assign tl_core_d_d2h[CoreDToSram] = tl_sram_h_d2h[SramFromCoreD];
- assign tl_h_o[TlDmSba] = tl_sram_h_d2h[SramFromDebugSba];
-
- tlul_socket_m1 #(
- .M (N_SRAM_HOST),
- .HReqPass ({N_SRAM_HOST{1'b1}}), // unregistered
- .HRspPass ({N_SRAM_HOST{1'b1}}), // unregistered
- .HReqDepth ({N_SRAM_HOST{4'h1}}), // minimal elasticity
- .HRspDepth ({N_SRAM_HOST{4'h1}}), // minimal elasticity
- .DReqPass (1'b1), // unregistered
- .DRspPass (1'b1), // unregistered
- .DReqDepth (4'h1), // minimal elasticity
- .DRspDepth (4'h1) // minimal elasticity
- ) sram_socket_31 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .tl_h_i (tl_sram_h_h2d),
- .tl_h_o (tl_sram_h_d2h),
- .tl_d_o (tl_d_o[TlRamMain]),
- .tl_d_i (tl_d_i[TlRamMain])
- );
-
-
- //
- // Debug Memory connects to Core I and Core D
- //
- localparam int unsigned N_DEBUGMEM_HOST = 2;
-
- typedef enum logic [0:0] {
- DebugMemFromCoreI = 1'h0,
- DebugMemFromCoreD = 1'h1
- } debugmem_host_e;
-
- tl_h2d_t tl_debugmem_h_h2d [N_DEBUGMEM_HOST];
- tl_d2h_t tl_debugmem_h_d2h [N_DEBUGMEM_HOST];
-
- assign tl_debugmem_h_h2d[DebugMemFromCoreI] = tl_core_i_h2d[CoreIToDebugMem];
- assign tl_debugmem_h_h2d[DebugMemFromCoreD] = tl_core_d_h2d[CoreDToDebugMem];
-
- assign tl_core_i_d2h[CoreIToDebugMem] = tl_debugmem_h_d2h[DebugMemFromCoreI];
- assign tl_core_d_d2h[CoreDToDebugMem] = tl_debugmem_h_d2h[DebugMemFromCoreD];
-
- tlul_socket_m1 #(
- .M (N_DEBUGMEM_HOST),
- .HReqPass ({N_DEBUGMEM_HOST{1'b1}}), // unregistered
- .HRspPass ({N_DEBUGMEM_HOST{1'b1}}), // unregistered
- .HReqDepth ({N_DEBUGMEM_HOST{4'h1}}), // minimal elasticity
- .HRspDepth ({N_DEBUGMEM_HOST{4'h1}}), // minimal elasticity
- .DReqPass (1'b1), // unregistered
- .DRspPass (1'b1), // unregistered
- .DReqDepth (4'h1), // minimal elasticity
- .DRspDepth (4'h1) // minimal elasticity
- ) debugmem_socket_21 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .tl_h_i (tl_debugmem_h_h2d),
- .tl_h_o (tl_debugmem_h_d2h),
- .tl_d_o (tl_d_o[TlDebugMem]),
- .tl_d_i (tl_d_i[TlDebugMem])
- );
-
-
- // UART connects to Core D
- // TODO: Connect to SBA as well?
- assign tl_d_o[TlUart] = tl_core_d_h2d[CoreDToUart];
- assign tl_core_d_d2h[CoreDToUart] = tl_d_i[TlUart];
-
- // GPIO connects to Core D
- // TODO: Connect to SBA as well?
- assign tl_d_o[TlGpio] = tl_core_d_h2d[CoreDToGpio];
- assign tl_core_d_d2h[CoreDToGpio] = tl_d_i[TlGpio];
-
- // SPI Device
- assign tl_d_o[TlSpiDevice] = tl_core_d_h2d[CoreDToSpiDevice];
- assign tl_core_d_d2h[CoreDToSpiDevice] = tl_d_i[TlSpiDevice];
-endmodule
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
index 8e6f8a1..5df9b76 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
@@ -15,6 +15,11 @@
// UART interface
input IO_URX,
output IO_UTX,
+ // USB interface
+ inout IO_USB_DP0,
+ inout IO_USB_DN0,
+ input IO_USB_SENSE0,
+ output IO_USB_PULLUP0,
// GPIO x 16 interface
inout IO_GP0,
inout IO_GP1,
@@ -34,9 +39,12 @@
inout IO_GP15
);
- logic clk_sys, rst_sys_n;
- logic [31:0] cio_gpio_p2d, cio_gpio_d2p, cio_gpio_en_d2p;
+ logic clk_sys, clk_48mhz, rst_sys_n;
+ logic [31:0] cio_gpio_p2d, cio_gpio_d2p, cio_gpio_en_d2p;
logic cio_uart_rx_p2d, cio_uart_tx_d2p, cio_uart_tx_en_d2p;
+ logic cio_usbdev_sense_p2d, cio_usbdev_pullup_d2p, cio_usbdev_pullup_en_d2p;
+ logic cio_usbdev_dp_p2d, cio_usbdev_dp_d2p, cio_usbdev_dp_en_d2p;
+ logic cio_usbdev_dn_p2d, cio_usbdev_dn_d2p, cio_usbdev_dn_en_d2p;
// Unlike Nexys Video there is no separate JTAG controller, tie off for now
logic IO_JTCK = 0;
@@ -45,12 +53,13 @@
logic IO_JTRST_N = IO_RST_N;
logic IO_JTDO;
-
// Top-level design
top_earlgrey top_earlgrey (
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
+ .clk_usb_48mhz_i (clk_48mhz),
+
.jtag_tck_i (IO_JTCK),
.jtag_tms_i (IO_JTMS),
.jtag_trst_ni (IO_JTRST_N),
@@ -63,7 +72,19 @@
.mio_in_i (cio_gpio_p2d),
.mio_out_o (cio_gpio_d2p),
- .mio_oe_o (cio_gpio_en_d2p)
+ .mio_oe_o (cio_gpio_en_d2p),
+
+ .dio_usbdev_sense_i (cio_usbdev_sense_p2d),
+ .dio_usbdev_pullup_o (cio_usbdev_pullup_d2p),
+ .dio_usbdev_pullup_en_o (cio_usbdev_pullup_en_d2p),
+ .dio_usbdev_dp_i (cio_usbdev_dp_p2d),
+ .dio_usbdev_dp_o (cio_usbdev_dp_d2p),
+ .dio_usbdev_dp_en_o (cio_usbdev_dp_en_d2p),
+ .dio_usbdev_dn_i (cio_usbdev_dn_p2d),
+ .dio_usbdev_dn_o (cio_usbdev_dn_d2p),
+ .dio_usbdev_dn_en_o (cio_usbdev_dn_en_d2p),
+
+ .scanmode_i (1'b0) // 1 for Scan
);
// Clock and reset
@@ -71,6 +92,7 @@
.IO_CLK(IO_CLK),
.IO_RST_N(IO_RST_N),
.clk_sys(clk_sys),
+ .clk_48MHz(clk_48mhz),
.rst_sys_n(rst_sys_n)
);
@@ -80,6 +102,16 @@
.cio_uart_rx_p2d,
.cio_uart_tx_d2p,
.cio_uart_tx_en_d2p,
+ // USB
+ .cio_usbdev_sense_p2d(cio_usbdev_sense_p2d),
+ .cio_usbdev_pullup_d2p(cio_usbdev_pullup_d2p),
+ .cio_usbdev_pullup_en_d2p(cio_usbdev_pullup_en_d2p),
+ .cio_usbdev_dp_p2d(cio_usbdev_dp_p2d),
+ .cio_usbdev_dp_d2p(cio_usbdev_dp_d2p),
+ .cio_usbdev_dp_en_d2p(cio_usbdev_dp_en_d2p),
+ .cio_usbdev_dn_p2d(cio_usbdev_dn_p2d),
+ .cio_usbdev_dn_d2p(cio_usbdev_dn_d2p),
+ .cio_usbdev_dn_en_d2p(cio_usbdev_dn_en_d2p),
// GPIO
.cio_gpio_p2d,
.cio_gpio_d2p,
@@ -87,6 +119,10 @@
// pads
.IO_URX,
.IO_UTX,
+ .IO_USB_DP0,
+ .IO_USB_DN0,
+ .IO_USB_SENSE0,
+ .IO_USB_PULLUP0,
.IO_GP0,
.IO_GP1,
.IO_GP2,
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
index ecb488e..c1b268f 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
@@ -6,6 +6,7 @@
// Clock and Reset
input IO_CLK,
input IO_RST_N,
+ input IO_CLK_USB_48MHZ,
// JTAG interface
input IO_JTCK,
input IO_JTMS,
@@ -15,6 +16,11 @@
// UART interface
input IO_URX,
output IO_UTX,
+ // USB interface
+ inout IO_USB_DP0,
+ inout IO_USB_DN0,
+ input IO_USB_SENSE0,
+ output IO_USB_PULLUP0,
// GPIO x 16 interface
inout IO_GP0,
inout IO_GP1,
@@ -34,14 +40,19 @@
inout IO_GP15
);
- logic [31:0] cio_gpio_p2d, cio_gpio_d2p, cio_gpio_en_d2p;
+ logic [31:0] cio_gpio_p2d, cio_gpio_d2p, cio_gpio_en_d2p;
logic cio_uart_rx_p2d, cio_uart_tx_d2p, cio_uart_tx_en_d2p;
+ logic cio_usbdev_sense_p2d, cio_usbdev_pullup_d2p, cio_usbdev_pullup_en_d2p;
+ logic cio_usbdev_dp_p2d, cio_usbdev_dp_d2p, cio_usbdev_dp_en_d2p;
+ logic cio_usbdev_dn_p2d, cio_usbdev_dn_d2p, cio_usbdev_dn_en_d2p;
// Top-level design
top_earlgrey top_earlgrey (
.clk_i (IO_CLK),
.rst_ni (IO_RST_N),
+ .clk_usb_48mhz_i (IO_CLK_USB_48MHZ),
+
.jtag_tck_i (IO_JTCK),
.jtag_tms_i (IO_JTMS),
.jtag_trst_ni (IO_JTRST_N),
@@ -56,6 +67,15 @@
.dio_uart_rx_i (cio_uart_rx_p2d),
.dio_uart_tx_o (cio_uart_tx_d2p),
.dio_uart_tx_en_o (cio_uart_tx_en_d2p),
+ .dio_usbdev_sense_i (cio_usbdev_sense_p2d),
+ .dio_usbdev_pullup_o (cio_usbdev_pullup_d2p),
+ .dio_usbdev_pullup_en_o (cio_usbdev_pullup_en_d2p),
+ .dio_usbdev_dp_i (cio_usbdev_dp_p2d),
+ .dio_usbdev_dp_o (cio_usbdev_dp_d2p),
+ .dio_usbdev_dp_en_o (cio_usbdev_dp_en_d2p),
+ .dio_usbdev_dn_i (cio_usbdev_dn_p2d),
+ .dio_usbdev_dn_o (cio_usbdev_dn_d2p),
+ .dio_usbdev_dn_en_o (cio_usbdev_dn_en_d2p),
.mio_in_i (cio_gpio_p2d),
.mio_out_o (cio_gpio_d2p),
@@ -70,6 +90,16 @@
.cio_uart_rx_p2d,
.cio_uart_tx_d2p,
.cio_uart_tx_en_d2p,
+ // USB
+ .cio_usbdev_sense_p2d(cio_usbdev_sense_p2d),
+ .cio_usbdev_pullup_d2p(cio_usbdev_pullup_d2p),
+ .cio_usbdev_pullup_en_d2p(cio_usbdev_pullup_en_d2p),
+ .cio_usbdev_dp_p2d(cio_usbdev_dp_p2d),
+ .cio_usbdev_dp_d2p(cio_usbdev_dp_d2p),
+ .cio_usbdev_dp_en_d2p(cio_usbdev_dp_en_d2p),
+ .cio_usbdev_dn_p2d(cio_usbdev_dn_p2d),
+ .cio_usbdev_dn_d2p(cio_usbdev_dn_d2p),
+ .cio_usbdev_dn_en_d2p(cio_usbdev_dn_en_d2p),
// GPIO
.cio_gpio_p2d,
.cio_gpio_d2p,
@@ -77,6 +107,10 @@
// pads
.IO_URX,
.IO_UTX,
+ .IO_USB_DP0,
+ .IO_USB_DN0,
+ .IO_USB_SENSE0,
+ .IO_USB_PULLUP0,
.IO_GP0,
.IO_GP1,
.IO_GP2,
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
index 2791eb8..dc3df9c 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
@@ -18,6 +18,11 @@
// UART interface
input IO_URX,
output IO_UTX,
+ // USB interface
+ inout IO_USB_DP0,
+ inout IO_USB_DN0,
+ input IO_USB_SENSE0,
+ output IO_USB_PULLUP0,
// GPIO x 16 interface
inout IO_GP0,
inout IO_GP1,
@@ -37,13 +42,16 @@
inout IO_GP15
);
- logic clk_sys, rst_sys_n;
- logic [31:0] cio_gpio_p2d, cio_gpio_d2p, cio_gpio_en_d2p;
+ logic clk_sys, clk_48mhz, rst_sys_n;
+ logic [31:0] cio_gpio_p2d, cio_gpio_d2p, cio_gpio_en_d2p;
logic cio_uart_rx_p2d, cio_uart_tx_d2p, cio_uart_tx_en_d2p;
logic cio_spi_device_sck_p2d, cio_spi_device_csb_p2d, cio_spi_device_mosi_p2d,
cio_spi_device_miso_d2p, cio_spi_device_miso_en_d2p;
logic cio_jtag_tck_p2d, cio_jtag_tms_p2d, cio_jtag_tdi_p2d, cio_jtag_tdo_d2p;
logic cio_jtag_trst_n_p2d, cio_jtag_srst_n_p2d;
+ logic cio_usbdev_sense_p2d, cio_usbdev_pullup_d2p, cio_usbdev_pullup_en_d2p;
+ logic cio_usbdev_dp_p2d, cio_usbdev_dp_d2p, cio_usbdev_dp_en_d2p;
+ logic cio_usbdev_dn_p2d, cio_usbdev_dn_d2p, cio_usbdev_dn_en_d2p;
// Top-level design
top_earlgrey #(
@@ -52,6 +60,8 @@
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
+ .clk_usb_48mhz_i (clk_48mhz),
+
.jtag_tck_i (cio_jtag_tck_p2d),
.jtag_tms_i (cio_jtag_tms_p2d),
.jtag_trst_ni (cio_jtag_trst_n_p2d),
@@ -72,13 +82,24 @@
.dio_spi_device_miso_o (cio_spi_device_miso_d2p),
.dio_spi_device_miso_en_o (cio_spi_device_miso_en_d2p),
- .scanmode_i (1'b0) // 1 for Scan
+ .dio_usbdev_sense_i (cio_usbdev_sense_p2d),
+ .dio_usbdev_pullup_o (cio_usbdev_pullup_d2p),
+ .dio_usbdev_pullup_en_o (cio_usbdev_pullup_en_d2p),
+ .dio_usbdev_dp_i (cio_usbdev_dp_p2d),
+ .dio_usbdev_dp_o (cio_usbdev_dp_d2p),
+ .dio_usbdev_dp_en_o (cio_usbdev_dp_en_d2p),
+ .dio_usbdev_dn_i (cio_usbdev_dn_p2d),
+ .dio_usbdev_dn_o (cio_usbdev_dn_d2p),
+ .dio_usbdev_dn_en_o (cio_usbdev_dn_en_d2p),
+
+ .scanmode_i (1'b0) // 1 for Scan
);
clkgen_xil7series clkgen (
.IO_CLK(IO_CLK),
.IO_RST_N(IO_RST_N & cio_jtag_srst_n_p2d),
.clk_sys(clk_sys),
+ .clk_48MHz(clk_48mhz),
.rst_sys_n(rst_sys_n)
);
@@ -88,6 +109,16 @@
.cio_uart_rx_p2d,
.cio_uart_tx_d2p,
.cio_uart_tx_en_d2p,
+ // USB
+ .cio_usbdev_sense_p2d(cio_usbdev_sense_p2d),
+ .cio_usbdev_pullup_d2p(cio_usbdev_pullup_d2p),
+ .cio_usbdev_pullup_en_d2p(cio_usbdev_pullup_en_d2p),
+ .cio_usbdev_dp_p2d(cio_usbdev_dp_p2d),
+ .cio_usbdev_dp_d2p(cio_usbdev_dp_d2p),
+ .cio_usbdev_dp_en_d2p(cio_usbdev_dp_en_d2p),
+ .cio_usbdev_dn_p2d(cio_usbdev_dn_p2d),
+ .cio_usbdev_dn_d2p(cio_usbdev_dn_d2p),
+ .cio_usbdev_dn_en_d2p(cio_usbdev_dn_en_d2p),
// GPIO
.cio_gpio_p2d,
.cio_gpio_d2p,
@@ -95,6 +126,10 @@
// pads
.IO_URX,
.IO_UTX,
+ .IO_USB_DP0,
+ .IO_USB_DN0,
+ .IO_USB_SENSE0,
+ .IO_USB_PULLUP0,
.IO_GP0,
.IO_GP1,
.IO_GP2,
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_usb.sv b/hw/top_earlgrey/rtl/top_earlgrey_usb.sv
deleted file mode 100644
index 1d5f264..0000000
--- a/hw/top_earlgrey/rtl/top_earlgrey_usb.sv
+++ /dev/null
@@ -1,863 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-module top_earlgrey_usb #(
- parameter bit IbexPipeLine = 0,
- parameter N_USB = 1,
- parameter MAX_USB = 2,
- parameter USB_UART = 1,
- parameter USB_DEVICE = 0
-) (
- // Clock and Reset
- input clk_i,
- input rst_ni,
-
- // JTAG interface
- input jtag_tck_i,
- input jtag_tms_i,
- input jtag_trst_ni,
- input jtag_td_i,
- output jtag_td_o,
-
- // USB interface
- input clk_48mhz_i,
- input dio_usb_dp_i[MAX_USB],
- output logic dio_usb_dp_o[MAX_USB],
- output logic dio_usb_dp_en_o[MAX_USB],
-
- input dio_usb_dn_i[MAX_USB],
- output logic dio_usb_dn_o[MAX_USB],
- output logic dio_usb_dn_en_o[MAX_USB],
-
- input dio_usb_sense_i[MAX_USB],
-
- output logic dio_usb_pullup_o[MAX_USB],
- output logic dio_usb_pullup_en_o[MAX_USB],
-
- // Multiplexed I/O
- input [31:0] mio_in_i,
- output logic [31:0] mio_out_o,
- output logic [31:0] mio_oe_o,
-
- // Dedicated I/O
- input dio_spi_device_sck_i,
- input dio_spi_device_csb_i,
- input dio_spi_device_mosi_i,
- output logic dio_spi_device_miso_o,
- output logic dio_spi_device_miso_en_o,
- input dio_uart_rx_i,
- output logic dio_uart_tx_o,
- output logic dio_uart_tx_en_o,
-
- input scanmode_i // 1 for Scan
-);
-
- // JTAG IDCODE for development versions of this code.
- // Manufacturers of OpenTitan chips must replace this code with one of their
- // own IDs.
- // Field structure as defined in the IEEE 1149.1 (JTAG) specification,
- // section 12.1.1.
- localparam JTAG_IDCODE = {
- 4'h0, // Version
- 16'h4F54, // Part Number: "OT"
- 11'h426, // Manufacturer Identity: Google
- 1'b1 // (fixed)
- };
-
- import tlul_pkg::*;
- import top_pkg::*;
- import tl_main_pkg::*;
- import flash_ctrl_pkg::*;
-
- tl_h2d_t tl_corei_h_h2d;
- tl_d2h_t tl_corei_h_d2h;
-
- tl_h2d_t tl_cored_h_h2d;
- tl_d2h_t tl_cored_h_d2h;
-
- tl_h2d_t tl_dm_sba_h_h2d;
- tl_d2h_t tl_dm_sba_h_d2h;
-
- tl_h2d_t tl_debug_mem_d_h2d;
- tl_d2h_t tl_debug_mem_d_d2h;
-
- tl_h2d_t tl_uart_d_h2d;
- tl_d2h_t tl_uart_d_d2h;
- tl_h2d_t tl_gpio_d_h2d;
- tl_d2h_t tl_gpio_d_d2h;
- tl_h2d_t tl_spi_device_d_h2d;
- tl_d2h_t tl_spi_device_d_d2h;
- tl_h2d_t tl_flash_ctrl_d_h2d;
- tl_d2h_t tl_flash_ctrl_d_d2h;
- tl_h2d_t tl_rv_timer_d_h2d;
- tl_d2h_t tl_rv_timer_d_d2h;
- tl_h2d_t tl_aes_d_h2d;
- tl_d2h_t tl_aes_d_d2h;
- tl_h2d_t tl_hmac_d_h2d;
- tl_d2h_t tl_hmac_d_d2h;
- tl_h2d_t tl_rv_plic_d_h2d;
- tl_d2h_t tl_rv_plic_d_d2h;
- tl_h2d_t tl_pinmux_d_h2d;
- tl_d2h_t tl_pinmux_d_d2h;
- tl_h2d_t tl_alert_handler_d_h2d;
- tl_d2h_t tl_alert_handler_d_d2h;
- tl_h2d_t tl_nmi_gen_d_h2d;
- tl_d2h_t tl_nmi_gen_d_d2h;
-
- tl_h2d_t tl_rom_d_h2d;
- tl_d2h_t tl_rom_d_d2h;
- tl_h2d_t tl_ram_main_d_h2d;
- tl_d2h_t tl_ram_main_d_d2h;
- tl_h2d_t tl_eflash_d_h2d;
- tl_d2h_t tl_eflash_d_d2h;
-
- tl_h2d_t tl_main_h_h2d;
- tl_d2h_t tl_main_h_d2h;
- tl_h2d_t tl_peri_d_h2d;
- tl_d2h_t tl_peri_d_d2h;
-
- assign tl_main_h_h2d = tl_peri_d_h2d;
- assign tl_peri_d_d2h = tl_main_h_d2h;
-
- //reset wires declaration
- logic lc_rst_n;
- logic sys_rst_n;
- logic sys_fixed_rst_n;
- logic spi_device_rst_n;
-
- //clock wires declaration
- logic main_clk;
- logic fixed_clk;
-
- // Signals
- logic [31:0] m2p;
- logic [31:0] p2m;
- logic [31:0] p2m_en;
- // uart
- logic cio_uart_rx_p2d;
- logic cio_uart_tx_d2p;
- logic cio_uart_tx_en_d2p;
- // gpio
- logic [31:0] cio_gpio_gpio_p2d;
- logic [31:0] cio_gpio_gpio_d2p;
- logic [31:0] cio_gpio_gpio_en_d2p;
- // spi_device
- logic cio_spi_device_sck_p2d;
- logic cio_spi_device_csb_p2d;
- logic cio_spi_device_mosi_p2d;
- logic cio_spi_device_miso_d2p;
- logic cio_spi_device_miso_en_d2p;
- // flash_ctrl
- // rv_timer
- // aes
- // hmac
- // rv_plic
- // pinmux
- // alert_handler
- // nmi_gen
-
-
- logic [62:0] intr_vector;
- // Interrupt source list
- logic intr_uart_tx_watermark;
- logic intr_uart_rx_watermark;
- logic intr_uart_tx_empty;
- logic intr_uart_rx_overflow;
- logic intr_uart_rx_frame_err;
- logic intr_uart_rx_break_err;
- logic intr_uart_rx_timeout;
- logic intr_uart_rx_parity_err;
- logic [31:0] intr_gpio_gpio;
- logic intr_spi_device_rxf;
- logic intr_spi_device_rxlvl;
- logic intr_spi_device_txlvl;
- logic intr_spi_device_rxerr;
- logic intr_spi_device_rxoverflow;
- logic intr_spi_device_txunderflow;
- logic intr_flash_ctrl_prog_empty;
- logic intr_flash_ctrl_prog_lvl;
- logic intr_flash_ctrl_rd_full;
- logic intr_flash_ctrl_rd_lvl;
- logic intr_flash_ctrl_op_done;
- logic intr_flash_ctrl_op_error;
- logic intr_rv_timer_timer_expired_0_0;
- logic intr_hmac_hmac_done;
- logic intr_hmac_fifo_full;
- logic intr_hmac_hmac_err;
- logic intr_alert_handler_classa;
- logic intr_alert_handler_classb;
- logic intr_alert_handler_classc;
- logic intr_alert_handler_classd;
- logic intr_nmi_gen_esc0;
- logic intr_nmi_gen_esc1;
- logic intr_nmi_gen_esc2;
- logic intr_nmi_gen_esc3;
-
-
- logic [0:0] irq_plic;
- logic [0:0] msip;
- logic [5:0] irq_id[1];
- logic [5:0] unused_irq_id[1];
-
- // this avoids lint errors
- assign unused_irq_id = irq_id;
-
- // Alert list
- prim_pkg::alert_tx_t [alert_pkg::NAlerts-1:0] alert_tx;
- prim_pkg::alert_rx_t [alert_pkg::NAlerts-1:0] alert_rx;
- // Escalation outputs
- prim_pkg::esc_tx_t [alert_pkg::N_ESC_SEV-1:0] esc_tx;
- prim_pkg::esc_rx_t [alert_pkg::N_ESC_SEV-1:0] esc_rx;
-
- // clock assignments
- assign main_clk = clk_i;
- assign fixed_clk = clk_i;
-
- // Non-debug module reset == reset for everything except for the debug module
- logic ndmreset_req;
-
- // root resets
- // TODO: lc_rst_n is not the true root reset. It will be differentiated once the
- // the reset controller logic is present
- assign lc_rst_n = rst_ni;
- assign sys_rst_n = (scanmode_i) ? lc_rst_n : ~ndmreset_req & lc_rst_n;
-
- //non-root reset assignments
- assign sys_fixed_rst_n = sys_rst_n;
- assign spi_device_rst_n = sys_rst_n;
-
- // debug request from rv_dm to core
- logic debug_req;
-
- // processor core
- rv_core_ibex #(
- .PMPEnable (0),
- .PMPGranularity (0),
- .PMPNumRegions (4),
- .MHPMCounterNum (8),
- .MHPMCounterWidth (40),
- .RV32E (0),
- .RV32M (1),
- .DmHaltAddr (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress),
- .DmExceptionAddr (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress),
- .PipeLine (IbexPipeLine)
- ) core (
- // clock and reset
- .clk_i (main_clk),
- .rst_ni (sys_rst_n),
- .test_en_i (1'b0),
- // static pinning
- .hart_id_i (32'b0),
- .boot_addr_i (ADDR_SPACE_ROM),
- // TL-UL buses
- .tl_i_o (tl_corei_h_h2d),
- .tl_i_i (tl_corei_h_d2h),
- .tl_d_o (tl_cored_h_h2d),
- .tl_d_i (tl_cored_h_d2h),
- // interrupts
- .irq_software_i (msip),
- .irq_timer_i (intr_rv_timer_timer_expired_0_0),
- .irq_external_i (irq_plic),
- .irq_fast_i (15'b0),// PLIC handles all peripheral interrupts
- .irq_nm_i (1'b0),// TODO - add and connect alert responder
- // debug interface
- .debug_req_i (debug_req),
- // CPU control signals
- .fetch_enable_i (1'b1),
- .core_sleep_o ()
- );
-
- // Debug Module (RISC-V Debug Spec 0.13)
- //
-
- rv_dm #(
- .NrHarts (1),
- .IdcodeValue (JTAG_IDCODE)
- ) u_dm_top (
- .clk_i (main_clk),
- .rst_ni (lc_rst_n),
- .testmode_i (1'b0),
- .ndmreset_o (ndmreset_req),
- .dmactive_o (),
- .debug_req_o (debug_req),
- .unavailable_i (1'b0),
-
- // bus device with debug memory (for execution-based debug)
- .tl_d_i (tl_debug_mem_d_h2d),
- .tl_d_o (tl_debug_mem_d_d2h),
-
- // bus host (for system bus accesses, SBA)
- .tl_h_o (tl_dm_sba_h_h2d),
- .tl_h_i (tl_dm_sba_h_d2h),
-
- //JTAG
- .tck_i (jtag_tck_i),
- .tms_i (jtag_tms_i),
- .trst_ni (jtag_trst_ni),
- .td_i (jtag_td_i),
- .td_o (jtag_td_o),
- .tdo_oe_o ( )
- );
-
- // ROM device
- logic rom_req;
- logic [10:0] rom_addr;
- logic [31:0] rom_rdata;
- logic rom_rvalid;
-
- tlul_adapter_sram #(
- .SramAw(11),
- .SramDw(32),
- .Outstanding(1),
- .ErrOnWrite(1)
- ) tl_adapter_rom (
- .clk_i (main_clk),
- .rst_ni (sys_rst_n),
-
- .tl_i (tl_rom_d_h2d),
- .tl_o (tl_rom_d_d2h),
-
- .req_o (rom_req),
- .gnt_i (1'b1), // Always grant as only one requester exists
- .we_o (),
- .addr_o (rom_addr),
- .wdata_o (),
- .wmask_o (),
- .rdata_i (rom_rdata),
- .rvalid_i (rom_rvalid),
- .rerror_i (2'b00)
- );
-
- prim_rom #(
- .Width(32),
- .Depth(2048)
- ) u_rom_rom (
- .clk_i (main_clk),
- .rst_ni (sys_rst_n),
- .cs_i (rom_req),
- .addr_i (rom_addr),
- .dout_o (rom_rdata),
- .dvalid_o (rom_rvalid)
- );
-
- // sram device
- logic ram_main_req;
- logic ram_main_we;
- logic [13:0] ram_main_addr;
- logic [31:0] ram_main_wdata;
- logic [31:0] ram_main_wmask;
- logic [31:0] ram_main_rdata;
- logic ram_main_rvalid;
-
- tlul_adapter_sram #(
- .SramAw(14),
- .SramDw(32),
- .Outstanding(1)
- ) tl_adapter_ram_main (
- .clk_i (main_clk),
- .rst_ni (sys_rst_n),
- .tl_i (tl_ram_main_d_h2d),
- .tl_o (tl_ram_main_d_d2h),
-
- .req_o (ram_main_req),
- .gnt_i (1'b1), // Always grant as only one requester exists
- .we_o (ram_main_we),
- .addr_o (ram_main_addr),
- .wdata_o (ram_main_wdata),
- .wmask_o (ram_main_wmask),
- .rdata_i (ram_main_rdata),
- .rvalid_i (ram_main_rvalid),
- .rerror_i (2'b00)
- );
-
- prim_ram_1p #(
- .Width(32),
- .Depth(16384),
- .DataBitsPerMask(8)
- ) u_ram1p_ram_main (
- .clk_i (main_clk),
- .rst_ni (sys_rst_n),
-
- .req_i (ram_main_req),
- .write_i (ram_main_we),
- .addr_i (ram_main_addr),
- .wdata_i (ram_main_wdata),
- .wmask_i (ram_main_wmask),
- .rvalid_o (ram_main_rvalid),
- .rdata_o (ram_main_rdata)
- );
-
- // flash controller to eflash communication
- flash_c2m_t flash_c2m;
- flash_m2c_t flash_m2c;
-
- // host to flash communication
- logic flash_host_req;
- logic flash_host_req_rdy;
- logic flash_host_req_done;
- logic [FLASH_DW-1:0] flash_host_rdata;
- logic [FLASH_AW-1:0] flash_host_addr;
-
- tlul_adapter_sram #(
- .SramAw(FLASH_AW),
- .SramDw(FLASH_DW),
- .Outstanding(1),
- .ByteAccess(0),
- .ErrOnWrite(1)
- ) tl_adapter_eflash (
- .clk_i (main_clk),
- .rst_ni (lc_rst_n),
-
- .tl_i (tl_eflash_d_h2d),
- .tl_o (tl_eflash_d_d2h),
-
- .req_o (flash_host_req),
- .gnt_i (flash_host_req_rdy),
- .we_o (),
- .addr_o (flash_host_addr),
- .wdata_o (),
- .wmask_o (),
- .rdata_i (flash_host_rdata),
- .rvalid_i (flash_host_req_done),
- .rerror_i (2'b00)
- );
-
- flash_phy #(
- .NumBanks(FLASH_BANKS),
- .PagesPerBank(FLASH_PAGES_PER_BANK),
- .WordsPerPage(FLASH_WORDS_PER_PAGE),
- .DataWidth(32)
- ) u_flash_eflash (
- .clk_i (main_clk),
- .rst_ni (lc_rst_n),
- .host_req_i (flash_host_req),
- .host_addr_i (flash_host_addr),
- .host_req_rdy_o (flash_host_req_rdy),
- .host_req_done_o (flash_host_req_done),
- .host_rdata_o (flash_host_rdata),
- .flash_ctrl_i (flash_c2m),
- .flash_ctrl_o (flash_m2c)
- );
-
-
- if (USB_UART == 0) begin : gen_uart
- uart uart (
- .tl_i (tl_uart_d_h2d),
- .tl_o (tl_uart_d_d2h),
-
- // Input
- .cio_rx_i (cio_uart_rx_p2d),
-
- // Output
- .cio_tx_o (cio_uart_tx_d2p),
- .cio_tx_en_o (cio_uart_tx_en_d2p),
-
- // Interrupt
- .intr_tx_watermark_o (intr_uart_tx_watermark),
- .intr_rx_watermark_o (intr_uart_rx_watermark),
- .intr_tx_empty_o (intr_uart_tx_empty),
- .intr_rx_overflow_o (intr_uart_rx_overflow),
- .intr_rx_frame_err_o (intr_uart_rx_frame_err),
- .intr_rx_break_err_o (intr_uart_rx_break_err),
- .intr_rx_timeout_o (intr_uart_rx_timeout),
- .intr_rx_parity_err_o (intr_uart_rx_parity_err),
-
- .clk_i (fixed_clk),
- .rst_ni (sys_fixed_rst_n)
- );
- end else begin : gen_uuart
- logic unused_rx = cio_uart_rx_p2d;
- assign cio_uart_tx_d2p_o = 0;
- assign cio_uart_tx_en_d2p_o = 0;
-
- usbuart uart (
- .clk_i (clk_i),
- .clk_48mhz_i (clk_48mhz_i),
- .rst_ni (sys_rst_n),
- .rst_usb_ni (sys_rst_n),
- .tl_i (tl_uart_d_h2d),
- .tl_o (tl_uart_d_d2h),
- .cio_usb_dp_i (dio_usb_dp_i[USB_UART - 1]),
- .cio_usb_dp_o (dio_usb_dp_o[USB_UART - 1]),
- .cio_usb_dp_en_o (dio_usb_dp_en_o[USB_UART - 1]),
- .cio_usb_dn_i (dio_usb_dn_i[USB_UART - 1]),
- .cio_usb_dn_o (dio_usb_dn_o[USB_UART - 1]),
- .cio_usb_dn_en_o (dio_usb_dn_en_o[USB_UART - 1]),
- .cio_usb_sense_i (dio_usb_sense_i[USB_UART - 1]),
- .cio_pullup_o (dio_usb_pullup_o[USB_UART - 1]),
- .cio_pullup_en_o (dio_usb_pullup_en_o[USB_UART - 1]),
-
- .intr_tx_watermark_o (intr_uart_tx_watermark),
- .intr_rx_watermark_o (intr_uart_rx_watermark),
- .intr_tx_overflow_o (intr_uart_tx_empty),
- .intr_rx_overflow_o (intr_uart_rx_overflow),
- .intr_rx_frame_err_o (intr_uart_rx_frame_err),
- .intr_rx_break_err_o (intr_uart_rx_break_err),
- .intr_rx_timeout_o (intr_uart_rx_timeout),
- .intr_rx_parity_err_o (intr_uart_rx_parity_err)
- );
- end // block: gen_uuart
-
- gpio gpio (
- .tl_i (tl_gpio_d_h2d),
- .tl_o (tl_gpio_d_d2h),
-
- // Input
- .cio_gpio_i (cio_gpio_gpio_p2d),
-
- // Output
- .cio_gpio_o (cio_gpio_gpio_d2p),
- .cio_gpio_en_o (cio_gpio_gpio_en_d2p),
-
- // Interrupt
- .intr_gpio_o (intr_gpio_gpio),
-
- .clk_i (fixed_clk),
- .rst_ni (sys_fixed_rst_n)
- );
-
- if (USB_DEVICE == 0) begin : gen_spi
- spi_device spi_device (
- .tl_i (tl_spi_device_d_h2d),
- .tl_o (tl_spi_device_d_d2h),
-
- // Input
- .cio_sck_i (cio_spi_device_sck_p2d),
- .cio_csb_i (cio_spi_device_csb_p2d),
- .cio_mosi_i (cio_spi_device_mosi_p2d),
-
- // Output
- .cio_miso_o (cio_spi_device_miso_d2p),
- .cio_miso_en_o (cio_spi_device_miso_en_d2p),
-
- // Interrupt
- .intr_rxf_o (intr_spi_device_rxf),
- .intr_rxlvl_o (intr_spi_device_rxlvl),
- .intr_txlvl_o (intr_spi_device_txlvl),
- .intr_rxerr_o (intr_spi_device_rxerr),
- .intr_rxoverflow_o (intr_spi_device_rxoverflow),
- .intr_txunderflow_o (intr_spi_device_txunderflow),
-
- .scanmode_i (scanmode_i),
-
- .clk_i (fixed_clk),
- .rst_ni (spi_device_rst_n)
- );
- end else begin : gen_usbdev // block: gen_spi
- logic unused_sck = cio_spi_device_sck_p2d;
- logic unused_csb = cio_spi_device_csb_p2d;
- logic unused_mosi = cio_spi_device_mosi_p2d;
- logic usbdev_usb_oe;
- logic usbdev_usb_pullup_en;
-
- assign intr_spi_device_rxlvl = 0;
- assign intr_spi_device_txf = 0;
- assign cio_spi_device_miso_o = 0;
- assign cio_spi_device_miso_en_o = 0;
-
- usbdev udev (
- .clk_i (clk_i),
- .clk_usb_48mhz_i (clk_48mhz_i),
- .rst_ni (spi_device_rst_n),
- .rst_usb_ni (spi_device_rst_n), // TODO: Need a real USB reset here
- .tl_i (tl_spi_device_d_h2d),
- .tl_o (tl_spi_device_d_d2h),
-
- .cio_usb_d_i (1'b0),
- .cio_usb_dp_i (dio_usb_dp_i[USB_DEVICE - 1]),
- .cio_usb_dn_i (dio_usb_dn_i[USB_DEVICE - 1]),
-
- .cio_usb_d_o (),
- .cio_usb_se0_o (),
- .cio_usb_dp_o (dio_usb_dp_o[USB_DEVICE - 1]),
- .cio_usb_dn_o (dio_usb_dn_o[USB_DEVICE - 1]),
- .cio_usb_oe_o (usbdev_usb_oe),
-
- .cio_usb_tx_mode_se_o (),
- .cio_usb_sense_i (dio_usb_sense_i[USB_DEVICE - 1]),
- .cio_usb_pullup_en_o (usbdev_usb_pullup_en),
- .cio_usb_suspend_o (),
-
- .intr_pkt_received_o (intr_spi_device_rxf),
- .intr_pkt_sent_o (intr_spi_device_txlvl),
- .intr_disconnected_o (),
- .intr_connected_o (),
- .intr_host_lost_o (),
- .intr_link_reset_o (),
- .intr_link_suspend_o (),
- .intr_link_resume_o (),
- .intr_av_empty_o (intr_spi_device_rxlvl),
- .intr_rx_full_o (intr_spi_device_rxerr),
- .intr_av_overflow_o (intr_spi_device_txunderflow),
- .intr_link_in_err_o (),
- .intr_rx_crc_err_o (),
- .intr_rx_pid_err_o (),
- .intr_rx_bitstuff_err_o (),
- .intr_frame_o ()
- );
-
- assign dio_usb_dp_en_o[USB_DEVICE - 1] = usbdev_usb_oe;
- assign dio_usb_dn_en_o[USB_DEVICE - 1] = usbdev_usb_oe;
-
- // Enable -- This is working but should these be swapped so there is no active pull down?
- assign dio_usb_pullup_o[USB_DEVICE - 1] = usbdev_usb_pullup_en;
- assign dio_usb_pullup_en_o[USB_DEVICE - 1] = 1'b1;
-
- end // block: gen_usbdev
-
- // Tie off unused USB
- if (N_USB < MAX_USB) begin: gen_utie
- for (genvar j = N_USB; j < MAX_USB; j = j + 1) begin
- logic unused_usb;
- assign unused_usb = dio_usb_dp_i[j] | dio_usb_dn_i[j] | dio_usb_sense_i[j];
- assign dio_usb_dp_o[j] = 1'b0;
- assign dio_usb_dp_en_o[j] = 1'b0;
- assign dio_usb_dn_o[j] = 1'b0;
- assign dio_usb_dn_en_o[j] = 1'b0;
- assign dio_usb_pullup_o[j] = 1'b0;
- assign dio_usb_pullup_en_o[j] = 1'b0;
- end
- end // block: gen_utie
-
- flash_ctrl flash_ctrl (
- .tl_i (tl_flash_ctrl_d_h2d),
- .tl_o (tl_flash_ctrl_d_d2h),
-
- // Interrupt
- .intr_prog_empty_o (intr_flash_ctrl_prog_empty),
- .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl),
- .intr_rd_full_o (intr_flash_ctrl_rd_full),
- .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
- .intr_op_done_o (intr_flash_ctrl_op_done),
- .intr_op_error_o (intr_flash_ctrl_op_error),
-
- .flash_o(flash_c2m),
- .flash_i(flash_m2c),
-
- .clk_i (main_clk),
- .rst_ni (lc_rst_n)
- );
-
- rv_timer rv_timer (
- .tl_i (tl_rv_timer_d_h2d),
- .tl_o (tl_rv_timer_d_d2h),
-
- // Interrupt
- .intr_timer_expired_0_0_o (intr_rv_timer_timer_expired_0_0),
-
- .clk_i (fixed_clk),
- .rst_ni (sys_fixed_rst_n)
- );
-
- aes aes (
- .tl_i (tl_aes_d_h2d),
- .tl_o (tl_aes_d_d2h),
-
- .clk_i (main_clk),
- .rst_ni (sys_rst_n)
- );
-
- hmac hmac (
- .tl_i (tl_hmac_d_h2d),
- .tl_o (tl_hmac_d_d2h),
-
- // Interrupt
- .intr_hmac_done_o (intr_hmac_hmac_done),
- .intr_fifo_full_o (intr_hmac_fifo_full),
- .intr_hmac_err_o (intr_hmac_hmac_err),
-
- // [0]: msg_push_sha_disabled
- .alert_tx_o ( alert_tx[0:0] ),
- .alert_rx_i ( alert_rx[0:0] ),
-
- .clk_i (main_clk),
- .rst_ni (sys_rst_n)
- );
-
- rv_plic rv_plic (
- .tl_i (tl_rv_plic_d_h2d),
- .tl_o (tl_rv_plic_d_d2h),
-
- .intr_src_i (intr_vector),
- .irq_o (irq_plic),
- .irq_id_o (irq_id),
- .msip_o (msip),
-
- .clk_i (main_clk),
- .rst_ni (sys_rst_n)
- );
-
- pinmux pinmux (
- .tl_i (tl_pinmux_d_h2d),
- .tl_o (tl_pinmux_d_d2h),
-
- .periph_to_mio_i (p2m ),
- .periph_to_mio_oe_i (p2m_en ),
- .mio_to_periph_o (m2p ),
-
- .mio_out_o (mio_out_o),
- .mio_oe_o (mio_oe_o ),
- .mio_in_i (mio_in_i ),
-
- .clk_i (main_clk),
- .rst_ni (sys_rst_n)
- );
-
- alert_handler alert_handler (
- .tl_i (tl_alert_handler_d_h2d),
- .tl_o (tl_alert_handler_d_d2h),
-
- // Interrupt
- .intr_classa_o (intr_alert_handler_classa),
- .intr_classb_o (intr_alert_handler_classb),
- .intr_classc_o (intr_alert_handler_classc),
- .intr_classd_o (intr_alert_handler_classd),
- // TODO: wire this to hardware debug circuit
- .crashdump_o ( ),
- // TODO: wire this to TRNG
- .entropy_i ( 1'b0 ),
- // alert signals
- .alert_rx_o ( alert_rx ),
- .alert_tx_i ( alert_tx ),
- // escalation outputs
- .esc_rx_i ( esc_rx ),
- .esc_tx_o ( esc_tx ),
-
- .clk_i (main_clk),
- .rst_ni (sys_rst_n)
- );
-
- nmi_gen nmi_gen (
- .tl_i (tl_nmi_gen_d_h2d),
- .tl_o (tl_nmi_gen_d_d2h),
-
- // Interrupt
- .intr_esc0_o (intr_nmi_gen_esc0),
- .intr_esc1_o (intr_nmi_gen_esc1),
- .intr_esc2_o (intr_nmi_gen_esc2),
- .intr_esc3_o (intr_nmi_gen_esc3),
- // escalation signal inputs
- .esc_rx_o ( esc_rx ),
- .esc_tx_i ( esc_tx ),
-
- .clk_i (main_clk),
- .rst_ni (sys_rst_n)
- );
-
- // interrupt assignments
- assign intr_vector = {
- intr_nmi_gen_esc3,
- intr_nmi_gen_esc2,
- intr_nmi_gen_esc1,
- intr_nmi_gen_esc0,
- intr_alert_handler_classd,
- intr_alert_handler_classc,
- intr_alert_handler_classb,
- intr_alert_handler_classa,
- intr_hmac_hmac_err,
- intr_hmac_fifo_full,
- intr_hmac_hmac_done,
- intr_flash_ctrl_op_error,
- intr_flash_ctrl_op_done,
- intr_flash_ctrl_rd_lvl,
- intr_flash_ctrl_rd_full,
- intr_flash_ctrl_prog_lvl,
- intr_flash_ctrl_prog_empty,
- intr_spi_device_txunderflow,
- intr_spi_device_rxoverflow,
- intr_spi_device_rxerr,
- intr_spi_device_txlvl,
- intr_spi_device_rxlvl,
- intr_spi_device_rxf,
- intr_uart_rx_parity_err,
- intr_uart_rx_timeout,
- intr_uart_rx_break_err,
- intr_uart_rx_frame_err,
- intr_uart_rx_overflow,
- intr_uart_tx_empty,
- intr_uart_rx_watermark,
- intr_uart_tx_watermark,
- intr_gpio_gpio
- };
-
- // TL-UL Crossbar
- xbar_main u_xbar_main (
- .clk_main_i (main_clk),
- .clk_fixed_i (fixed_clk),
- .rst_main_ni (sys_rst_n),
- .rst_fixed_ni (sys_fixed_rst_n),
- .tl_corei_i (tl_corei_h_h2d),
- .tl_corei_o (tl_corei_h_d2h),
- .tl_cored_i (tl_cored_h_h2d),
- .tl_cored_o (tl_cored_h_d2h),
- .tl_dm_sba_i (tl_dm_sba_h_h2d),
- .tl_dm_sba_o (tl_dm_sba_h_d2h),
- .tl_rom_o (tl_rom_d_h2d),
- .tl_rom_i (tl_rom_d_d2h),
- .tl_debug_mem_o (tl_debug_mem_d_h2d),
- .tl_debug_mem_i (tl_debug_mem_d_d2h),
- .tl_ram_main_o (tl_ram_main_d_h2d),
- .tl_ram_main_i (tl_ram_main_d_d2h),
- .tl_eflash_o (tl_eflash_d_h2d),
- .tl_eflash_i (tl_eflash_d_d2h),
- .tl_peri_o (tl_peri_d_h2d),
- .tl_peri_i (tl_peri_d_d2h),
- .tl_flash_ctrl_o (tl_flash_ctrl_d_h2d),
- .tl_flash_ctrl_i (tl_flash_ctrl_d_d2h),
- .tl_hmac_o (tl_hmac_d_h2d),
- .tl_hmac_i (tl_hmac_d_d2h),
- .tl_aes_o (tl_aes_d_h2d),
- .tl_aes_i (tl_aes_d_d2h),
- .tl_rv_plic_o (tl_rv_plic_d_h2d),
- .tl_rv_plic_i (tl_rv_plic_d_d2h),
- .tl_pinmux_o (tl_pinmux_d_h2d),
- .tl_pinmux_i (tl_pinmux_d_d2h),
- .tl_alert_handler_o (tl_alert_handler_d_h2d),
- .tl_alert_handler_i (tl_alert_handler_d_d2h),
- .tl_nmi_gen_o (tl_nmi_gen_d_h2d),
- .tl_nmi_gen_i (tl_nmi_gen_d_d2h),
-
- .scanmode_i
- );
- xbar_peri u_xbar_peri (
- .clk_peri_i (fixed_clk),
- .rst_peri_ni (sys_fixed_rst_n),
- .tl_main_i (tl_main_h_h2d),
- .tl_main_o (tl_main_h_d2h),
- .tl_uart_o (tl_uart_d_h2d),
- .tl_uart_i (tl_uart_d_d2h),
- .tl_gpio_o (tl_gpio_d_h2d),
- .tl_gpio_i (tl_gpio_d_d2h),
- .tl_spi_device_o (tl_spi_device_d_h2d),
- .tl_spi_device_i (tl_spi_device_d_d2h),
- .tl_rv_timer_o (tl_rv_timer_d_h2d),
- .tl_rv_timer_i (tl_rv_timer_d_d2h),
-
- .scanmode_i
- );
-
- // Pinmux connections
- assign p2m = {
- cio_gpio_gpio_d2p
- };
- assign p2m_en = {
- cio_gpio_gpio_en_d2p
- };
- assign {
- cio_gpio_gpio_p2d
- } = m2p;
-
- assign cio_spi_device_sck_p2d = dio_spi_device_sck_i;
- assign cio_spi_device_csb_p2d = dio_spi_device_csb_i;
- assign cio_spi_device_mosi_p2d = dio_spi_device_mosi_i;
- assign dio_spi_device_miso_o = cio_spi_device_miso_d2p;
- assign dio_spi_device_miso_en_o = cio_spi_device_miso_en_d2p;
- assign cio_uart_rx_p2d = dio_uart_rx_i;
- assign dio_uart_tx_o = cio_uart_tx_d2p;
- assign dio_uart_tx_en_o = cio_uart_tx_en_d2p;
-
- // make sure scanmode_i is never X (including during reset)
- `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0)
-
-endmodule
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_usb_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_usb_nexysvideo.sv
deleted file mode 100644
index 00d76f6..0000000
--- a/hw/top_earlgrey/rtl/top_earlgrey_usb_nexysvideo.sv
+++ /dev/null
@@ -1,183 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-module top_earlgrey_usb_nexysvideo (
- // Clock and Reset
- input IO_CLK,
- input IO_RST_N,
- // JTAG interface
- input IO_DPS0, // IO_JTCK, IO_SDCK
- input IO_DPS3, // IO_JTMS, IO_SDCSB
- input IO_DPS1, // IO_JTDI, IO_SDMOSI
- input IO_DPS4, // IO_JTRST_N,
- input IO_DPS5, // IO_JSRST_N,
- output IO_DPS2, // IO_JTDO, IO_MISO
- input IO_DPS6, // JTAG=0, SPI=1
- // UART interface
- input IO_URX,
- output IO_UTX,
- // USB interface
- inout IO_USB_DP0,
- inout IO_USB_DN0,
- input IO_USB_SENSE0,
- output IO_USB_PULLUP0,
- inout IO_USB_DP1,
- inout IO_USB_DN1,
- input IO_USB_SENSE1,
- output IO_USB_PULLUP1,
- output IO_OBS,
- // GPIO x 16 interface
- inout IO_GP0,
- inout IO_GP1,
- inout IO_GP2,
- inout IO_GP3,
- inout IO_GP4,
- inout IO_GP5,
- inout IO_GP6,
- inout IO_GP7,
- inout IO_GP8,
- inout IO_GP9,
- inout IO_GP10,
- inout IO_GP11,
- inout IO_GP12,
- inout IO_GP13,
- inout IO_GP14,
- inout IO_GP15
-);
-
- localparam MAX_USB=2;
-
- logic clk_sys, clk_48mhz, rst_sys_n;
- logic [31:0] cio_gpio_p2d, cio_gpio_d2p, cio_gpio_en_d2p;
- logic cio_uart_rx_p2d, cio_uart_tx_d2p, cio_uart_tx_en_d2p;
- logic cio_usb_dp_p2d[MAX_USB], cio_usb_dp_d2p[MAX_USB], cio_usb_dp_en_d2p[MAX_USB];
- logic cio_usb_dn_p2d[MAX_USB], cio_usb_dn_d2p[MAX_USB], cio_usb_dn_en_d2p[MAX_USB];
- logic cio_usb_sense_p2d[MAX_USB];
- logic cio_usb_pullup_d2p[MAX_USB], cio_usb_pullup_en_d2p[MAX_USB];
- logic cio_spi_device_sck_p2d, cio_spi_device_csb_p2d, cio_spi_device_mosi_p2d;
- logic cio_spi_device_miso_d2p, cio_spi_device_miso_en_d2p;
- logic cio_jtag_tck_p2d, cio_jtag_tms_p2d, cio_jtag_tdi_p2d, cio_jtag_tdo_d2p;
- logic cio_jtag_trst_n_p2d, cio_jtag_srst_n_p2d;
-
- // Top-level design
- top_earlgrey_usb #(
- .MAX_USB(MAX_USB),
- .N_USB(2),
- .USB_UART(2),
- .USB_DEVICE(1)
- ) top_earlgrey_usb (
- .clk_i (clk_sys),
- .rst_ni (rst_sys_n),
-
- .jtag_tck_i (cio_jtag_tck_p2d),
- .jtag_tms_i (cio_jtag_tms_p2d),
- .jtag_trst_ni (cio_jtag_trst_n_p2d),
- .jtag_td_i (cio_jtag_tdi_p2d),
- .jtag_td_o (cio_jtag_tdo_d2p),
-
- .cio_uart_rx_p2d_i (cio_uart_rx_p2d),
- .cio_uart_tx_d2p_o (cio_uart_tx_d2p),
- .cio_uart_tx_en_d2p_o (cio_uart_tx_en_d2p),
- .clk_48mhz_i (clk_48mhz),
- .cio_usb_dp_i (cio_usb_dp_p2d),
- .cio_usb_dp_o (cio_usb_dp_d2p),
- .cio_usb_dp_en_o (cio_usb_dp_en_d2p),
- .cio_usb_dn_i (cio_usb_dn_p2d),
- .cio_usb_dn_o (cio_usb_dn_d2p),
- .cio_usb_dn_en_o (cio_usb_dn_en_d2p),
- .cio_usb_sense_i (cio_usb_sense_p2d),
- .cio_usb_pullup_o (cio_usb_pullup_d2p),
- .cio_usb_pullup_en_o (cio_usb_pullup_en_d2p),
-
- .cio_gpio_p2d_i (cio_gpio_p2d),
- .cio_gpio_d2p_o (cio_gpio_d2p),
- .cio_gpio_en_d2p_o (cio_gpio_en_d2p),
-
- .cio_spi_device_sck_i (cio_spi_device_sck_p2d),
- .cio_spi_device_csb_i (cio_spi_device_csb_p2d),
- .cio_spi_device_mosi_i (cio_spi_device_mosi_p2d),
- .cio_spi_device_miso_o (cio_spi_device_miso_d2p),
- .cio_spi_device_miso_en_o (cio_spi_device_miso_en_d2p),
-
- .scanmode_i (1'b0)// 1 for Scan
- );
-
- // Clock and reset
- clkgen_xil7series clkgen (
- .IO_CLK (IO_CLK),
- .IO_RST_N (IO_RST_N & cio_jtag_srst_n_p2d),
- .clk_sys (clk_sys),
- .clk_48MHz (clk_48mhz),
- .rst_sys_n (rst_sys_n)
- );
-
- assign IO_OBS = cio_usb_dp_en_d2p[0];
- // pad control
- padctl_usb padctl (
- // UART
- .cio_uart_rx_p2d,
- .cio_uart_tx_d2p,
- .cio_uart_tx_en_d2p,
- // USB
- .cio_usb_dp_p2d(cio_usb_dp_p2d),
- .cio_usb_dp_d2p(cio_usb_dp_d2p),
- .cio_usb_dp_en_d2p(cio_usb_dp_en_d2p),
- .cio_usb_dn_p2d(cio_usb_dn_p2d),
- .cio_usb_dn_d2p(cio_usb_dn_d2p),
- .cio_usb_dn_en_d2p(cio_usb_dn_en_d2p),
- .cio_usb_sense_p2d(cio_usb_sense_p2d),
- .cio_usb_pullup_d2p(cio_usb_pullup_d2p),
- .cio_usb_pullup_en_d2p(cio_usb_pullup_en_d2p),
- // GPIO
- .cio_gpio_p2d,
- .cio_gpio_d2p,
- .cio_gpio_en_d2p,
- // pads
- .IO_URX,
- .IO_UTX,
- .IO_USB_DP0,
- .IO_USB_DN0,
- .IO_USB_SENSE0,
- .IO_USB_PULLUP0,
- .IO_USB_DP1,
- .IO_USB_DN1,
- .IO_USB_SENSE1,
- .IO_USB_PULLUP1,
- .IO_GP0,
- .IO_GP1,
- .IO_GP2,
- .IO_GP3,
- .IO_GP4,
- .IO_GP5,
- .IO_GP6,
- .IO_GP7,
- .IO_GP8,
- .IO_GP9,
- .IO_GP10,
- .IO_GP11,
- .IO_GP12,
- .IO_GP13,
- .IO_GP14,
- .IO_GP15,
-
- .cio_spi_device_sck_p2d,
- .cio_spi_device_csb_p2d,
- .cio_spi_device_mosi_p2d,
- .cio_spi_device_miso_d2p,
- .cio_spi_device_miso_en_d2p,
- .cio_jtag_tck_p2d,
- .cio_jtag_tms_p2d,
- .cio_jtag_trst_n_p2d,
- .cio_jtag_srst_n_p2d,
- .cio_jtag_tdi_p2d,
- .cio_jtag_tdo_d2p,
- .IO_DPS0,
- .IO_DPS1,
- .IO_DPS2,
- .IO_DPS3,
- .IO_DPS4,
- .IO_DPS5,
- .IO_DPS6
- );
-endmodule
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_usb_verilator.sv b/hw/top_earlgrey/rtl/top_earlgrey_usb_verilator.sv
deleted file mode 100644
index 8b8e17a..0000000
--- a/hw/top_earlgrey/rtl/top_earlgrey_usb_verilator.sv
+++ /dev/null
@@ -1,138 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-module top_earlgrey_usb_verilator (
- // Clock and Reset
- input clk_i,
- input rst_ni
- );
-
- localparam MAX_USB=1;
-
- logic cio_jtag_tck, cio_jtag_tms, cio_jtag_tdi, cio_jtag_tdo;
- logic cio_jtag_trst_n, cio_jtag_srst_n;
-
- logic [31:0] cio_gpio_p2d, cio_gpio_d2p, cio_gpio_en_d2p;
- logic cio_uart_rx_p2d, cio_uart_tx_d2p, cio_uart_tx_en_d2p;
- logic dio_usb_dp_p2d[MAX_USB], dio_usb_dp_d2p[MAX_USB], dio_usb_dp_en_d2p[MAX_USB];
- logic dio_usb_dn_p2d[MAX_USB], dio_usb_dn_d2p[MAX_USB], dio_usb_dn_en_d2p[MAX_USB];
- logic dio_usb_sense_p2d[MAX_USB], dio_usb_pullup_d2p[MAX_USB], dio_usb_pullup_en_d2p[MAX_USB];
-
- logic cio_spi_device_sck_p2d, cio_spi_device_csb_p2d;
- logic cio_spi_device_mosi_p2d;
- logic cio_spi_device_miso_d2p, cio_spi_device_miso_en_d2p;
-
- logic IO_JTCK, IO_JTMS, IO_JTRST_N, IO_JTDI, IO_JTDO;
-
- // Top-level design
- top_earlgrey_usb #(
- .MAX_USB(1),
- .N_USB(1),
- .USB_UART(0),
- .USB_DEVICE(1)
- ) top_earlgrey_usb (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- .jtag_tck_i (IO_JTCK),
- .jtag_tms_i (IO_JTMS),
- .jtag_trst_ni (rst_ni),
- .jtag_td_i (IO_JTDI),
- .jtag_td_o (IO_JTDO),
-
- .dio_uart_rx_i (cio_uart_rx_p2d),
- .dio_uart_tx_o (cio_uart_tx_d2p),
- .dio_uart_tx_en_o (cio_uart_tx_en_d2p),
-
- .clk_48mhz_i (clk_i),
- .dio_usb_dp_i (dio_usb_dp_p2d),
- .dio_usb_dp_o (dio_usb_dp_d2p),
- .dio_usb_dp_en_o (dio_usb_dp_en_d2p),
- .dio_usb_dn_i (dio_usb_dn_p2d),
- .dio_usb_dn_o (dio_usb_dn_d2p),
- .dio_usb_dn_en_o (dio_usb_dn_en_d2p),
- .dio_usb_sense_i (dio_usb_sense_p2d),
- .dio_usb_pullup_o (dio_usb_pullup_d2p),
- .dio_usb_pullup_en_o (dio_usb_pullup_en_d2p),
-
- .mio_in_i (cio_gpio_p2d),
- .mio_out_o (cio_gpio_d2p),
- .mio_oe_o (cio_gpio_en_d2p),
-
- .dio_spi_device_sck_i (cio_spi_device_sck_p2d),
- .dio_spi_device_csb_i (cio_spi_device_csb_p2d),
- .dio_spi_device_mosi_i (cio_spi_device_mosi_p2d),
- .dio_spi_device_miso_o (cio_spi_device_miso_d2p),
- .dio_spi_device_miso_en_o (cio_spi_device_miso_en_d2p),
-
- .scanmode_i (1'b0)
- );
-
- // GPIO DPI
- gpiodpi
- #(.N_GPIO(32))
- u_gpiodpi(
- .clk_i(clk_i),
- .rst_ni(rst_ni),
- .gpio_p2d(cio_gpio_p2d),
- .gpio_d2p(cio_gpio_d2p),
- .gpio_en_d2p(cio_gpio_en_d2p)
- );
-
- // UART DPI
- // The baud rate set to match FPGA implementation; the frequency is
- // "artificial".
- // Both baud rate and frequency must match the settings used in the on-chip
- // software.
- uartdpi #(
- .BAUD('d9_600),
- .FREQ('d500_000)
- ) u_uart (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .tx_o (cio_uart_rx_p2d),
- .rx_i (cio_uart_tx_d2p)
- );
-
- // USB DPI
- usbdpi udpi (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .clk_48MHz_i (clk_i),
- .dp_p2d (dio_usb_dp_p2d[0]),
- .dp_d2p (dio_usb_dp_d2p[0]),
- .dp_en_d2p (dio_usb_dp_en_d2p[0]),
- .dn_p2d (dio_usb_dn_p2d[0]),
- .dn_d2p (dio_usb_dn_d2p[0]),
- .dn_en_d2p (dio_usb_dn_en_d2p[0]),
- .sense_p2d (dio_usb_sense_p2d[0]),
- .pullup_d2p (dio_usb_pullup_d2p[0]),
- .pullup_en_d2p (dio_usb_pullup_en_d2p[0])
- );
-
- // JTAG DPI for OpenOCD
- jtagdpi u_jtagdpi (
- .clk_i,
- .rst_ni,
-
- .jtag_tck (cio_jtag_tck),
- .jtag_tms (cio_jtag_tms),
- .jtag_tdi (cio_jtag_tdi),
- .jtag_tdo (cio_jtag_tdo),
- .jtag_trst_n (cio_jtag_trst_n),
- .jtag_srst_n (cio_jtag_srst_n)
- );
-
- // SPI DPI
- spidpi u_spi (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
- .spi_device_sck_o (cio_spi_device_sck_p2d),
- .spi_device_csb_o (cio_spi_device_csb_p2d),
- .spi_device_mosi_o (cio_spi_device_mosi_p2d),
- .spi_device_miso_i (cio_spi_device_miso_d2p),
- .spi_device_miso_en_i (cio_spi_device_miso_en_d2p)
- );
-
-endmodule
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
index c334b83..5535aed 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
@@ -18,6 +18,10 @@
logic cio_spi_device_mosi_p2d;
logic cio_spi_device_miso_d2p, cio_spi_device_miso_en_d2p;
+ logic cio_usbdev_sense_p2d, cio_usbdev_pullup_d2p, cio_usbdev_pullup_en_d2p;
+ logic cio_usbdev_dp_p2d, cio_usbdev_dp_d2p, cio_usbdev_dp_en_d2p;
+ logic cio_usbdev_dn_p2d, cio_usbdev_dn_d2p, cio_usbdev_dn_en_d2p;
+
logic IO_JTCK, IO_JTMS, IO_JTRST_N, IO_JTDI, IO_JTDO;
// Top-level design
@@ -25,6 +29,8 @@
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .clk_usb_48mhz_i (clk_i),
+
.jtag_tck_i (cio_jtag_tck),
.jtag_tms_i (cio_jtag_tms),
.jtag_trst_ni (cio_jtag_trst_n),
@@ -47,7 +53,17 @@
.dio_spi_device_miso_o (cio_spi_device_miso_d2p),
.dio_spi_device_miso_en_o (cio_spi_device_miso_en_d2p),
- .scanmode_i (1'b0)
+ .dio_usbdev_sense_i (cio_usbdev_sense_p2d),
+ .dio_usbdev_pullup_o (cio_usbdev_pullup_d2p),
+ .dio_usbdev_pullup_en_o (cio_usbdev_pullup_en_d2p),
+ .dio_usbdev_dp_i (cio_usbdev_dp_p2d),
+ .dio_usbdev_dp_o (cio_usbdev_dp_d2p),
+ .dio_usbdev_dp_en_o (cio_usbdev_dp_en_d2p),
+ .dio_usbdev_dn_i (cio_usbdev_dn_p2d),
+ .dio_usbdev_dn_o (cio_usbdev_dn_d2p),
+ .dio_usbdev_dn_en_o (cio_usbdev_dn_en_d2p),
+
+ .scanmode_i (1'b0)
);
// GPIO DPI
@@ -98,6 +114,22 @@
.spi_device_miso_en_i (cio_spi_device_miso_en_d2p)
);
+ // USB DPI
+ usbdpi u_usbdpi (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clk_48MHz_i (clk_i),
+ .sense_p2d (cio_usbdev_sense_p2d),
+ .pullup_d2p (cio_usbdev_pullup_d2p),
+ .pullup_en_d2p (cio_usbdev_pullup_en_d2p),
+ .dp_p2d (cio_usbdev_dp_p2d),
+ .dp_d2p (cio_usbdev_dp_d2p),
+ .dp_en_d2p (cio_usbdev_dp_en_d2p),
+ .dn_p2d (cio_usbdev_dn_p2d),
+ .dn_d2p (cio_usbdev_dn_d2p),
+ .dn_en_d2p (cio_usbdev_dn_en_d2p)
+ );
+
// monitor for termination
`ifndef END_MON_PATH
`define END_MON_PATH top_earlgrey.u_ram1p_ram_main
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index e22adfb..eca2f58 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -11,7 +11,7 @@
// PERIPH_INSEL ranges from 0 to NUM_MIO + 2 -1}
// 0 and 1 are tied to value 0 and 1
#define NUM_MIO 32
-#define NUM_DIO 6
+#define NUM_DIO 10
#define PINMUX_GPIO_GPIO_0_IN 0
#define PINMUX_GPIO_GPIO_1_IN 1
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core
index 6430e3c..bf7630e 100644
--- a/hw/top_earlgrey/top_earlgrey.core
+++ b/hw/top_earlgrey/top_earlgrey.core
@@ -23,6 +23,7 @@
- lowrisc:ip:flash_ctrl:0.1
- lowrisc:constants:top_pkg
- lowrisc:ip:nmi_gen
+ - lowrisc:ip:usbdev
files:
- ip/xbar_main/rtl/autogen/tl_main_pkg.sv
- ip/xbar_main/rtl/autogen/xbar_main.sv
diff --git a/hw/top_earlgrey/top_earlgrey_usb.core b/hw/top_earlgrey/top_earlgrey_usb.core
deleted file mode 100644
index 32ca59e..0000000
--- a/hw/top_earlgrey/top_earlgrey_usb.core
+++ /dev/null
@@ -1,79 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:top_earlgrey_usb:0.1"
-description: "Technology-independent Earl Grey with USB toplevel"
-filesets:
- files_rtl_generic:
- depend:
- - lowrisc:ip:uart:0.1
- - lowrisc:ip:gpio
- - lowrisc:ip:rv_core_ibex
- - lowrisc:ip:rv_dm
- - lowrisc:ip:rv_plic_component
- - lowrisc:ip:rv_timer
- - lowrisc:ip:tlul
- - lowrisc:ip:spi_device
- - lowrisc:ip:aes
- - lowrisc:ip:hmac
- - lowrisc:prim:ram_1p
- - lowrisc:prim:rom
- - lowrisc:prim:flash
- - lowrisc:ip:flash_ctrl:0.1
- - lowrisc:constants:top_pkg
- - lowrisc:ip:nmi_gen
- - lowrisc:ip:usbuart
- - lowrisc:ip:usbdev
- files:
- - ip/xbar_main/rtl/autogen/tl_main_pkg.sv
- - ip/xbar_main/rtl/autogen/xbar_main.sv
- - ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
- - ip/xbar_peri/rtl/autogen/xbar_peri.sv
- - ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
- - ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
- - ip/rv_plic/rtl/autogen/rv_plic.sv
- - ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
- - ip/pinmux/rtl/autogen/pinmux_reg_top.sv
- - ../ip/pinmux/rtl/pinmux.sv
- - ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
- - ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
- - ../ip/alert_handler/rtl/alert_pkg.sv
- - ../ip/alert_handler/rtl/alert_handler_reg_wrap.sv
- - ../ip/alert_handler/rtl/alert_handler_class.sv
- - ../ip/alert_handler/rtl/alert_handler_ping_timer.sv
- - ../ip/alert_handler/rtl/alert_handler_esc_timer.sv
- - ../ip/alert_handler/rtl/alert_handler_accu.sv
- - ../ip/alert_handler/rtl/alert_handler.sv
- - rtl/padctl_usb.sv
- - rtl/top_earlgrey_usb.sv
- file_type: systemVerilogSource
-
-parameters:
- SYNTHESIS:
- datatype: bool
- paramtype: vlogdefine
- ASIC_SYNTHESIS:
- datatype: bool
- paramtype: vlogdefine
- # For value definition, please see ip/prim/rtl/prim_pkg.sv
- PRIM_DEFAULT_IMPL:
- datatype: str
- paramtype: vlogdefine
- description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
- default: prim_pkg::ImplGeneric
-
-targets:
- default: &default_target
- filesets:
- - files_rtl_generic
- parameters:
- - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
- toplevel: top_earlgrey
- sim:
- default_tool: icarus
- filesets:
- - files_rtl_generic
- parameters:
- - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
- toplevel: top_earlgrey_usb
diff --git a/hw/top_earlgrey/top_earlgrey_usb_nexysvideo.core b/hw/top_earlgrey/top_earlgrey_usb_nexysvideo.core
deleted file mode 100644
index 52d8ab0..0000000
--- a/hw/top_earlgrey/top_earlgrey_usb_nexysvideo.core
+++ /dev/null
@@ -1,50 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:top_earlgrey_usb_nexysvideo:0.1"
-description: "Earl Grey with USB toplevel for the Nexys Video board"
-filesets:
- files_rtl_usb_nexysvideo:
- depend:
- - lowrisc:systems:top_earlgrey_usb:0.1
- files:
- - rtl/clkgen_xil7series.sv
- - rtl/top_earlgrey_usb_nexysvideo.sv
- file_type: systemVerilogSource
-
- files_constraints:
- files:
- - data/pins_nexysvideo.xdc
- file_type: xdc
-
-parameters:
- # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
- # directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
- # --SRAM_INIT_FILE=$PWD/build-bin/sw/device/fpga/examples/hello_usbdev/hello_usbdev.vmem
- # XXX: The VMEM file should be added to the sources of the Vivado project to
- # make the Vivado dependency tracking work. However this requires changes to
- # fusesoc first.
- SRAM_INIT_FILE:
- datatype: str
- description: SRAM initialization file in vmem hex format
- default: "../../../../../build-bin/sw/device/fpga/examples/hello_usbdev/hello_usbdev.vmem"
- paramtype: vlogdefine
- PRIM_DEFAULT_IMPL:
- datatype: str
- paramtype: vlogdefine
- description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
-
-targets:
- synth:
- default_tool: vivado
- filesets:
- - files_rtl_usb_nexysvideo
- - files_constraints
- toplevel: top_earlgrey_usb_nexysvideo
- parameters:
- - SRAM_INIT_FILE
- - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
- tools:
- vivado:
- part: "xc7a200tsbg484-1" # Nexys Video
diff --git a/hw/top_earlgrey/top_earlgrey_usb_verilator.cc b/hw/top_earlgrey/top_earlgrey_usb_verilator.cc
deleted file mode 100644
index 007fa34..0000000
--- a/hw/top_earlgrey/top_earlgrey_usb_verilator.cc
+++ /dev/null
@@ -1,39 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <iostream>
-
-#include "verilated_toplevel.h"
-#include "verilator_memutil.h"
-#include "verilator_sim_ctrl.h"
-
-int main(int argc, char **argv) {
- top_earlgrey_usb_verilator top;
- VerilatorMemUtil memutil;
- VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
- simctrl.SetTop(&top, &top.clk_i, &top.rst_ni,
- VerilatorSimCtrlFlags::ResetPolarityNegative);
-
- memutil.RegisterMemoryArea("rom",
- "TOP.top_earlgrey_usb_verilator.top_earlgrey_usb."
- "u_rom_rom.gen_mem_generic."
- "u_impl_generic");
- memutil.RegisterMemoryArea(
- "ram",
- "TOP.top_earlgrey_usb_verilator.top_earlgrey_usb.u_ram1p_ram_main"
- ".gen_mem_generic.u_impl_generic");
- memutil.RegisterMemoryArea(
- "flash",
- "TOP.top_earlgrey_usb_verilator.top_earlgrey_usb.u_flash_eflash."
- "gen_flash_banks[0].u_flash.gen_flash.u_impl_generic.u_mem.gen_mem_"
- "generic.u_impl_"
- "generic");
- simctrl.RegisterExtension(&memutil);
-
- std::cout << "Simulation of OpenTitan Earl Grey" << std::endl
- << "=================================" << std::endl
- << std::endl;
-
- return simctrl.Exec(argc, argv);
-}
diff --git a/hw/top_earlgrey/top_earlgrey_usb_verilator.core b/hw/top_earlgrey/top_earlgrey_usb_verilator.core
deleted file mode 100644
index a347fdf..0000000
--- a/hw/top_earlgrey/top_earlgrey_usb_verilator.core
+++ /dev/null
@@ -1,60 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:top_earlgrey_usb_verilator:0.1"
-description: "Earl Grey toplevel with USB for simulation with Verilator"
-filesets:
- files_sim_verilator:
- depend:
- - lowrisc:systems:top_earlgrey_usb:0.1
- - lowrisc:dv_dpi:uartdpi
- - lowrisc:dv_dpi:usbdpi
- - lowrisc:dv_dpi:gpiodpi
- - lowrisc:dv_dpi:jtagdpi
- - lowrisc:dv_dpi:spidpi
- - lowrisc:dv_verilator:simutil_verilator
- - lowrisc:dv_verilator:memutil_verilator
-
- files:
- - rtl/top_earlgrey_usb_verilator.sv: { file_type: systemVerilogSource }
- - top_earlgrey_usb_verilator.cc: { file_type: cppSource }
-parameters:
- # For value definition, please see ip/prim/rtl/prim_pkg.sv
- PRIM_DEFAULT_IMPL:
- datatype: str
- paramtype: vlogdefine
- description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
-
-targets:
- sim:
- parameters:
- - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
- default_tool: verilator
- filesets:
- - files_sim_verilator
- toplevel: top_earlgrey_usb_verilator
- tools:
- verilator:
- mode: cc
- verilator_options:
- # Disabling tracing reduces compile times but doesn't have a
- # huge influence on runtime performance.
- - '--trace'
- - '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
- # Remove FST options for VCD trace (~100 x faster but larger files)
- - '--trace-structs'
- - '--trace-params'
- - '--trace-max-array 1024'
- - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=top_earlgrey_usb_verilator -g"'
- - '-LDFLAGS "-pthread -lutil -lelf"'
- - "-Wall"
- - "-Wno-PINCONNECTEMPTY"
- # XXX: Cleanup all warnings and remove this option
- # (or make it more fine-grained at least)
- - "-Wno-fatal"
- make_options:
- # Optimization levels have a large impact on the runtime performance
- # of the simulation model. -O2 and -O3 are pretty similar, -Os is
- # slower than -O2/-O3
- - OPT_FAST="-O2"
diff --git a/hw/top_earlgrey/top_earlgrey_verilator.core b/hw/top_earlgrey/top_earlgrey_verilator.core
index 6f09f6d..c5e752d 100644
--- a/hw/top_earlgrey/top_earlgrey_verilator.core
+++ b/hw/top_earlgrey/top_earlgrey_verilator.core
@@ -12,6 +12,7 @@
- lowrisc:dv_dpi:gpiodpi
- lowrisc:dv_dpi:jtagdpi
- lowrisc:dv_dpi:spidpi
+ - lowrisc:dv_dpi:usbdpi
- lowrisc:dv_verilator:memutil_verilator
- lowrisc:dv_verilator:simutil_verilator
- lowrisc:ibex:ibex_tracer
diff --git a/sw/device/examples/hello_usbdev/hello_usbdev.c b/sw/device/examples/hello_usbdev/hello_usbdev.c
index 9c7b7dd..3182b3e 100644
--- a/sw/device/examples/hello_usbdev/hello_usbdev.c
+++ b/sw/device/examples/hello_usbdev/hello_usbdev.c
@@ -2,19 +2,40 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
+#include <stdbool.h>
#include "sw/device/lib/base/stdasm.h"
#include "sw/device/lib/common.h"
#include "sw/device/lib/gpio.h"
+#include "sw/device/lib/pinmux.h"
#include "sw/device/lib/runtime/hart.h"
+#include "sw/device/lib/spi_device.h"
#include "sw/device/lib/uart.h"
#include "sw/device/lib/usb_controlep.h"
#include "sw/device/lib/usb_simpleserial.h"
#include "sw/device/lib/usbdev.h"
// These just for the '/' printout
-#define USBDEV_BASE_ADDR 0x40020000
+#define USBDEV_BASE_ADDR 0x40150000
#include "usbdev_regs.h" // Generated.
+#define SPI_MAX 32
+
+// called from ctr0 when something bad happens
+// char I=illegal instruction, A=lsu error (address), E=ecall
+void trap_handler(uint32_t mepc, char c) {
+ uart_send_char(c);
+ uart_send_uint(mepc, 32);
+ while (1) {
+ gpio_write_all(0xAA00); // pattern
+ usleep(200 * 1000);
+ gpio_write_all(0x5500); // pattern
+ usleep(100 * 1000);
+ }
+}
+
+#define MK_PRINT(c) \
+ (((c != 0xa) && (c != 0xd) && ((c < 32) || (c > 126))) ? '_' : c)
+
// Build Configuration descriptor array
static uint8_t cfg_dscr[] = {
USB_CFG_DSCR_HEAD(
@@ -33,42 +54,32 @@
static usb_controlep_ctx_t control_ctx;
static usb_ss_ctx_t ss_ctx[2];
-static void test_error(void) {
- while (1) {
- gpio_write_all(0xAA00); // pattern
- usleep(200 * 1000);
- gpio_write_all(0x5500); // pattern
- usleep(100 * 1000);
- }
-}
-
-// Override default handler routines
-void handler_instr_ill_fault(void) {
- uart_send_str("Instruction Illegal fault");
- test_error();
-}
-
-// Override default handler routines
-void handler_lsu_fault(void) {
- uart_send_str("Load/Store Fault");
- test_error();
-}
-
-#define MK_PRINT(c) \
- (((c != 0xa) && (c != 0xd) && ((c < 32) || (c > 126))) ? '_' : c)
+// We signal PASS! after receiving USB_MAX.
+static volatile unsigned int num_chars_rx = 0;
+#ifndef USB_MAX
+#define USB_MAX 6
+#endif
/* Inbound USB characters get printed to the UART via these callbacks */
/* Not ideal because the UART is slower */
-static void serial_rx0(uint8_t c) { uart_send_char(MK_PRINT(c)); }
+static void serial_rx0(uint8_t c) {
+ uart_send_char(MK_PRINT(c));
+ num_chars_rx++;
+}
/* Add one to rx character so you can tell it is the second instance */
-static void serial_rx1(uint8_t c) { uart_send_char(MK_PRINT(c + 1)); }
+static void serial_rx1(uint8_t c) {
+ uart_send_char(MK_PRINT(c + 1));
+ num_chars_rx++;
+}
int main(int argc, char **argv) {
uart_init(UART_BAUD_RATE);
+ pinmux_init();
// Enable GPIO: 0-7 and 16 is input, 8-15 is output
gpio_init(0xFF00);
+ spid_init();
// Add DATE and TIME because I keep fooling myself with old versions
uart_send_str(
"Hello USB! "__DATE__
@@ -87,13 +98,19 @@
usb_controlep_init(&control_ctx, &usbdev_ctx, 0, cfg_dscr, sizeof(cfg_dscr));
usb_simpleserial_init(&ss_ctx[0], &usbdev_ctx, 1, serial_rx0);
usb_simpleserial_init(&ss_ctx[1], &usbdev_ctx, 2, serial_rx1);
+ bool pass_signaled = false;
uint32_t gpio_in;
uint32_t gpio_in_prev = 0;
uint32_t gpio_in_changes;
+ uint8_t spi_buf[SPI_MAX];
+ uint32_t spi_in;
+
+ spid_send("SPI!", 4);
while (1) {
usbdev_poll(&usbdev_ctx);
+
// report changed switches over UART
gpio_in = gpio_read() & 0x100FF; // 0-7 is switch input, 16 is FTDI
gpio_in_changes = (gpio_in & ~gpio_in_prev) | (~gpio_in & gpio_in_prev);
@@ -113,13 +130,25 @@
}
gpio_in_prev = gpio_in;
+ // SPI character echo
+ spi_in = spid_read_nb(spi_buf, SPI_MAX);
+ if (spi_in) {
+ uint32_t d = (*(uint32_t *)spi_buf) ^ 0x01010101;
+ spid_send(&d, 4);
+ uart_send_str("SPI: ");
+ for (int i = 0; i < spi_in; i++) {
+ uart_send_char(MK_PRINT(spi_buf[i]));
+ }
+ uart_send_str("\r\n");
+ }
// UART echo
char rcv_char;
while (uart_rcv_char(&rcv_char) != -1) {
uart_send_char(rcv_char);
+ gpio_write_all(rcv_char << 8);
if (rcv_char == '/') {
uart_send_char('I');
- uart_send_uint(REG32(USBDEV_INTR_STATE()), 12);
+ uart_send_uint(REG32(USBDEV_INTR_STATE()), 16);
uart_send_char('-');
uart_send_uint(REG32(USBDEV_USBSTAT()), 32);
uart_send_char(' ');
@@ -127,7 +156,15 @@
usb_simpleserial_send_byte(&ss_ctx[0], rcv_char);
usb_simpleserial_send_byte(&ss_ctx[1], rcv_char + 1);
}
- gpio_write_all(rcv_char << 8);
+ }
+
+ // Signal that the simulation passed
+ if ((num_chars_rx >= USB_MAX) && (pass_signaled == false)) {
+ uart_send_str("\r\nPASS!\r\n");
+ pass_signaled = true;
}
}
+ uart_send_str("\r\nUSB received 0x");
+ uart_send_uint(num_chars_rx, 32);
+ uart_send_str(" characters.\r\n");
}
diff --git a/sw/device/examples/hello_usbdev/meson.build b/sw/device/examples/hello_usbdev/meson.build
index dc89956..86bc516 100644
--- a/sw/device/examples/hello_usbdev/meson.build
+++ b/sw/device/examples/hello_usbdev/meson.build
@@ -8,8 +8,10 @@
name_suffix: 'elf',
dependencies: [
sw_lib_runtime_hart,
+ sw_lib_pinmux,
sw_lib_gpio,
sw_lib_irq,
+ sw_lib_spi_device,
sw_lib_uart,
sw_lib_usb,
riscv_crt,
diff --git a/sw/device/lib/usbdev.c b/sw/device/lib/usbdev.c
index bd5f74b..5bb905b 100644
--- a/sw/device/lib/usbdev.c
+++ b/sw/device/lib/usbdev.c
@@ -6,7 +6,7 @@
#include "sw/device/lib/common.h"
-#define USBDEV_BASE_ADDR 0x40020000
+#define USBDEV_BASE_ADDR 0x40150000
#include "usbdev_regs.h" // Generated.
#define EXTRACT(n, f) ((n >> USBDEV_##f##_OFFSET) & USBDEV_##f##_MASK)
diff --git a/sw/device/lib/usbdev.h b/sw/device/lib/usbdev.h
index 6e14770..4e4c19a 100644
--- a/sw/device/lib/usbdev.h
+++ b/sw/device/lib/usbdev.h
@@ -224,10 +224,18 @@
*/
void usbdev_init(usbdev_ctx_t *ctx);
-// Used for tracing what is going on
+// Used for tracing what is going on. This may impact timing which is critical
+// when simulating with the USB DPI module.
+//#define ENABLE_TRC
+#ifdef ENABLE_TRC
#include "sw/device/lib/uart.h"
#define TRC_S(s) uart_send_str(s)
#define TRC_I(i, b) uart_send_uint(i, b)
#define TRC_C(c) uart_send_char(c)
+#else
+#define TRC_S(s)
+#define TRC_I(i, b)
+#define TRC_C(c)
+#endif
#endif // OPENTITAN_SW_DEVICE_LIB_USBDEV_H_
