[top] Integrate latest ast and remove ast_wrapper
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Various fixes for ast connection
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Add missing core file
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Various fixes for other top levels
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] various connectivity fixes
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] complete removal of ast_wrapper
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] fix englishbreakfast syntax error
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] fix typo
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy.sv b/hw/ip/flash_ctrl/rtl/flash_phy.sv
index 9de316f..3c78579 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy.sv
@@ -241,6 +241,10 @@
.lc_en_o(lc_nvm_debug_en)
);
+ lc_ctrl_pkg::lc_tx_t bist_enable_qual;
+ assign bist_enable_qual = lc_ctrl_pkg::lc_tx_t'(flash_bist_enable_i &
+ lc_nvm_debug_en[FlashBistSel]);
+
prim_flash #(
.NumBanks(NumBanks),
.InfosPerBank(InfosPerBank),
@@ -264,7 +268,7 @@
.tdi_i(jtag_req_i.tdi & (lc_nvm_debug_en[FlashLcTdiSel] == lc_ctrl_pkg::On)),
.tms_i(jtag_req_i.tms & (lc_nvm_debug_en[FlashLcTmsSel] == lc_ctrl_pkg::On)),
.tdo_o(tdo),
- .bist_enable_i(flash_bist_enable_i & lc_nvm_debug_en[FlashBistSel]),
+ .bist_enable_i(bist_enable_qual),
.scanmode_i,
.scan_en_i,
.scan_rst_ni,
diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv b/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv
index 532dbbb..21fab8f 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv
@@ -16,11 +16,11 @@
// variables referenced only by pwrmgr
localparam int TotalWakeWidth = pwrmgr_reg_pkg::NumWkups + 2; // Abort and fall through are added
- // The following structs should eventually be relocted to other modules
- typedef enum logic [1:0] {
- DiffValid = 2'b10,
- DiffInvalid = 2'b01
- } pwrmgr_diff_e;
+ //// The following structs should eventually be relocted to other modules
+ //typedef enum logic [1:0] {
+ // DiffValid = 2'b10,
+ // DiffInvalid = 2'b01
+ //} pwrmgr_diff_e;
// pwrmgr to ast
typedef struct packed {
@@ -33,27 +33,27 @@
} pwr_ast_req_t;
typedef struct packed {
- pwrmgr_diff_e slow_clk_val;
- pwrmgr_diff_e core_clk_val;
- pwrmgr_diff_e io_clk_val;
- pwrmgr_diff_e usb_clk_val;
+ logic slow_clk_val;
+ logic core_clk_val;
+ logic io_clk_val;
+ logic usb_clk_val;
logic main_pok;
} pwr_ast_rsp_t;
// default value of pwr_ast_rsp (for dangling ports)
parameter pwr_ast_rsp_t PWR_AST_RSP_DEFAULT = '{
- slow_clk_val: DiffValid,
- core_clk_val: DiffValid,
- io_clk_val: DiffValid,
- usb_clk_val: DiffValid,
+ slow_clk_val: 1'b1,
+ core_clk_val: 1'b1,
+ io_clk_val: 1'b1,
+ usb_clk_val: 1'b1,
main_pok: 1'b1
};
parameter pwr_ast_rsp_t PWR_AST_RSP_SYNC_DEFAULT = '{
- slow_clk_val: DiffInvalid,
- core_clk_val: DiffInvalid,
- io_clk_val: DiffInvalid,
- usb_clk_val: DiffInvalid,
+ slow_clk_val: 1'b0,
+ core_clk_val: 1'b0,
+ io_clk_val: 1'b0,
+ usb_clk_val: 1'b0,
main_pok: 1'b0
};
diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv b/hw/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv
index c8dc69e..243182c 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv
@@ -55,15 +55,15 @@
// all clocks sources are valid
// if clocks (usb) not configured to be active, then just bypass check
- assign all_clks_valid = (ast_i.core_clk_val == DiffValid) &
- (ast_i.io_clk_val == DiffValid) &
- (~usb_clk_en_active_i | ast_i.usb_clk_val == DiffValid);
+ assign all_clks_valid = ast_i.core_clk_val &
+ ast_i.io_clk_val &
+ (~usb_clk_en_active_i | ast_i.usb_clk_val);
// if clocks were configured to turn off, make sure val is invalid
// if clocks were not configured to turn off, just bypass the check
- assign all_clks_invalid = (core_clk_en_i | ast_i.core_clk_val != DiffValid) &
- (io_clk_en_i | ast_i.io_clk_val != DiffValid) &
- (usb_clk_en_lp_i | ast_i.usb_clk_val != DiffValid);
+ assign all_clks_invalid = (core_clk_en_i | ~ast_i.core_clk_val) &
+ (io_clk_en_i | ~ast_i.io_clk_val) &
+ (usb_clk_en_lp_i | ~ast_i.usb_clk_val);
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
@@ -224,7 +224,7 @@
/// Unused
////////////////////////////
- logic [1:0] unused_slow_clk_val;
+ logic unused_slow_clk_val;
assign unused_slow_clk_val = ast_i.slow_clk_val;
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 069b49b..9af4c52 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -3253,9 +3253,8 @@
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
- end_idx: -1
- top_type: broadcast
- top_signame: lc_ctrl_lc_clk_byp_req
+ external: true
+ top_signame: lc_clk_byp_req
index: -1
}
{
@@ -4150,6 +4149,10 @@
act: rcv
package: lc_ctrl_pkg
inst_name: clkmgr_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: lc_clk_byp_ack
index: -1
}
{
@@ -4645,7 +4648,7 @@
type: req_rsp
name: ast_alert
act: rsp
- package: ast_wrapper_pkg
+ package: ast_pkg
inst_name: sensor_ctrl_aon
width: 1
default: ""
@@ -4658,7 +4661,7 @@
type: uni
name: ast_status
act: rcv
- package: ast_wrapper_pkg
+ package: ast_pkg
inst_name: sensor_ctrl_aon
width: 1
default: ""
@@ -6237,6 +6240,10 @@
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
+ clock_reset_export:
+ [
+ ast
+ ]
base_addr: 0x41160000
clock_connections:
{
@@ -6330,6 +6337,10 @@
act: req
package: entropy_src_pkg
inst_name: entropy_src
+ width: 1
+ default: ""
+ external: true
+ top_signame: es_rng
index: -1
}
{
@@ -6378,6 +6389,10 @@
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
+ clock_reset_export:
+ [
+ ast
+ ]
base_addr: 0x41170000
clock_connections:
{
@@ -7304,7 +7319,6 @@
[
otp_ctrl.lc_check_byp_en
]
- lc_ctrl.lc_clk_byp_req: []
lc_ctrl.lc_clk_byp_ack:
[
clkmgr_aon.lc_clk_bypass_ack
@@ -7532,6 +7546,9 @@
eflash.flash_power_ready_h: flash_power_ready_h
eflash.flash_test_mode_a: flash_test_mode_a
eflash.flash_test_voltage_h: flash_test_voltage_h
+ entropy_src.entropy_src_rng: es_rng
+ lc_ctrl.lc_clk_byp_req: lc_clk_byp_req
+ clkmgr_aon.ast_clk_bypass_ack: lc_clk_byp_ack
ast_edn.edn: ""
clkmgr_aon.clocks_ast: clks_ast
rstmgr_aon.resets_ast: rsts_ast
@@ -11618,6 +11635,14 @@
[
io_div4_secure
]
+ entropy_src:
+ [
+ main_secure
+ ]
+ edn0:
+ [
+ main_secure
+ ]
}
}
wakeups:
@@ -11654,6 +11679,14 @@
[
sys_io_div4
]
+ entropy_src:
+ [
+ sys
+ ]
+ edn0:
+ [
+ sys
+ ]
}
}
reset_paths:
@@ -12351,9 +12384,8 @@
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
- end_idx: -1
- top_type: broadcast
- top_signame: lc_ctrl_lc_clk_byp_req
+ external: true
+ top_signame: lc_clk_byp_req
index: -1
}
{
@@ -12910,6 +12942,10 @@
act: rcv
package: lc_ctrl_pkg
inst_name: clkmgr_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: lc_clk_byp_ack
index: -1
}
{
@@ -13185,7 +13221,7 @@
type: req_rsp
name: ast_alert
act: rsp
- package: ast_wrapper_pkg
+ package: ast_pkg
inst_name: sensor_ctrl_aon
width: 1
default: ""
@@ -13198,7 +13234,7 @@
type: uni
name: ast_status
act: rcv
- package: ast_wrapper_pkg
+ package: ast_pkg
inst_name: sensor_ctrl_aon
width: 1
default: ""
@@ -13765,6 +13801,10 @@
act: req
package: entropy_src_pkg
inst_name: entropy_src
+ width: 1
+ default: ""
+ external: true
+ top_signame: es_rng
index: -1
}
{
@@ -14818,7 +14858,7 @@
netname: pwrmgr_ast_rsp
}
{
- package: ast_wrapper_pkg
+ package: ast_pkg
struct: ast_alert_req
signame: sensor_ctrl_ast_alert_req_i
width: 1
@@ -14829,7 +14869,7 @@
netname: sensor_ctrl_ast_alert_req
}
{
- package: ast_wrapper_pkg
+ package: ast_pkg
struct: ast_alert_rsp
signame: sensor_ctrl_ast_alert_rsp_o
width: 1
@@ -14840,7 +14880,7 @@
netname: sensor_ctrl_ast_alert_rsp
}
{
- package: ast_wrapper_pkg
+ package: ast_pkg
struct: ast_status
signame: sensor_ctrl_ast_status_i
width: 1
@@ -14972,6 +15012,50 @@
netname: flash_test_voltage_h
}
{
+ package: entropy_src_pkg
+ struct: entropy_src_rng_req
+ signame: es_rng_req_o
+ width: 1
+ type: req_rsp
+ default: ""
+ direction: out
+ index: -1
+ netname: es_rng_req
+ }
+ {
+ package: entropy_src_pkg
+ struct: entropy_src_rng_rsp
+ signame: es_rng_rsp_i
+ width: 1
+ type: req_rsp
+ default: ""
+ direction: in
+ index: -1
+ netname: es_rng_rsp
+ }
+ {
+ package: lc_ctrl_pkg
+ struct: lc_tx
+ signame: lc_clk_byp_req_o
+ width: 1
+ type: uni
+ default: lc_ctrl_pkg::Off
+ direction: out
+ index: -1
+ netname: lc_clk_byp_req
+ }
+ {
+ package: lc_ctrl_pkg
+ struct: lc_tx
+ signame: lc_clk_byp_ack_i
+ width: 1
+ type: uni
+ default: ""
+ direction: in
+ index: -1
+ netname: lc_clk_byp_ack
+ }
+ {
package: edn_pkg
struct: edn_req
signame: ast_edn_edn_req_i
@@ -15648,17 +15732,6 @@
{
package: lc_ctrl_pkg
struct: lc_tx
- signame: lc_ctrl_lc_clk_byp_req
- width: 1
- type: uni
- end_idx: -1
- act: req
- suffix: ""
- default: lc_ctrl_pkg::Off
- }
- {
- package: lc_ctrl_pkg
- struct: lc_tx
signame: lc_ctrl_lc_clk_byp_ack
width: 1
type: uni
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 4641605..57e1c3f 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -484,6 +484,7 @@
clock_srcs: {clk_i: "main"},
clock_group: "secure",
reset_connections: {rst_ni: "sys"},
+ clock_reset_export: ["ast"],
base_addr: "0x41160000",
},
{ name: "edn0",
@@ -491,6 +492,7 @@
clock_srcs: {clk_i: "main"},
clock_group: "secure",
reset_connections: {rst_ni: "sys"},
+ clock_reset_export: ["ast"],
base_addr: "0x41170000",
},
{ name: "edn1",
@@ -750,7 +752,6 @@
'lc_ctrl.lc_check_byp_en' : ['otp_ctrl.lc_check_byp_en'],
// TODO: OTP Clock bypass signal going from LC to AST/clkmgr
- 'lc_ctrl.lc_clk_byp_req' : [],
'lc_ctrl.lc_clk_byp_ack' : ['clkmgr_aon.lc_clk_bypass_ack'],
// LC access control signal broadcast
@@ -775,25 +776,28 @@
// ext is to create port in the top.
'external': {
- 'clkmgr_aon.clk_main': 'clk_main', // clock inputs
- 'clkmgr_aon.clk_io': 'clk_io', // clock inputs
- 'clkmgr_aon.clk_usb': 'clk_usb', // clock inputs
- 'clkmgr_aon.clk_aon': 'clk_aon', // clock inputs
- 'rstmgr_aon.ast': 'rstmgr_ast',
- 'pwrmgr_aon.pwr_ast': 'pwrmgr_ast',
- 'sensor_ctrl_aon.ast_alert': 'sensor_ctrl_ast_alert',
- 'sensor_ctrl_aon.ast_status': 'sensor_ctrl_ast_status',
- 'usbdev.usb_ref_val': '',
- 'usbdev.usb_ref_pulse': '',
- 'peri.tl_ast_wrapper': 'ast_tl',
- 'otp_ctrl.otp_ast_pwr_seq': '',
- 'otp_ctrl.otp_ast_pwr_seq_h': '',
- 'eflash.flash_bist_enable': 'flash_bist_enable',
- 'eflash.flash_power_down_h': 'flash_power_down_h',
- 'eflash.flash_power_ready_h': 'flash_power_ready_h',
- 'eflash.flash_test_mode_a': 'flash_test_mode_a',
- 'eflash.flash_test_voltage_h': 'flash_test_voltage_h',
- 'ast_edn.edn': ''
+ 'clkmgr_aon.clk_main' : 'clk_main', // clock inputs
+ 'clkmgr_aon.clk_io' : 'clk_io', // clock inputs
+ 'clkmgr_aon.clk_usb' : 'clk_usb', // clock inputs
+ 'clkmgr_aon.clk_aon' : 'clk_aon', // clock inputs
+ 'rstmgr_aon.ast' : 'rstmgr_ast',
+ 'pwrmgr_aon.pwr_ast' : 'pwrmgr_ast',
+ 'sensor_ctrl_aon.ast_alert' : 'sensor_ctrl_ast_alert',
+ 'sensor_ctrl_aon.ast_status' : 'sensor_ctrl_ast_status',
+ 'usbdev.usb_ref_val' : '',
+ 'usbdev.usb_ref_pulse' : '',
+ 'peri.tl_ast_wrapper' : 'ast_tl',
+ 'otp_ctrl.otp_ast_pwr_seq' : '',
+ 'otp_ctrl.otp_ast_pwr_seq_h' : '',
+ 'eflash.flash_bist_enable' : 'flash_bist_enable',
+ 'eflash.flash_power_down_h' : 'flash_power_down_h',
+ 'eflash.flash_power_ready_h' : 'flash_power_ready_h',
+ 'eflash.flash_test_mode_a' : 'flash_test_mode_a',
+ 'eflash.flash_test_voltage_h' : 'flash_test_voltage_h',
+ 'entropy_src.entropy_src_rng' : 'es_rng',
+ 'lc_ctrl.lc_clk_byp_req' : 'lc_clk_byp_req',
+ 'clkmgr_aon.ast_clk_bypass_ack': 'lc_clk_byp_ack',
+ 'ast_edn.edn' : ''
},
},
diff --git a/hw/top_earlgrey/ip/ast/ast_wrapper_pkg.core b/hw/top_earlgrey/ip/ast/ast_pkg.core
similarity index 85%
rename from hw/top_earlgrey/ip/ast/ast_wrapper_pkg.core
rename to hw/top_earlgrey/ip/ast/ast_pkg.core
index 88b7e7c..d366795 100644
--- a/hw/top_earlgrey/ip/ast/ast_wrapper_pkg.core
+++ b/hw/top_earlgrey/ip/ast/ast_pkg.core
@@ -2,7 +2,7 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:ast_wrapper_pkg"
+name: "lowrisc:systems:ast_pkg"
description: "Analog sensor top (AST) wrapper package"
filesets:
@@ -11,7 +11,7 @@
- lowrisc:constants:top_pkg
- lowrisc:ip:lc_ctrl_pkg
files:
- - rtl/ast_wrapper_pkg.sv
+ - rtl/ast_pkg.sv
file_type: systemVerilogSource
targets:
diff --git a/hw/top_earlgrey/ip/ast/ast_wrapper.core b/hw/top_earlgrey/ip/ast/ast_wrapper.core
deleted file mode 100644
index 195bdc0..0000000
--- a/hw/top_earlgrey/ip/ast/ast_wrapper.core
+++ /dev/null
@@ -1,39 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:ast_wrapper:0.1"
-description: "Analog sensor top (AST) wrapper"
-
-filesets:
- files_rtl:
- depend:
- - lowrisc:prim:assert
- - lowrisc:tlul:headers
- - lowrisc:systems:ast_wrapper_pkg
- - lowrisc:systems:ast
- - lowrisc:systems:sensor_ctrl_reg
- - lowrisc:systems:clkmgr_pkg
- - "fileset_top ? (lowrisc:ip:pwrmgr_pkg)"
- - "fileset_topgen ? (lowrisc:systems:topgen)"
- - lowrisc:ip:rstmgr
- - lowrisc:ip:entropy_src_pkg
- files:
- - rtl/ast_wrapper.sv
- file_type: systemVerilogSource
-
-
-targets:
- default: &default_target
- filesets:
- - files_rtl
- toplevel: ast_wrapper
-
- lint:
- <<: *default_target
- default_tool: verilator
- tools:
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv b/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
index 157b187..77304e0 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
@@ -45,14 +45,19 @@
logic clk_aon;
} ast_clks_t;
+ // Alert interface
typedef struct packed {
- logic [NumAlerts-1:0] alerts_p;
- logic [NumAlerts-1:0] alerts_n;
+ logic p;
+ logic n;
+ } ast_dif_t;
+
+ typedef struct packed {
+ ast_dif_t [NumAlerts-1:0] alerts;
} ast_alert_req_t;
typedef struct packed {
- logic [NumAlerts-1:0] alerts_ack;
- logic [NumAlerts-1:0] alerts_trig;
+ ast_dif_t [NumAlerts-1:0] alerts_ack;
+ ast_dif_t [NumAlerts-1:0] alerts_trig;
} ast_alert_rsp_t;
typedef struct packed {
@@ -65,23 +70,6 @@
SwAck = 1
} ast_ack_mode_e;
- parameter ast_alert_req_t AST_ALERT_REQ_DEFAULT = '{
- alerts_p: '0,
- alerts_n: {NumAlerts{1'b1}}
- };
-
- typedef struct packed {
- logic flash_bist_enable;
- logic flash_power_down_h;
- logic flash_power_ready_h;
- } ast_eflash_t;
-
- // Alert interface
- typedef struct packed {
- logic p;
- logic n;
- } ast_dif_t;
-
// Read-Write Margin interface
typedef struct packed {
logic marg_en_a;
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_wrapper.sv b/hw/top_earlgrey/ip/ast/rtl/ast_wrapper.sv
deleted file mode 100644
index a910e35..0000000
--- a/hw/top_earlgrey/ip/ast/rtl/ast_wrapper.sv
+++ /dev/null
@@ -1,419 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// This is the integration wrapper layer for AST
-
-`include "prim_assert.sv"
-
-module ast_wrapper import ast_wrapper_pkg::*;
-(
- // root clock / rests
- input clk_ext_i,
- input por_ni,
-
- // Bus Interface
- input tlul_pkg::tl_h2d_t bus_i,
- output tlul_pkg::tl_d2h_t bus_o,
-
- // pwrmgr interface
- input pwrmgr_pkg::pwr_ast_req_t pwr_i,
- output pwrmgr_pkg::pwr_ast_rsp_t pwr_o,
-
- // rstmgr interface
- output ast_rst_t rst_o,
-
- // clkmgr interface
- output ast_clks_t clks_o,
-
- // usb interface
- input usb_ref_pulse_i,
- input usb_ref_val_i,
-
- // synchronization clocks / rests
- input clkmgr_pkg::clkmgr_ast_out_t clks_ast_i,
- input rstmgr_pkg::rstmgr_ast_out_t rsts_ast_i,
-
- // adc
- // The adc package definition should eventually be moved to the adc module
- input adc_ast_req_t adc_i,
- output adc_ast_rsp_t adc_o,
-
- // entropy source interface
- // The entropy source pacakge definition should eventually be moved to es
- input entropy_src_pkg::entropy_src_rng_req_t es_i,
- output entropy_src_pkg::entropy_src_rng_rsp_t es_o,
-
- // alerts interface
- input ast_alert_rsp_t alert_i,
- output ast_alert_req_t alert_o,
-
- // assorted ast status
- output ast_status_t status_o,
-
- // dft related
- input scanmode_i,
- input scan_reset_ni,
-
- // usb io calibration
- output logic [UsbCalibWidth-1:0] usb_io_pu_cal_o,
-
- // IO connection to flash
- output ast_eflash_t ast_eflash_o
-);
-
- // For nettype real awire;
- import ana_pkg::*;
-
- //TODO: Added for new typdef's
- import ast_pkg::*;
-
-
- ///////////////////////////
- // AST instantiation
- ///////////////////////////
-
- // Switch these to prim_mux cells
- logic core_clk_val;
- logic slow_clk_val;
- logic io_clk_val;
- logic usb_clk_val;
-
- assign pwr_o.core_clk_val = core_clk_val ? pwrmgr_pkg::DiffValid : pwrmgr_pkg::DiffInvalid;
- assign pwr_o.slow_clk_val = slow_clk_val ? pwrmgr_pkg::DiffValid : pwrmgr_pkg::DiffInvalid;
- assign pwr_o.io_clk_val = io_clk_val ? pwrmgr_pkg::DiffValid : pwrmgr_pkg::DiffInvalid;
- assign pwr_o.usb_clk_val = usb_clk_val ? pwrmgr_pkg::DiffValid : pwrmgr_pkg::DiffInvalid;
-
-// need to hookup later
-`ifndef VERILATOR
-`ifndef SYNTHESIS
- awire adc_a0_a; // ADC A0 Analog Input
- awire adc_a1_a; // ADC A1 Analog Input
- assign adc_a0_a = 0.0;
- assign adc_a1_a = 0.0;
- awire pad2ast_t0_a; // T0 Analog Input
- awire pad2ast_t1_a; // T1 Analog Input
- assign pad2ast_t0_a = 0.0;
- assign pad2ast_t1_a = 0.0;
-`else
- wire adc_a0_a; // ADC A0 Analog Input
- wire adc_a1_a; // ADC A1 Analog Input
- assign adc_a0_a = 1'b0;
- assign adc_a1_a = 1'b0;
- wire pad2ast_t0_a; // T0 Analog Input
- wire pad2ast_t1_a; // T1 Analog Input
- assign pad2ast_t0_a = 1'b0;
- assign pad2ast_t1_a = 1'b0;
-`endif
-`else
- wire adc_a0_a; // ADC A0 Analog Input
- wire adc_a1_a; // ADC A1 Analog Input
- assign adc_a0_a = 1'b0;
- assign adc_a1_a = 1'b0;
- wire pad2ast_t0_a; // T0 Analog Input
- wire pad2ast_t1_a; // T1 Analog Input
- assign pad2ast_t0_a = 1'b0;
- assign pad2ast_t1_a = 1'b0;
-`endif
-
-
- ast #(
- .EntropyStreams(EntropyStreams),
- .AdcChannels(AdcChannels),
- .AdcDataWidth(AdcDataWidth),
- .UsbCalibWidth(UsbCalibWidth)
- ) i_ast (
- // ast interface and sync clocks / rests
- .clk_ast_adc_i(1'b0), // not yet in design
- .clk_ast_rng_i(1'b0), // not yet in design
- .clk_ast_usb_i(clks_ast_i.clk_ast_usbdev_usb_peri),
- .clk_ast_es_i(1'b0), // not yet in design
- // sensor control acts as both the alert interface and the tlul // front-end
- .clk_ast_alert_i(clks_ast_i.clk_ast_sensor_ctrl_aon_io_div4_secure),
- .clk_ast_tlul_i(clks_ast_i.clk_ast_sensor_ctrl_aon_io_div4_secure),
- .rst_ast_adc_ni(1'b0), // not yet in design
- .rst_ast_rng_ni(1'b0), // not yet in design
- .rst_ast_usb_ni(rsts_ast_i.rst_ast_usbdev_usb_n),
- .rst_ast_es_ni(1'b0),
- .rst_ast_alert_ni(rsts_ast_i.rst_ast_sensor_ctrl_aon_sys_io_div4_n),
- .rst_ast_tlul_ni(rsts_ast_i.rst_ast_sensor_ctrl_aon_sys_io_div4_n),
-
- // tlul if
- .tl_i(bus_i),
- .tl_o(bus_o),
-
- // power related
- .por_ni,
- .vcaon_pok_o(rst_o.aon_pok),
- .vcmain_pok_o(pwr_o.main_pok),
- .vioa_pok_o(status_o.io_pok[0]),
- .viob_pok_o(status_o.io_pok[1]),
- .main_pd_ni(pwr_i.main_pd_n),
- .main_iso_en_i(pwr_i.pwr_clamp),
-
- // power OK control (for debug only). pok signal follows these inputs
- .vcc_supp_i(1'b1), // VCC Supply Test
- .vcmain_supp_i(1'b1), // MAIN Supply Test
- .vcaon_supp_i(1'b1), // AON Supply Test
- .vioa_supp_i(1'b1), // IO Rails Supply Test
- .viob_supp_i(1'b1), // IO Rails Supply Test
-
- // output clocks and associated controls
- .clk_src_sys_o(clks_o.clk_sys),
- .clk_src_sys_val_o(core_clk_val),
- .clk_src_sys_en_i(pwr_i.core_clk_en),
- .clk_src_sys_jen_i(1'b0), // need to add function in clkmgr
-
- .clk_src_aon_o(clks_o.clk_aon),
- .clk_src_aon_val_o(slow_clk_val),
-
- .clk_src_usb_o(clks_o.clk_usb),
- .clk_src_usb_val_o(usb_clk_val),
- .clk_src_usb_en_i(pwr_i.usb_clk_en),
-
- .clk_src_io_o(clks_o.clk_io),
- .clk_src_io_val_o(io_clk_val),
- .clk_src_io_en_i(pwr_i.io_clk_en),
-
- // input clock and references for calibration
- .clk_ast_ext_i(clk_ext_i),
- .usb_ref_pulse_i,
- .usb_ref_val_i,
-
- // ADC interface
- .adc_a0_ai(adc_a0_a),
- .adc_a1_ai(adc_a1_a),
- .adc_chnsel_i(adc_i.channel_sel),
- .adc_pd_i(adc_i.pd),
- .adc_d_o(adc_o.data),
- .adc_d_val_o(adc_o.data_valid),
-
- // entropy source interface
- .rng_en_i(es_i.rng_enable),
- .rng_val_o(es_o.rng_valid),
- .rng_b_o(es_o.rng_b),
-
- // entropy distribution interface - need to hookup later
- .entropy_req_o(),
- .entropy_ack_i('0),
- .entropy_i('0),
-
- // alerts
- .as_alert_po(alert_o.alerts_p[sensor_ctrl_reg_pkg::AsSel]),
- .as_alert_no(alert_o.alerts_n[sensor_ctrl_reg_pkg::AsSel]),
- .cg_alert_po(alert_o.alerts_p[sensor_ctrl_reg_pkg::CgSel]),
- .cg_alert_no(alert_o.alerts_n[sensor_ctrl_reg_pkg::CgSel]),
- .gd_alert_po(alert_o.alerts_p[sensor_ctrl_reg_pkg::GdSel]),
- .gd_alert_no(alert_o.alerts_n[sensor_ctrl_reg_pkg::GdSel]),
- .ts_alert_hi_po(alert_o.alerts_p[sensor_ctrl_reg_pkg::TsHiSel]),
- .ts_alert_hi_no(alert_o.alerts_n[sensor_ctrl_reg_pkg::TsHiSel]),
- .ts_alert_lo_po(alert_o.alerts_p[sensor_ctrl_reg_pkg::TsLoSel]),
- .ts_alert_lo_no(alert_o.alerts_n[sensor_ctrl_reg_pkg::TsLoSel]),
- .ls_alert_po(alert_o.alerts_p[sensor_ctrl_reg_pkg::LsSel]),
- .ls_alert_no(alert_o.alerts_n[sensor_ctrl_reg_pkg::LsSel]),
- .ot_alert_po(alert_o.alerts_p[sensor_ctrl_reg_pkg::OtSel]),
- .ot_alert_no(alert_o.alerts_n[sensor_ctrl_reg_pkg::OtSel]),
- .as_alert_ack_i(alert_i.alerts_ack[sensor_ctrl_reg_pkg::AsSel]),
- .cg_alert_ack_i(alert_i.alerts_ack[sensor_ctrl_reg_pkg::CgSel]),
- .gd_alert_ack_i(alert_i.alerts_ack[sensor_ctrl_reg_pkg::GdSel]),
- .ts_alert_hi_ack_i(alert_i.alerts_ack[sensor_ctrl_reg_pkg::TsHiSel]),
- .ts_alert_lo_ack_i(alert_i.alerts_ack[sensor_ctrl_reg_pkg::TsLoSel]),
- .ls_alert_ack_i(alert_i.alerts_ack[sensor_ctrl_reg_pkg::LsSel]),
- .ot_alert_ack_i(alert_i.alerts_ack[sensor_ctrl_reg_pkg::OtSel]),
- .as_alert_trig_i(alert_i.alerts_trig[sensor_ctrl_reg_pkg::AsSel]),
- .cg_alert_trig_i(alert_i.alerts_trig[sensor_ctrl_reg_pkg::CgSel]),
- .gd_alert_trig_i(alert_i.alerts_trig[sensor_ctrl_reg_pkg::GdSel]),
- .ts_alert_hi_trig_i(alert_i.alerts_trig[sensor_ctrl_reg_pkg::TsHiSel]),
- .ts_alert_lo_trig_i(alert_i.alerts_trig[sensor_ctrl_reg_pkg::TsLoSel]),
- .ls_alert_trig_i(alert_i.alerts_trig[sensor_ctrl_reg_pkg::LsSel]),
- .ot_alert_trig_i(alert_i.alerts_trig[sensor_ctrl_reg_pkg::OtSel]),
-
- // flash interface
- .flash_power_down_h_o(ast_eflash_o.flash_power_down_h),
- .flash_power_ready_h_o(ast_eflash_o.flash_power_ready_h),
-
- // analog debug signals
- .ast2pad_a_io(),
-
- // pad mux related - DFT
- .ast2padmux_o(), // DFT_2_IO Output Signals
- .padmux2ast_i('0), // IO_2_DFT Input Signals
-
- // usb IO calib
- .usb_io_pu_cal_o, // USB IO Pull-up Calibration Setting
-
- // dft related
- .scan_mode_i(scanmode_i),
- .scan_reset_ni
- );
-
- // TODO hook-up to ast
- assign ast_eflash_o.flash_bist_enable = lc_ctrl_pkg::Off;
-
-endmodule // ast_wrapper
-
-//lc_ctrl_pkg::lc_tx_t flash_bist_en_o;
-//assign ast_eflash_o.flash_bist_enable = (flash_bist_en_o == lc_ctrl_pkg::On);
-//
-//ast_pkg::ast_dif_t as_alert_o;
-//assign alert_o.alerts_p[sensor_ctrl_reg_pkg::AsSel] = as_alert_o.p;
-//assign alert_o.alerts_n[sensor_ctrl_reg_pkg::AsSel] = as_alert_o.n;
-//
-//ast_pkg::ast_dif_t cg_alert_o;
-//assign alert_o.alerts_p[sensor_ctrl_reg_pkg::CgSel] = cg_alert_o.p;
-//assign alert_o.alerts_n[sensor_ctrl_reg_pkg::CgSel] = cg_alert_o.n;
-//
-//ast_pkg::ast_dif_t gd_alert_o;
-//assign alert_o.alerts_p[sensor_ctrl_reg_pkg::GdSel] = gd_alert_o.p;
-//assign alert_o.alerts_n[sensor_ctrl_reg_pkg::GdSel] = gd_alert_o.n;
-//
-//ast_pkg::ast_dif_t ts_alert_hi_o;
-//assign alert_o.alerts_p[sensor_ctrl_reg_pkg::TsHiSel] = ts_alert_hi_o.p;
-//assign alert_o.alerts_n[sensor_ctrl_reg_pkg::TsHiSel] = ts_alert_hi_o.n;
-//
-//ast_pkg::ast_dif_t ts_alert_lo_o;
-//assign alert_o.alerts_p[sensor_ctrl_reg_pkg::TsLoSel] = ts_alert_lo_o.p;
-//assign alert_o.alerts_n[sensor_ctrl_reg_pkg::TsLoSel] = ts_alert_lo_o.n;
-//
-//ast_pkg::ast_dif_t ls_alert_o;
-//assign alert_o.alerts_p[sensor_ctrl_reg_pkg::LsSel] = ls_alert_o.p;
-//assign alert_o.alerts_n[sensor_ctrl_reg_pkg::LsSel] = ls_alert_o.n;
-//
-//ast_pkg::ast_dif_t ot_alert_o;
-//assign alert_o.alerts_p[sensor_ctrl_reg_pkg::OtSel] = ot_alert_o.p;
-//assign alert_o.alerts_n[sensor_ctrl_reg_pkg::OtSel] = ot_alert_o.n;
-//
-////~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//// Module: 'ast' - Jun 25, 2020. 'vinst.pl' Rev 1.06
-////~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//ast #(
-///*P*/ .EntropyStreams ( EntropyStreams ),
-///*P*/ .AdcChannels ( AdcChannels ),
-///*P*/ .AdcDataWidth ( AdcDataWidth ),
-///*P*/ .UsbCalibWidth ( UsbCalibWidth ),
-///*P*/ .Ast2PadOutWidth ( 10 ), //TODO: Assign
-///*P*/ .Pad2AstInWidth ( 10 ) //TODO: Assign
-//) u_ast (
-// // tlul
-///*I*/ .tl_i ( bus_i ),
-///*O*/ .tl_o ( bus_o ),
-// // buffered clocks & resets
-///*I*/ .clk_ast_adc_i ( 1'b0 ), // Not yet in the design
-///*I*/ .rst_ast_adc_ni ( 1'b0 ), // Not yet in the design
-///*I*/ .clk_ast_alert_i ( clks_ast_i.clk_ast_sensor_ctrl_io_div4_secure ),
-///*I*/ .rst_ast_alert_ni ( rsts_ast_i.rst_ast_sensor_ctrl_sys_io_div4_n ), //JL TODO
-///*I*/ .clk_ast_es_i ( 1'b0 ), // Not yet in the design
-///*I*/ .rst_ast_es_ni ( 1'b0 ), // Not yet in the design
-///*I*/ .clk_ast_rng_i ( 1'b0 ), // Not yet in the design
-///*I*/ .rst_ast_rng_ni ( 1'b0 ), // Not yet in the design
-///*I*/ .clk_ast_tlul_i ( clks_ast_i.clk_ast_sensor_ctrl_io_div4_secure ),
-///*I*/ .rst_ast_tlul_ni ( rsts_ast_i.rst_ast_sensor_ctrl_sys_io_div4_n ), //JL TODO
-///*I*/ .clk_ast_usb_i ( clks_ast_i.clk_ast_usbdev_usb_peri ),
-///*I*/ .rst_ast_usb_ni ( rsts_ast_i.rst_ast_usbdev_usb_n ), //JL TODO
-///*I*/ .clk_ast_ext_i ( clk_ext_i ),
-///*I*/ .por_ni ( por_ni ),
-// // pok test
-///*I*/ .vcc_supp_i ( 1'b1 ), // VCC Supply Test
-///*I*/ .vcaon_supp_i ( 1'b1 ), // AON Supply Test
-///*I*/ .vcmain_supp_i ( 1'b1 ), // MAIN Supply Test
-///*I*/ .vioa_supp_i ( 1'b1 ), // IO Rails Supply Test
-///*I*/ .viob_supp_i ( 1'b1 ), // IO Rails Supply Test
-// // pok
-///*O*/ .vcaon_pok_o ( rst_o.aon_pok ),
-///*O*/ .vcmain_pok_o ( pwr_o.main_pok ),
-///*O*/ .vioa_pok_o ( status_o.io_pok[0] ),
-///*O*/ .viob_pok_o ( status_o.io_pok[1] ),
-// // main regulator
-///*I*/ .main_iso_en_i ( pwr_i.pwr_clamp ),
-///*I*/ .main_pd_ni ( pwr_i.main_pd_n ),
-// // pdm control (flash)/otp
-///*O*/ .flash_power_down_h_o ( ast_eflash_o.flash_power_down_h ),
-///*O*/ .flash_power_ready_h_o ( ast_eflash_o.flash_power_ready_h ),
-///*I*/ .otp_power_seq_i ( 2'b00 ), //TODO: Connect
-///*O*/ .otp_power_seq_h_o ( ), //TODO: Connect
-// // system source clock
-///*I*/ .clk_src_sys_en_i ( pwr_i.core_clk_en ),
-///*I*/ .clk_src_sys_jen_i ( 1'b0 ), // need to add function in clkmgr
-///*O*/ .clk_src_sys_o ( clks_o.clk_sys ),
-///*O*/ .clk_src_sys_val_o ( core_clk_val ),
-// // aon source clock
-///*O*/ .clk_src_aon_o ( clks_o.clk_aon ),
-///*O*/ .clk_src_aon_val_o ( slow_clk_val ),
-// // io source clock
-///*I*/ .clk_src_io_en_i ( pwr_i.io_clk_en ),
-///*O*/ .clk_src_io_o ( clks_o.clk_io ),
-///*O*/ .clk_src_io_val_o ( io_clk_val ),
-// // usb source clock
-///*I*/ .usb_ref_pulse_i ( usb_ref_pulse_i ),
-///*I*/ .usb_ref_val_i ( usb_ref_val_i ),
-///*I*/ .clk_src_usb_en_i ( pwr_i.usb_clk_en ),
-///*O*/ .clk_src_usb_o ( clks_o.clk_usb ),
-///*O*/ .clk_src_usb_val_o ( usb_clk_val ),
-///*O*/ .usb_io_pu_cal_o, // USB IO Pull-up Calibration Setting
-// // adc
-///*I*/ .adc_pd_i ( adc_i.pd ),
-///*I*/ .adc_a0_ai ( adc_a0_a ),
-///*I*/ .adc_a1_ai ( adc_a1_a ),
-///*I*/ .adc_chnsel_i ( adc_i.channel_sel ),
-///*O*/ .adc_d_o ( adc_o.data ),
-///*O*/ .adc_d_val_o ( adc_o.data_valid ),
-// // rng
-///*I*/ .rng_en_i ( es_i.rng_enable ),
-///*O*/ .rng_val_o ( es_o.rng_valid ),
-///*O*/ .rng_b_o ( es_o.rng_b ),
-// // entropy
-///*I*/ .entropy_rsp_i ( '{edn_ack: 1'b0, edn_fips: 1'b1, edn_bus: '0} ),
-///*O*/ .entropy_req_o ( ), //TODO: Connect
-// // alerts
-///*I*/ .as_alert_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*I*/ .as_alert_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*O*/ .as_alert_o ( as_alert_o ),
-///*I*/ .cg_alert_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*I*/ .cg_alert_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*O*/ .cg_alert_o ( cg_alert_o ),
-///*I*/ .gd_alert_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*I*/ .gd_alert_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*O*/ .gd_alert_o ( gd_alert_o ),
-///*I*/ .ts_alert_hi_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*I*/ .ts_alert_hi_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*O*/ .ts_alert_hi_o ( ts_alert_hi_o ),
-///*I*/ .ts_alert_lo_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*I*/ .ts_alert_lo_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*O*/ .ts_alert_lo_o ( ts_alert_lo_o ),
-///*I*/ .ls_alert_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*I*/ .ls_alert_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*O*/ .ls_alert_o ( ls_alert_o ),
-///*I*/ .ot_alert_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*I*/ .ot_alert_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
-///*O*/ .ot_alert_o ( ot_alert_o ),
-// // dft
-///*I*/ .dft_strap_test_i ( '{valid: 1'b0, straps: 2'b00} ), //TODO: Connect
-///*I*/ .lc_dft_en_i ( lc_ctrl_pkg::On ), //TODO: Connect
-// // pad mux related
-///*I*/ .padmux2ast_i ( '0 ), //TODO: Connect
-///*O*/ .ast2padmux_o ( ), //TODO: Connect
-///*I*/ .pad2ast_t0_ai ( pad2ast_t0_a ), //TODO: Connect
-///*I*/ .pad2ast_t1_ai ( pad2ast_t1_a ), //TODO: Connect
-///*O*/ .ast2pad_t0_ao ( ), //TODO: Connect
-///*O*/ .ast2pad_t1_ao ( ), //TODO: Connect
-// //
-///*I*/ .lc_clk_byp_req_i ( lc_ctrl_pkg::Off ), //TODO: Connect
-///*O*/ .lc_clk_byp_ack_o ( ), //TODO: Connect
-///*O*/ .flash_bist_en_o ( flash_bist_en_o ), //TODO: Connect
-// //
-///*O*/ .dpram_rmf_o ( ), //TODO: Connect
-///*O*/ .dpram_rml_o ( ), //TODO: Connect
-///*O*/ .spram_rm_o ( ), //TODO: Connect
-///*O*/ .sprgf_rm_o ( ), //TODO: Connect
-///*O*/ .sprom_rm_o ( ), //TODO: Connect
-// // scan
-///*O*/ .dft_scan_md_o ( ), //TODO: Connect
-///*O*/ .scan_shift_en_o ( ), //TODO: Connect
-///*O*/ .scan_reset_no ( ) //TODO: Connect
-//);
-//// end of u_ast
-//
-//
-//
-//endmodule : ast_wrapper
-//>>>>>>> 05149b668 ([ast] Added DFT interface + logic updates)
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_wrapper_pkg.sv b/hw/top_earlgrey/ip/ast/rtl/ast_wrapper_pkg.sv
deleted file mode 100644
index aa2f935..0000000
--- a/hw/top_earlgrey/ip/ast/rtl/ast_wrapper_pkg.sv
+++ /dev/null
@@ -1,72 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-
-package ast_wrapper_pkg;
-
- parameter int NumAlerts = top_pkg::NUM_AST_ALERTS;
- parameter int NumIoRails = top_pkg::NUM_IO_RAILS;
- parameter int EntropyStreams = top_pkg::ENTROPY_STREAM;
- parameter int AdcChannels = top_pkg::ADC_CHANNELS;
- parameter int AdcDataWidth = top_pkg::ADC_DATAW;
- parameter int UsbCalibWidth = 16;
-
- // The following structs should eventually be relocted to other modules
- typedef struct packed {
- logic [AdcChannels-1:0] channel_sel;
- logic pd;
- } adc_ast_req_t;
-
- typedef struct packed {
- logic [AdcDataWidth-1:0] data;
- logic data_valid;
- } adc_ast_rsp_t;
-
- typedef struct packed {
- logic aon_pok;
- } ast_rst_t;
-
- parameter ast_rst_t AST_RST_DEFAULT = '{
- aon_pok: 1'b1
- };
-
- typedef struct packed {
- logic clk_sys;
- logic clk_io;
- logic clk_usb;
- logic clk_aon;
- } ast_clks_t;
-
- typedef struct packed {
- logic [NumAlerts-1:0] alerts_p;
- logic [NumAlerts-1:0] alerts_n;
- } ast_alert_req_t;
-
- typedef struct packed {
- logic [NumAlerts-1:0] alerts_ack;
- logic [NumAlerts-1:0] alerts_trig;
- } ast_alert_rsp_t;
-
- typedef struct packed {
- logic [NumIoRails-1:0] io_pok;
- } ast_status_t;
-
- // Ack mode enumerations
- typedef enum logic {
- ImmAck = 0,
- SwAck = 1
- } ast_ack_mode_e;
-
- parameter ast_alert_req_t AST_ALERT_REQ_DEFAULT = '{
- alerts_p: '0,
- alerts_n: {NumAlerts{1'b1}}
- };
-
- typedef struct packed {
- lc_ctrl_pkg::lc_tx_t flash_bist_enable;
- logic flash_power_down_h;
- logic flash_power_ready_h;
- } ast_eflash_t;
-
-endpackage // ast_wrapper_pkg
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
index 8a0a1b2..5f409d1 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -450,6 +450,8 @@
assign clocks_ast_o.clk_ast_usbdev_aon_peri = clocks_o.clk_aon_peri;
assign clocks_ast_o.clk_ast_usbdev_usb_peri = clocks_o.clk_usb_peri;
assign clocks_ast_o.clk_ast_sensor_ctrl_aon_io_div4_secure = clocks_o.clk_io_div4_secure;
+ assign clocks_ast_o.clk_ast_entropy_src_main_secure = clocks_o.clk_main_secure;
+ assign clocks_ast_o.clk_ast_edn0_main_secure = clocks_o.clk_main_secure;
////////////////////////////////////////////////////
// Assertions
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
index 9652869..3227a95 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
@@ -49,6 +49,8 @@
logic clk_ast_usbdev_aon_peri;
logic clk_ast_usbdev_usb_peri;
logic clk_ast_sensor_ctrl_aon_io_div4_secure;
+ logic clk_ast_entropy_src_main_secure;
+ logic clk_ast_edn0_main_secure;
} clkmgr_ast_out_t;
typedef struct packed {
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
index 50887c2..ed2bed5 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -695,6 +695,8 @@
assign resets_ast_o.rst_ast_usbdev_sys_aon_n = resets_o.rst_sys_aon_n;
assign resets_ast_o.rst_ast_usbdev_usb_n = resets_o.rst_usb_n;
assign resets_ast_o.rst_ast_sensor_ctrl_aon_sys_io_div4_n = resets_o.rst_sys_io_div4_n;
+ assign resets_ast_o.rst_ast_entropy_src_sys_n = resets_o.rst_sys_n;
+ assign resets_ast_o.rst_ast_edn0_sys_n = resets_o.rst_sys_n;
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
index 8c1737a..85dc87b 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
@@ -72,6 +72,8 @@
logic [PowerDomains-1:0] rst_ast_usbdev_sys_aon_n;
logic [PowerDomains-1:0] rst_ast_usbdev_usb_n;
logic [PowerDomains-1:0] rst_ast_sensor_ctrl_aon_sys_io_div4_n;
+ logic [PowerDomains-1:0] rst_ast_entropy_src_sys_n;
+ logic [PowerDomains-1:0] rst_ast_edn0_sys_n;
} rstmgr_ast_out_t;
// default value for rstmgr_ast_rsp_t (for dangling ports)
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson b/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson
index 9d01c41..122180a 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson
+++ b/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson
@@ -94,7 +94,7 @@
]
- // Define ast_wrapper struct package
+ // Define ast_struct package
inter_signal_list: [
// should be defined by ast wrapper later
@@ -102,7 +102,7 @@
type: "req_rsp",
name: "ast_alert",
act: "rsp",
- package: "ast_wrapper_pkg",
+ package: "ast_pkg",
},
// should be defined by ast wrapper later
@@ -110,7 +110,7 @@
type: "uni",
name: "ast_status",
act: "rcv",
- package: "ast_wrapper_pkg",
+ package: "ast_pkg",
},
],
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv
index 9be6cee..207340f 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv
+++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv
@@ -18,9 +18,9 @@
output tlul_pkg::tl_d2h_t tl_o,
// Interface from AST
- input ast_wrapper_pkg::ast_alert_req_t ast_alert_i,
- output ast_wrapper_pkg::ast_alert_rsp_t ast_alert_o,
- input ast_wrapper_pkg::ast_status_t ast_status_i,
+ input ast_pkg::ast_alert_req_t ast_alert_i,
+ output ast_pkg::ast_alert_rsp_t ast_alert_o,
+ input ast_pkg::ast_status_t ast_status_i,
// Alerts
input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
@@ -60,7 +60,11 @@
// While the alerts are differential, they are not perfectly aligned.
// Instead, each alert is treated independently.
- assign alerts_vld = ast_alert_i.alerts_p | ~ast_alert_i.alerts_n;
+ always_comb begin
+ for (int i = 0; i < NumAlerts; i++) begin
+ alerts_vld[i] = ast_alert_i.alerts[i].p | ~ast_alert_i.alerts[i].n;
+ end
+ end
// alert test connection
assign alert_test[AsSel] = reg2hw.alert_test.recov_as.qe & reg2hw.alert_test.recov_as.q;
@@ -109,13 +113,19 @@
// When in immediate ack mode, ack alerts as they are received by the sender
// When in software ack mode, only ack when software issues the command to clear alert_state
always_comb begin
- ast_alert_o.alerts_ack = '0;
for (int i = 0; i < NumAlerts; i++) begin
- ast_alert_o.alerts_ack[i] = alerts_clr[i];
+ ast_alert_o.alerts_ack[i].p = alerts_clr[i];
+ ast_alert_o.alerts_ack[i].n = ~alerts_clr[i];
end
end
// alert trigger for test
- assign ast_alert_o.alerts_trig = reg2hw.alert_trig;
+ always_comb begin
+ for (int i = 0; i < NumAlerts; i++) begin
+ ast_alert_o.alerts_trig[i].p = reg2hw.alert_trig[i];
+ ast_alert_o.alerts_trig[i].n = ~reg2hw.alert_trig[i];
+ end
+ end
+
endmodule // sensor_ctrl
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/sensor_ctrl_pkg.core b/hw/top_earlgrey/ip/sensor_ctrl/sensor_ctrl_pkg.core
index 6849b9e..800ece1 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/sensor_ctrl_pkg.core
+++ b/hw/top_earlgrey/ip/sensor_ctrl/sensor_ctrl_pkg.core
@@ -9,7 +9,7 @@
files_rtl:
depend:
- lowrisc:constants:top_pkg
- - lowrisc:systems:ast_wrapper_pkg
+ - lowrisc:systems:ast_pkg
- lowrisc:systems:sensor_ctrl_reg
files:
- rtl/sensor_ctrl_pkg.sv
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 48cf7db..efcc279 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -61,9 +61,9 @@
input rstmgr_pkg::rstmgr_ast_t rstmgr_ast_i,
output pwrmgr_pkg::pwr_ast_req_t pwrmgr_ast_req_o,
input pwrmgr_pkg::pwr_ast_rsp_t pwrmgr_ast_rsp_i,
- input ast_wrapper_pkg::ast_alert_req_t sensor_ctrl_ast_alert_req_i,
- output ast_wrapper_pkg::ast_alert_rsp_t sensor_ctrl_ast_alert_rsp_o,
- input ast_wrapper_pkg::ast_status_t sensor_ctrl_ast_status_i,
+ input ast_pkg::ast_alert_req_t sensor_ctrl_ast_alert_req_i,
+ output ast_pkg::ast_alert_rsp_t sensor_ctrl_ast_alert_rsp_o,
+ input ast_pkg::ast_status_t sensor_ctrl_ast_status_i,
output logic usbdev_usb_ref_val_o,
output logic usbdev_usb_ref_pulse_o,
output tlul_pkg::tl_h2d_t ast_tl_req_o,
@@ -75,6 +75,10 @@
input logic flash_power_ready_h_i,
input logic [3:0] flash_test_mode_a_i,
input logic flash_test_voltage_h_i,
+ output entropy_src_pkg::entropy_src_rng_req_t es_rng_req_o,
+ input entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp_i,
+ output lc_ctrl_pkg::lc_tx_t lc_clk_byp_req_o,
+ input lc_ctrl_pkg::lc_tx_t lc_clk_byp_ack_i,
input edn_pkg::edn_req_t ast_edn_edn_req_i,
output edn_pkg::edn_rsp_t ast_edn_edn_rsp_o,
output clkmgr_pkg::clkmgr_ast_out_t clks_ast_o,
@@ -429,7 +433,6 @@
lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_cpu_en;
lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_escalate_en;
lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_check_byp_en;
- lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_clk_byp_req;
lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_clk_byp_ack;
lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_creator_seed_sw_rw_en;
lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_owner_seed_sw_rw_en;
@@ -1356,7 +1359,7 @@
.lc_cpu_en_o(lc_ctrl_lc_cpu_en),
.lc_keymgr_en_o(),
.lc_escalate_en_o(lc_ctrl_lc_escalate_en),
- .lc_clk_byp_req_o(lc_ctrl_lc_clk_byp_req),
+ .lc_clk_byp_req_o(lc_clk_byp_req_o),
.lc_clk_byp_ack_i(lc_ctrl_lc_clk_byp_ack),
.lc_flash_rma_req_o(flash_ctrl_rma_req),
.lc_flash_rma_seed_o(flash_ctrl_rma_seed),
@@ -1488,7 +1491,7 @@
// Inter-module signals
.clocks_o(clkmgr_aon_clocks),
- .ast_clk_bypass_ack_i(lc_ctrl_pkg::LC_TX_DEFAULT),
+ .ast_clk_bypass_ack_i(lc_clk_byp_ack_i),
.lc_clk_bypass_ack_o(lc_ctrl_lc_clk_byp_ack),
.clk_main_i(clk_main_i),
.clk_io_i(clk_io_i),
@@ -1836,8 +1839,8 @@
// Inter-module signals
.entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
.entropy_src_hw_if_o(csrng_entropy_src_hw_if_rsp),
- .entropy_src_rng_o(),
- .entropy_src_rng_i(entropy_src_pkg::ENTROPY_SRC_RNG_RSP_DEFAULT),
+ .entropy_src_rng_o(es_rng_req_o),
+ .entropy_src_rng_i(es_rng_rsp_i),
.entropy_src_xht_o(),
.entropy_src_xht_i(entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT),
.efuse_es_sw_reg_en_i('0),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
index e98de0e..e2e7484 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
@@ -139,13 +139,6 @@
.dio_attr_i ( dio_attr )
);
- // TODO: Do I need the imports?
- // For nettype real awire;
- import ana_pkg::*;
- // For new typdef's
- import ast_pkg::*;
-
-
//////////////////////
// JTAG Overlay Mux //
//////////////////////
@@ -202,62 +195,14 @@
//////////////////////
// AST //
//////////////////////
-//tlul_pkg::tl_h2d_t base_ast_bus;
-//tlul_pkg::tl_d2h_t ast_base_bus;
-//ast_wrapper_pkg::ast_status_t ast_base_status;
-//ast_wrapper_pkg::ast_alert_req_t ast_base_alerts;
-//ast_wrapper_pkg::ast_alert_rsp_t base_ast_alerts;
-//ast_wrapper_pkg::ast_rst_t ast_base_rst;
-//ast_wrapper_pkg::ast_clks_t ast_base_clks;
-//ast_wrapper_pkg::ast_eflash_t ast_base_eflash;
-//pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
-//pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
-//clkmgr_pkg::clkmgr_ast_out_t clks_ast;
-//rstmgr_pkg::rstmgr_ast_out_t rsts_ast;
-//otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq;
-//otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h;
-////ast_wrapper_pkg::ast_func_clks_rsts base_ast_aux;
-//logic usb_ref_pulse;
-//logic usb_ref_val;
-//
-//// TODO: connect once available in AST
-//logic unused_otp_ctrl_otp_ast_pwr_seq;
-//assign unused_otp_ctrl_otp_ast_pwr_seq = otp_ctrl_otp_ast_pwr_seq;
-//assign otp_ctrl_otp_ast_pwr_seq_h = '0;
-//
-//ast_wrapper ast_wrapper (
-// .clk_ext_i(clk),
-// .por_ni(rst_n),
-// .bus_i(base_ast_bus),
-// .bus_o(ast_base_bus),
-// .pwr_i(base_ast_pwr),
-// .pwr_o(ast_base_pwr),
-// .rst_o(ast_base_rst),
-// .clks_o(ast_base_clks),
-// .usb_ref_pulse_i(usb_ref_pulse),
-// .usb_ref_val_i(usb_ref_val),
-// .clks_ast_i(clks_ast),
-// .rsts_ast_i(rsts_ast),
-// .adc_i('0),
-// .adc_o(),
-// .es_i('0), // not in top_earlgrey
-// .es_o(), // not in top_earlgrey
-// .alert_i(base_ast_alerts),
-// .alert_o(ast_base_alerts),
-// .status_o(ast_base_status),
-// .usb_io_pu_cal_o(),
-// .ast_eflash_o(ast_base_eflash),
-// .scanmode_i(1'b0),
-// .scan_reset_ni(1'b1)
-//);
-
// TLUL interface
tlul_pkg::tl_h2d_t base_ast_bus;
tlul_pkg::tl_d2h_t ast_base_bus;
// assorted ast status
- ast_pkg::ast_status_t status_o;
+ ast_pkg::ast_status_t ast_status;
+ // ast clocks and resets
ast_pkg::ast_rst_t ast_base_rst;
ast_pkg::ast_clks_t ast_base_clks;
@@ -283,221 +228,173 @@
// entropy source interface
// The entropy source pacakge definition should eventually be moved to es
- entropy_src_pkg::entropy_src_rng_req_t es_i;
- entropy_src_pkg::entropy_src_rng_rsp_t es_o;
+ entropy_src_pkg::entropy_src_rng_req_t es_rng_req;
+ entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp;
+
+ // entropy distribution network
+ edn_pkg::edn_req_t ast_edn_edn_req;
+ edn_pkg::edn_rsp_t ast_edn_edn_rsp;
// alerts interface
- ast_pkg::ast_alert_rsp_t alert_i;
- ast_pkg::ast_alert_req_t alert_o;
+ ast_pkg::ast_alert_rsp_t ast_alert_rsp;
+ ast_pkg::ast_alert_req_t ast_alert_req;
- // Switch these to prim_mux cells
- logic core_clk_val;
- assign ast_base_pwr.core_clk_val = core_clk_val ? pwrmgr_pkg::DiffValid :
- pwrmgr_pkg::DiffInvalid;
- logic slow_clk_val;
- assign ast_base_pwr.slow_clk_val = slow_clk_val ? pwrmgr_pkg::DiffValid :
- pwrmgr_pkg::DiffInvalid;
- logic io_clk_val;
- assign ast_base_pwr.io_clk_val = io_clk_val ? pwrmgr_pkg::DiffValid :
- pwrmgr_pkg::DiffInvalid;
- logic usb_clk_val;
- assign ast_base_pwr.usb_clk_val = usb_clk_val ? pwrmgr_pkg::DiffValid :
- pwrmgr_pkg::DiffInvalid;
+ // Flash connections
+ lc_ctrl_pkg::lc_tx_t flash_bist_enable;
+ logic flash_power_down_h;
+ logic flash_power_ready_h;
-// need to hookup later
-`ifndef VERILATOR
-`ifndef SYNTHESIS
- awire adc_a0_a; // ADC A0 Analog Input
- awire adc_a1_a; // ADC A1 Analog Input
- assign adc_a0_a = 0.0;
- assign adc_a1_a = 0.0;
- awire pad2ast_t0_a; // T0 Analog Input
- awire pad2ast_t1_a; // T1 Analog Input
- assign pad2ast_t0_a = 0.0;
- assign pad2ast_t1_a = 0.0;
-`else
- wire adc_a0_a; // ADC A0 Analog Input
- wire adc_a1_a; // ADC A1 Analog Input
- assign adc_a0_a = 1'b0;
- assign adc_a1_a = 1'b0;
- wire pad2ast_t0_a; // T0 Analog Input
- wire pad2ast_t1_a; // T1 Analog Input
- assign pad2ast_t0_a = 1'b0;
- assign pad2ast_t1_a = 1'b0;
-`endif
-`else
- wire adc_a0_a; // ADC A0 Analog Input
- wire adc_a1_a; // ADC A1 Analog Input
- assign adc_a0_a = 1'b0;
- assign adc_a1_a = 1'b0;
- wire pad2ast_t0_a; // T0 Analog Input
- wire pad2ast_t1_a; // T1 Analog Input
- assign pad2ast_t0_a = 1'b0;
- assign pad2ast_t1_a = 1'b0;
-`endif
+ // Life cycle clock bypass req/ack
+ lc_ctrl_pkg::lc_tx_t lc_ast_clk_byp_req;
+ lc_ctrl_pkg::lc_tx_t lc_ast_clk_byp_ack;
- // TODO: Need to use lc_tx_t for flash_bist_enable after Dana's PR
- lc_ctrl_pkg::lc_tx_t flash_bist_en_o;
- ast_pkg::ast_eflash_t ast_base_eflash;
- assign ast_base_eflash.flash_bist_enable = (flash_bist_en_o == lc_ctrl_pkg::On);
+ // DFT connections
+ logic scan_rst_n;
+ logic scan_en;
+ lc_ctrl_pkg::lc_tx_t scanmode;
- // Typedefs adjustment...
- ast_pkg::ast_dif_t as_alert_o;
- assign alert_o.alerts_p[sensor_ctrl_reg_pkg::AsSel] = as_alert_o.p;
- assign alert_o.alerts_n[sensor_ctrl_reg_pkg::AsSel] = as_alert_o.n;
+ // Alert connections
+ import sensor_ctrl_reg_pkg::AsSel;
+ import sensor_ctrl_reg_pkg::CgSel;
+ import sensor_ctrl_reg_pkg::GdSel;
+ import sensor_ctrl_reg_pkg::TsHiSel;
+ import sensor_ctrl_reg_pkg::TsLoSel;
+ import sensor_ctrl_reg_pkg::LsSel;
+ import sensor_ctrl_reg_pkg::OtSel;
- ast_pkg::ast_dif_t cg_alert_o;
- assign alert_o.alerts_p[sensor_ctrl_reg_pkg::CgSel] = cg_alert_o.p;
- assign alert_o.alerts_n[sensor_ctrl_reg_pkg::CgSel] = cg_alert_o.n;
-
- ast_pkg::ast_dif_t gd_alert_o;
- assign alert_o.alerts_p[sensor_ctrl_reg_pkg::GdSel] = gd_alert_o.p;
- assign alert_o.alerts_n[sensor_ctrl_reg_pkg::GdSel] = gd_alert_o.n;
-
- ast_pkg::ast_dif_t ts_alert_hi_o;
- assign alert_o.alerts_p[sensor_ctrl_reg_pkg::TsHiSel] = ts_alert_hi_o.p;
- assign alert_o.alerts_n[sensor_ctrl_reg_pkg::TsHiSel] = ts_alert_hi_o.n;
-
- ast_pkg::ast_dif_t ts_alert_lo_o;
- assign alert_o.alerts_p[sensor_ctrl_reg_pkg::TsLoSel] = ts_alert_lo_o.p;
- assign alert_o.alerts_n[sensor_ctrl_reg_pkg::TsLoSel] = ts_alert_lo_o.n;
-
- ast_pkg::ast_dif_t ls_alert_o;
- assign alert_o.alerts_p[sensor_ctrl_reg_pkg::LsSel] = ls_alert_o.p;
- assign alert_o.alerts_n[sensor_ctrl_reg_pkg::LsSel] = ls_alert_o.n;
-
- ast_pkg::ast_dif_t ot_alert_o;
- assign alert_o.alerts_p[sensor_ctrl_reg_pkg::OtSel] = ot_alert_o.p;
- assign alert_o.alerts_n[sensor_ctrl_reg_pkg::OtSel] = ot_alert_o.n;
-
+ // reset domain connections
+ import rstmgr_pkg::DomainAonSel;
+ import rstmgr_pkg::Domain0Sel;
ast #(
- .EntropyStreams ( EntropyStreams ), // Parameter moved to ast_pkg.sv
- .AdcChannels ( AdcChannels ), // Parameter moved to ast_pkg.sv
- .AdcDataWidth ( AdcDataWidth ), // Parameter moved to ast_pkg.sv
- .UsbCalibWidth ( UsbCalibWidth ), // Parameter moved to ast_pkg.sv
- .Ast2PadOutWidth ( Ast2PadOutWidth ), // Parameter moved to ast_pkg.sv
- .Pad2AstInWidth ( Pad2AstInWidth ) // Parameter moved to ast_pkg.sv
+ .EntropyStreams(top_pkg::ENTROPY_STREAM),
+ .AdcChannels(top_pkg::ADC_CHANNELS),
+ .AdcDataWidth(top_pkg::ADC_DATAW),
+ .UsbCalibWidth(ast_pkg::UsbCalibWidth),
+ .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth),
+ .Pad2AstInWidth(ast_pkg::Pad2AstInWidth)
) u_ast (
// tlul
- .tl_i ( base_ast_bus ),
- .tl_o ( ast_base_bus ),
+ .tl_i ( base_ast_bus ),
+ .tl_o ( ast_base_bus ),
// buffered clocks & resets
- .clk_ast_adc_i ( 1'b0 ), // TODO: Connect
- .rst_ast_adc_ni ( 1'b0 ), // TODO: Coonect
- .clk_ast_alert_i ( clks_ast.clk_ast_sensor_ctrl_io_div4_secure ),
- // TODO: Which reset domain? See GH issue #5022
- .rst_ast_alert_ni ( rsts_ast.rst_ast_sensor_ctrl_sys_io_div4_n[0] ),
- .clk_ast_es_i ( 1'b0 ), // TODO: Connect
- .rst_ast_es_ni ( 1'b0 ), // TODO: Connect
- .clk_ast_rng_i ( 1'b0 ), // TODO: Connect
- .rst_ast_rng_ni ( 1'b0 ), // TODO: Connect
- .clk_ast_tlul_i ( clks_ast.clk_ast_sensor_ctrl_io_div4_secure ),
- // TODO: Which reset domain? See GH issue #5022
- .rst_ast_tlul_ni ( rsts_ast.rst_ast_sensor_ctrl_sys_io_div4_n[0] ),
- .clk_ast_usb_i ( clks_ast.clk_ast_usbdev_usb_peri ),
- // TODO: which reset domain? See GH issue #5022
- .rst_ast_usb_ni ( rsts_ast.rst_ast_usbdev_usb_n[0] ),
- .clk_ast_ext_i ( clk ),
- .por_ni ( rst_n ),
+ // Reset domain connection is manual at the moment
+ .clk_ast_adc_i ( 1'b0 ),
+ .rst_ast_adc_ni ( 1'b0 ),
+ .clk_ast_alert_i ( clks_ast.clk_ast_sensor_ctrl_aon_io_div4_secure ),
+ .rst_ast_alert_ni ( rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[DomainAonSel] ),
+ .clk_ast_es_i ( clks_ast.clk_ast_edn0_main_secure ),
+ .rst_ast_es_ni ( rsts_ast.rst_ast_edn0_sys_n[Domain0Sel] ),
+ .clk_ast_rng_i ( clks_ast.clk_ast_entropy_src_main_secure ),
+ .rst_ast_rng_ni ( rsts_ast.rst_ast_entropy_src_sys_n[Domain0Sel] ),
+ .clk_ast_tlul_i ( clks_ast.clk_ast_sensor_ctrl_aon_io_div4_secure ),
+ .rst_ast_tlul_ni ( rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[DomainAonSel] ),
+ .clk_ast_usb_i ( clks_ast.clk_ast_usbdev_usb_peri ),
+ .rst_ast_usb_ni ( rsts_ast.rst_ast_usbdev_usb_n[Domain0Sel] ),
+ .clk_ast_ext_i ( clk ),
+ .por_ni ( rst_n ),
// pok test for FPGA
- .vcc_supp_i ( 1'b1 ), // VCC Supply Test for FPGA
- .vcaon_supp_i ( 1'b1 ), // AON Supply Test for FPGA
- .vcmain_supp_i ( 1'b1 ), // MAIN Supply Test for FPGA
- .vioa_supp_i ( 1'b1 ), // IO Rails Supply Test for FPGA
- .viob_supp_i ( 1'b1 ), // IO Rails Supply Test for FPGA
+ .vcc_supp_i ( 1'b1 ),
+ .vcaon_supp_i ( 1'b1 ),
+ .vcmain_supp_i ( 1'b1 ),
+ .vioa_supp_i ( 1'b1 ),
+ .viob_supp_i ( 1'b1 ),
// pok
- .vcaon_pok_o ( ast_base_rst.aon_pok ),
- .vcmain_pok_o ( ast_base_pwr.main_pok ),
- .vioa_pok_o ( status_o.io_pok[0] ),
- .viob_pok_o ( status_o.io_pok[1] ),
+ .vcaon_pok_o ( ast_base_rst.aon_pok ),
+ .vcmain_pok_o ( ast_base_pwr.main_pok ),
+ .vioa_pok_o ( ast_status.io_pok[0] ),
+ .viob_pok_o ( ast_status.io_pok[1] ),
// main regulator
- .main_iso_en_i ( base_ast_pwr.pwr_clamp ),
- .main_pd_ni ( base_ast_pwr.main_pd_n ),
+ .main_iso_en_i ( base_ast_pwr.pwr_clamp ),
+ .main_pd_ni ( base_ast_pwr.main_pd_n ),
// pdm control (flash)/otp
- .flash_power_down_h_o ( ast_base_eflash.flash_power_down_h ),
- .flash_power_ready_h_o ( ast_base_eflash.flash_power_ready_h ),
- .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ), //TODO: Connect
- .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ), //TODO: Connect
+ .flash_power_down_h_o ( flash_power_down_h ),
+ .flash_power_ready_h_o ( flash_power_ready_h ),
+ .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ),
+ .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ),
// system source clock
- .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ),
- .clk_src_sys_jen_i ( 1'b0 ), // need to add function in clkmgr
- .clk_src_sys_o ( ast_base_clks.clk_sys ),
- .clk_src_sys_val_o ( core_clk_val ),
+ .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ),
+ // need to add function in clkmgr
+ .clk_src_sys_jen_i ( 1'b0 ),
+ .clk_src_sys_o ( ast_base_clks.clk_sys ),
+ .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ),
// aon source clock
- .clk_src_aon_o ( ast_base_clks.clk_aon ),
- .clk_src_aon_val_o ( slow_clk_val ),
+ .clk_src_aon_o ( ast_base_clks.clk_aon ),
+ .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ),
// io source clock
- .clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
- .clk_src_io_o ( ast_base_clks.clk_io ),
- .clk_src_io_val_o ( io_clk_val ),
+ .clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
+ .clk_src_io_o ( ast_base_clks.clk_io ),
+ .clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
// usb source clock
- .usb_ref_pulse_i ( usb_ref_pulse ),
- .usb_ref_val_i ( usb_ref_val ),
- .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ),
- .clk_src_usb_o ( ast_base_clks.clk_usb ),
- .clk_src_usb_val_o ( usb_clk_val ),
- .usb_io_pu_cal_o ( ), // USB IO Pull-up Calibration Setting
+ .usb_ref_pulse_i ( usb_ref_pulse ),
+ .usb_ref_val_i ( usb_ref_val ),
+ .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ),
+ .clk_src_usb_o ( ast_base_clks.clk_usb ),
+ .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ),
+ // USB IO Pull-up Calibration Setting
+ .usb_io_pu_cal_o ( ),
// adc
- .adc_pd_i ( adc_i.pd ),
- .adc_a0_ai ( adc_a0_a ),
- .adc_a1_ai ( adc_a1_a ),
- .adc_chnsel_i ( adc_i.channel_sel ),
- .adc_d_o ( adc_o.data ),
- .adc_d_val_o ( adc_o.data_valid ),
+ // TODO: Connect to do adc_ctrl when instantiated
+ .adc_pd_i ( '0 ),
+ .adc_a0_ai ( '0 ),
+ .adc_a1_ai ( '0 ),
+ .adc_chnsel_i ( '0 ),
+ .adc_d_o ( ),
+ .adc_d_val_o ( ),
// rng
- .rng_en_i ( es_i.rng_enable ),
- .rng_val_o ( es_o.rng_valid ),
- .rng_b_o ( es_o.rng_b ),
+ .rng_en_i ( es_rng_req.rng_enable ),
+ .rng_val_o ( es_rng_rsp.rng_valid ),
+ .rng_b_o ( es_rng_rsp.rng_b ),
// entropy
- .entropy_rsp_i ( '{edn_ack: 1'b0, edn_fips: 1'b1, edn_bus: '0} ),
- .entropy_req_o ( ), //TODO: Connect
+ .entropy_rsp_i ( ast_edn_edn_rsp ),
+ .entropy_req_o ( ast_edn_edn_req ),
// alerts
- .as_alert_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .as_alert_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .as_alert_o ( as_alert_o ),
- .cg_alert_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .cg_alert_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .cg_alert_o ( cg_alert_o ),
- .gd_alert_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .gd_alert_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .gd_alert_o ( gd_alert_o ),
- .ts_alert_hi_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .ts_alert_hi_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .ts_alert_hi_o ( ts_alert_hi_o ),
- .ts_alert_lo_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .ts_alert_lo_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .ts_alert_lo_o ( ts_alert_lo_o ),
- .ls_alert_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .ls_alert_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .ls_alert_o ( ls_alert_o ),
- .ot_alert_trig_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .ot_alert_ack_i ( '{ p: 1'b0, n: 1'b1 } ), //TODO: Connect
- .ot_alert_o ( ot_alert_o ),
+ .as_alert_trig_i ( ast_alert_rsp.alerts_trig[AsSel] ),
+ .as_alert_ack_i ( ast_alert_rsp.alerts_ack[AsSel] ),
+ .as_alert_o ( ast_alert_req.alerts[AsSel] ),
+ .cg_alert_trig_i ( ast_alert_rsp.alerts_trig[CgSel] ),
+ .cg_alert_ack_i ( ast_alert_rsp.alerts_ack[CgSel] ),
+ .cg_alert_o ( ast_alert_req.alerts[CgSel] ),
+ .gd_alert_trig_i ( ast_alert_rsp.alerts_trig[GdSel] ),
+ .gd_alert_ack_i ( ast_alert_rsp.alerts_ack[GdSel] ),
+ .gd_alert_o ( ast_alert_req.alerts[GdSel] ),
+ .ts_alert_hi_trig_i ( ast_alert_rsp.alerts_trig[TsHiSel] ),
+ .ts_alert_hi_ack_i ( ast_alert_rsp.alerts_ack[TsHiSel] ),
+ .ts_alert_hi_o ( ast_alert_req.alerts[TsHiSel] ),
+ .ts_alert_lo_trig_i ( ast_alert_rsp.alerts_trig[TsLoSel] ),
+ .ts_alert_lo_ack_i ( ast_alert_rsp.alerts_ack[TsLoSel] ),
+ .ts_alert_lo_o ( ast_alert_req.alerts[TsLoSel] ),
+ .ls_alert_trig_i ( ast_alert_rsp.alerts_trig[LsSel] ),
+ .ls_alert_ack_i ( ast_alert_rsp.alerts_ack[LsSel] ),
+ .ls_alert_o ( ast_alert_req.alerts[LsSel] ),
+ .ot_alert_trig_i ( ast_alert_rsp.alerts_trig[OtSel] ),
+ .ot_alert_ack_i ( ast_alert_rsp.alerts_ack[OtSel] ),
+ .ot_alert_o ( ast_alert_req.alerts[OtSel] ),
// dft
- .dft_strap_test_i ( '{valid: 1'b0, straps: 2'b00} ), //TODO: Connect
- .lc_dft_en_i ( lc_ctrl_pkg::On ), //TODO: Connect
+ .dft_strap_test_i ( '{valid: 1'b0, straps: 2'b00} ),
+ .lc_dft_en_i ( lc_ctrl_pkg::Off ),
// pad mux related
- .padmux2ast_i ( '0 ), //TODO: Connect to pinmux
- .ast2padmux_o ( ), //TODO: Connect to pinmux
- .pad2ast_t0_ai ( pad2ast_t0_a ), //TODO: Connect to PAD
- .pad2ast_t1_ai ( pad2ast_t1_a ), //TODO: Connect tp PAD
- .ast2pad_t0_ao ( ), //TODO: Connect to PAD
- .ast2pad_t1_ao ( ), //TODO: Connect tp PAD
- //
- .lc_clk_byp_req_i ( lc_ctrl_pkg::Off ), //TODO: Connect
- .lc_clk_byp_ack_o ( ), //TODO: Connect
- .flash_bist_en_o ( flash_bist_en_o ), //TODO: Connect
- //
- .dpram_rmf_o ( ), //TODO: Connect to memories
- .dpram_rml_o ( ), //TODO: Connect to memories
- .spram_rm_o ( ), //TODO: Connect to memories
- .sprgf_rm_o ( ), //TODO: Connect to memories
- .sprom_rm_o ( ), //TODO: Connect to memories
+ //TODO: Connect to pinmux
+ .padmux2ast_i ( '0 ),
+ .ast2padmux_o ( ),
+ //TODO: Connect to PAD
+ .pad2ast_t0_ai ( '0 ),
+ .pad2ast_t1_ai ( '0 ),
+ .ast2pad_t0_ao ( ),
+ .ast2pad_t1_ao ( ),
+ .lc_clk_byp_req_i ( lc_ast_clk_byp_req ),
+ .lc_clk_byp_ack_o ( lc_ast_clk_byp_ack ),
+ .flash_bist_en_o ( flash_bist_enable ),
+ //TODO: Connect to memories
+ .dpram_rmf_o ( ),
+ .dpram_rml_o ( ),
+ .spram_rm_o ( ),
+ .sprgf_rm_o ( ),
+ .sprom_rm_o ( ),
// scan
- .dft_scan_md_o ( ), //TODO: Connect rstmgr
- .scan_shift_en_o ( ), //TODO: Connect ???
- .scan_reset_no ( ) //TODO: Connect rstmgr
+ .dft_scan_md_o ( scanmode ),
+ .scan_shift_en_o ( scan_en ),
+ .scan_reset_no ( scan_rst_n )
);
@@ -524,24 +421,27 @@
.rsts_ast_o ( rsts_ast ),
.pwrmgr_ast_req_o ( base_ast_pwr ),
.pwrmgr_ast_rsp_i ( ast_base_pwr ),
- .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
- .sensor_ctrl_ast_alert_rsp_o ( base_ast_alerts ),
- .sensor_ctrl_ast_status_i ( ast_base_status ),
+ .sensor_ctrl_ast_alert_req_i ( ast_alert_req ),
+ .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ),
+ .sensor_ctrl_ast_status_i ( ast_status ),
.usbdev_usb_ref_val_o ( usb_ref_pulse ),
.usbdev_usb_ref_pulse_o ( usb_ref_val ),
.ast_tl_req_o ( base_ast_bus ),
.ast_tl_rsp_i ( ast_base_bus ),
+ .ast_edn_edn_req_i ( ast_edn_edn_req ),
+ .ast_edn_edn_rsp_o ( ast_edn_edn_rsp ),
.otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ),
.otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ),
- .flash_bist_enable_i ( ast_base_eflash.flash_bist_enable ),
- .flash_power_down_h_i ( ast_base_eflash.flash_power_down_h ),
- .flash_power_ready_h_i ( ast_base_eflash.flash_power_ready_h ),
- .ast_edn_edn_req_i ( '0 ),
- .ast_edn_edn_rsp_o ( ),
+ .flash_bist_enable_i ( flash_bist_enable ),
+ .flash_power_down_h_i ( flash_power_down_h ),
+ .flash_power_ready_h_i ( flash_power_ready_h ),
+ .es_rng_req_o ( es_rng_req ),
+ .es_rng_rsp_i ( es_rng_rsp ),
+ .lc_clk_byp_req_o ( lc_ast_clk_byp_req ),
+ .lc_clk_byp_ack_i ( lc_ast_clk_byp_ack ),
// TODO: connect these
- .flash_test_mode_a_i ('0),
- .flash_test_voltage_h_i ('0),
-
+ .flash_test_mode_a_i ('0 ),
+ .flash_test_voltage_h_i ('0 ),
// JTAG
.jtag_tck_i ( jtag_tck ),
.jtag_tms_i ( jtag_tms ),
@@ -564,9 +464,10 @@
.dio_attr_o ( dio_attr ),
// DFT signals
- .scan_rst_ni ( 1'b1 ),
- .scan_en_i ( 1'b0 ),
- .scanmode_i ( 1'b0 )
+ .scan_rst_ni ( scan_rst_n ),
+ .scan_en_i ( scan_en ),
+ // TODO: Update scanmode to be a multi-bit connection inside the design
+ .scanmode_i ( scanmode == lc_ctrl_pkg::On )
);
endmodule : top_earlgrey_asic
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
index 37e90c7..a7809bc 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
@@ -360,24 +360,30 @@
// Top-level design //
//////////////////////
pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
- ast_wrapper_pkg::ast_rst_t ast_base_rst;
- ast_wrapper_pkg::ast_alert_req_t ast_base_alerts;
- ast_wrapper_pkg::ast_status_t ast_base_status;
+ ast_pkg::ast_rst_t ast_base_rst;
+ ast_pkg::ast_alert_req_t ast_base_alerts;
+ ast_pkg::ast_status_t ast_base_status;
- assign ast_base_pwr.slow_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.core_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.io_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.usb_clk_val = pwrmgr_pkg::DiffValid;
+ assign ast_base_pwr.slow_clk_val = 1'b1;
+ assign ast_base_pwr.core_clk_val = 1'b1;
+ assign ast_base_pwr.io_clk_val = 1'b1;
+ assign ast_base_pwr.usb_clk_val = 1'b1;
assign ast_base_pwr.main_pok = 1'b1;
- assign ast_base_alerts.alerts_p = '0;
- assign ast_base_alerts.alerts_n = {ast_wrapper_pkg::NumAlerts{1'b1}};
- assign ast_base_status.io_pok = {ast_wrapper_pkg::NumIoRails{1'b1}};
+ ast_pkg::ast_dif_t silent_alert = '{
+ p: 1'b0,
+ n: 1'b1
+ };
+
+ assign ast_base_alerts.alerts = {ast_pkg::NumAlerts{silent_alert}};
+ assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}};
// the rst_ni pin only goes to AST
// the rest of the logic generates reset based on the 'pok' signal.
// for verilator purposes, make these two the same.
assign ast_base_rst.aon_pok = rst_n;
+ lc_ctrl_pkg::lc_tx_t lc_clk_bypass;
+
top_earlgrey #(
.AesMasking(1'b0),
.AesSBoxImpl(aes_pkg::SBoxImplLut),
@@ -389,14 +395,16 @@
.BootRomInitFile(BootRomInitFile)
) top_earlgrey (
// Clocks, resets
- .rst_ni ( rst_n ),
- .clk_main_i ( clk_main ),
- .clk_io_i ( clk_main ),
- .clk_usb_i ( clk_usb_48mhz ),
- .clk_aon_i ( clk_main ),
- .rstmgr_ast_i ( ast_base_rst ),
- .pwrmgr_ast_req_o ( ),
- .pwrmgr_ast_rsp_i ( ast_base_pwr ),
+ .rst_ni ( rst_n ),
+ .clk_main_i ( clk_main ),
+ .clk_io_i ( clk_main ),
+ .clk_usb_i ( clk_usb_48mhz ),
+ .clk_aon_i ( clk_main ),
+ .clks_ast_o ( ),
+ .rstmgr_ast_i ( ast_base_rst ),
+ .rsts_ast_o ( ),
+ .pwrmgr_ast_req_o ( ),
+ .pwrmgr_ast_rsp_i ( ast_base_pwr ),
.sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
.sensor_ctrl_ast_alert_rsp_o ( ),
.sensor_ctrl_ast_status_i ( ast_base_status ),
@@ -404,15 +412,21 @@
.usbdev_usb_ref_pulse_o ( ),
.ast_tl_req_o ( ),
.ast_tl_rsp_i ( '0 ),
+ .ast_edn_edn_req_i ( '0 ),
+ .ast_edn_edn_rsp_o ( ),
.otp_ctrl_otp_ast_pwr_seq_o ( ),
.otp_ctrl_otp_ast_pwr_seq_h_i ( '0 ),
.flash_bist_enable_i ( 1'b0 ),
.flash_power_down_h_i ( 1'b0 ),
.flash_power_ready_h_i ( 1'b1 ),
- .flash_test_mode_a_i ('0),
- .flash_test_voltage_h_i ('0),
- .clks_ast_o ( ),
- .rsts_ast_o ( ),
+ // Need to modle this logic at some point, otherwise entropy
+ // on verilator will hang
+ .es_rng_req_o ( ),
+ .es_rng_rsp_i ( '0 ),
+ .lc_clk_byp_req_o ( lc_clk_bypass ),
+ .lc_clk_byp_ack_i ( lc_clk_bypass ),
+ .flash_test_mode_a_i ('0 ),
+ .flash_test_voltage_h_i ('0 ),
// JTAG
.jtag_tck_i ( jtag_tck_buf ),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
index f5754df..6035eb4 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
@@ -75,75 +75,88 @@
// dummy ast connections
pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
- ast_wrapper_pkg::ast_rst_t ast_base_rst;
- ast_wrapper_pkg::ast_alert_req_t ast_base_alerts;
- ast_wrapper_pkg::ast_status_t ast_base_status;
+ ast_pkg::ast_rst_t ast_base_rst;
+ ast_pkg::ast_alert_req_t ast_base_alerts;
+ ast_pkg::ast_status_t ast_base_status;
- assign ast_base_pwr.slow_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.core_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.io_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.usb_clk_val = pwrmgr_pkg::DiffValid;
+ assign ast_base_pwr.slow_clk_val = 1'b1;
+ assign ast_base_pwr.core_clk_val = 1'b1;
+ assign ast_base_pwr.io_clk_val = 1'b1;
+ assign ast_base_pwr.usb_clk_val = 1'b1;
assign ast_base_pwr.main_pok = 1'b1;
- assign ast_base_alerts.alerts_p = '0;
- assign ast_base_alerts.alerts_n = {ast_wrapper_pkg::NumAlerts{1'b1}};
- assign ast_base_status.io_pok = {ast_wrapper_pkg::NumIoRails{1'b1}};
+ ast_pkg::ast_dif_t silent_alert = '{
+ p: 1'b0,
+ n: 1'b1
+ };
+
+ assign ast_base_alerts.alerts = {ast_pkg::NumAlerts{silent_alert}};
+ assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}};
// the rst_ni pin only goes to AST
// the rest of the logic generates reset based on the 'pok' signal.
// for verilator purposes, make these two the same.
assign ast_base_rst.aon_pok = rst_ni;
+
+ lc_ctrl_pkg::lc_tx_t lc_clk_bypass;
// Top-level design
top_earlgrey top_earlgrey (
- .rst_ni (rst_ni),
- .clk_main_i (clk_i),
- .clk_io_i (clk_i),
- .clk_usb_i (clk_i),
- .clk_aon_i (clk_i),
- .rstmgr_ast_i ( ast_base_rst ),
- .pwrmgr_ast_req_o ( ),
- .pwrmgr_ast_rsp_i ( ast_base_pwr ),
- .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
- .sensor_ctrl_ast_alert_rsp_o ( ),
- .sensor_ctrl_ast_status_i ( ast_base_status ),
- .usbdev_usb_ref_val_o ( ),
- .usbdev_usb_ref_pulse_o ( ),
- .ast_tl_req_o ( ),
- .ast_tl_rsp_i ( '0 ),
- .otp_ctrl_otp_ast_pwr_seq_o ( ),
- .otp_ctrl_otp_ast_pwr_seq_h_i ( '0 ),
- .flash_bist_enable_i ( 1'b0 ),
- .flash_power_down_h_i ( 1'b0 ),
- .flash_power_ready_h_i ( 1'b1 ),
+ .rst_ni (rst_ni ),
+ .clk_main_i (clk_i ),
+ .clk_io_i (clk_i ),
+ .clk_usb_i (clk_i ),
+ .clk_aon_i (clk_i ),
+ .clks_ast_o ( ),
+ .rstmgr_ast_i ( ast_base_rst ),
+ .rsts_ast_o ( ),
+ .pwrmgr_ast_req_o ( ),
+ .pwrmgr_ast_rsp_i ( ast_base_pwr ),
+ .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
+ .sensor_ctrl_ast_alert_rsp_o ( ),
+ .sensor_ctrl_ast_status_i ( ast_base_status ),
+ .usbdev_usb_ref_val_o ( ),
+ .usbdev_usb_ref_pulse_o ( ),
+ .ast_tl_req_o ( ),
+ .ast_tl_rsp_i ( '0 ),
+ .ast_edn_edn_req_i ( '0 ),
+ .ast_edn_edn_rsp_o ( ),
+ .otp_ctrl_otp_ast_pwr_seq_o ( ),
+ .otp_ctrl_otp_ast_pwr_seq_h_i ( '0 ),
+ .flash_bist_enable_i ( lc_ctrl_pkg::Off ),
+ .flash_power_down_h_i ( 1'b0 ),
+ .flash_power_ready_h_i ( 1'b1 ),
+ // Need to model this logic at some point, otherwise entropy
+ // on verilator will hang
+ .es_rng_req_o ( ),
+ .es_rng_rsp_i ( '0 ),
+ .lc_clk_byp_req_o ( lc_clk_bypass ),
+ .lc_clk_byp_ack_i ( lc_clk_bypass ),
.flash_test_mode_a_i ('0),
.flash_test_voltage_h_i ('0),
- .clks_ast_o ( ),
- .rsts_ast_o ( ),
-
- .jtag_tck_i (cio_jtag_tck),
- .jtag_tms_i (cio_jtag_tms),
- .jtag_trst_ni (cio_jtag_trst_n),
- .jtag_tdi_i (cio_jtag_tdi),
- .jtag_tdo_o (cio_jtag_tdo),
+ .jtag_tck_i (cio_jtag_tck),
+ .jtag_tms_i (cio_jtag_tms),
+ .jtag_trst_ni (cio_jtag_trst_n),
+ .jtag_tdi_i (cio_jtag_tdi),
+ .jtag_tdo_o (cio_jtag_tdo),
// Multiplexed I/O
- .mio_in_i (cio_gpio_p2d),
- .mio_out_o (cio_gpio_d2p),
- .mio_oe_o (cio_gpio_en_d2p),
+ .mio_in_i (cio_gpio_p2d),
+ .mio_out_o (cio_gpio_d2p),
+ .mio_oe_o (cio_gpio_en_d2p),
// Dedicated I/O
- .dio_in_i (dio_in),
- .dio_out_o (dio_out),
- .dio_oe_o (dio_oe),
+ .dio_in_i (dio_in),
+ .dio_out_o (dio_out),
+ .dio_oe_o (dio_oe),
// Pad attributes
- .mio_attr_o ( ),
- .dio_attr_o ( ),
+ .mio_attr_o ( ),
+ .dio_attr_o ( ),
// DFT signals
- .scan_rst_ni (1'b1),
- .scan_en_i (1'b0),
- .scanmode_i (1'b0)
+ .scan_rst_ni (1'b1),
+ .scan_en_i (1'b0),
+ .scanmode_i (1'b0)
);
// GPIO DPI
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core
index 9f00dff..1a43534 100644
--- a/hw/top_earlgrey/top_earlgrey.core
+++ b/hw/top_earlgrey/top_earlgrey.core
@@ -46,7 +46,7 @@
- lowrisc:ip:pwrmgr
- lowrisc:systems:clkmgr
- lowrisc:systems:sensor_ctrl
- - lowrisc:systems:ast_wrapper_pkg
+ - lowrisc:systems:ast_pkg
- lowrisc:tlul:headers
- lowrisc:prim:all
files:
diff --git a/hw/top_englishbreakfast/rtl/top_englishbreakfast_cw305.sv b/hw/top_englishbreakfast/rtl/top_englishbreakfast_cw305.sv
index eeb2011..c336081 100644
--- a/hw/top_englishbreakfast/rtl/top_englishbreakfast_cw305.sv
+++ b/hw/top_englishbreakfast/rtl/top_englishbreakfast_cw305.sv
@@ -218,19 +218,22 @@
// Top-level design //
//////////////////////
pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
- ast_wrapper_pkg::ast_rst_t ast_base_rst;
- ast_wrapper_pkg::ast_alert_req_t ast_base_alerts;
- ast_wrapper_pkg::ast_status_t ast_base_status;
+ ast_pkg::ast_rst_t ast_base_rst;
+ ast_pkg::ast_alert_req_t ast_base_alerts;
+ ast_pkg::ast_status_t ast_base_status;
- assign ast_base_pwr.slow_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.core_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.io_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.usb_clk_val = pwrmgr_pkg::DiffValid;
+ assign ast_base_pwr.slow_clk_val = 1'b1;
+ assign ast_base_pwr.core_clk_val = 1'b1;
+ assign ast_base_pwr.io_clk_val = 1'b1;
+ assign ast_base_pwr.usb_clk_val = 1'b1;
assign ast_base_pwr.main_pok = 1'b1;
- assign ast_base_alerts.alerts_p = '0;
- assign ast_base_alerts.alerts_n = {ast_wrapper_pkg::NumAlerts{1'b1}};
- assign ast_base_status.io_pok = {ast_wrapper_pkg::NumIoRails{1'b1}};
+ ast_pkg::ast_dif_t silent_alert = '{
+ p: 1'b0,
+ n: 1'b1
+ };
+ assign ast_base_alerts.alerts = {ast_pkg::NumAlerts{silent_alert}};
+ assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}};
// the rst_ni pin only goes to AST
// the rest of the logic generates reset based on the 'pok' signal.
diff --git a/hw/top_englishbreakfast/rtl/top_englishbreakfast_verilator.sv b/hw/top_englishbreakfast/rtl/top_englishbreakfast_verilator.sv
index 2137a2e..7449de2 100644
--- a/hw/top_englishbreakfast/rtl/top_englishbreakfast_verilator.sv
+++ b/hw/top_englishbreakfast/rtl/top_englishbreakfast_verilator.sv
@@ -75,19 +75,22 @@
// dummy ast connections
pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
- ast_wrapper_pkg::ast_rst_t ast_base_rst;
- ast_wrapper_pkg::ast_alert_req_t ast_base_alerts;
- ast_wrapper_pkg::ast_status_t ast_base_status;
+ ast_pkg::ast_rst_t ast_base_rst;
+ ast_pkg::ast_alert_req_t ast_base_alerts;
+ ast_pkg::ast_status_t ast_base_status;
- assign ast_base_pwr.slow_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.core_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.io_clk_val = pwrmgr_pkg::DiffValid;
- assign ast_base_pwr.usb_clk_val = pwrmgr_pkg::DiffValid;
+ assign ast_base_pwr.slow_clk_val = 1'b1;
+ assign ast_base_pwr.core_clk_val = 1'b1;
+ assign ast_base_pwr.io_clk_val = 1'b1;
+ assign ast_base_pwr.usb_clk_val = 1'b1;
assign ast_base_pwr.main_pok = 1'b1;
- assign ast_base_alerts.alerts_p = '0;
- assign ast_base_alerts.alerts_n = {ast_wrapper_pkg::NumAlerts{1'b1}};
- assign ast_base_status.io_pok = {ast_wrapper_pkg::NumIoRails{1'b1}};
+ ast_pkg::ast_dif_t silent_alert = '{
+ p: 1'b0,
+ n: 1'b1
+ };
+ assign ast_base_alerts.alerts = {ast_pkg::NumAlerts{silent_alert}};
+ assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}};
// the rst_ni pin only goes to AST
// the rest of the logic generates reset based on the 'pok' signal.
diff --git a/util/topgen-fusesoc.py b/util/topgen-fusesoc.py
index 607cecf..c864032 100644
--- a/util/topgen-fusesoc.py
+++ b/util/topgen-fusesoc.py
@@ -139,7 +139,7 @@
# Top
# ast and sensor_ctrl not auto-generated, re-used from top_earlgrey
'lowrisc:systems:sensor_ctrl',
- 'lowrisc:systems:ast_wrapper_pkg',
+ 'lowrisc:systems:ast_pkg',
],
'files': [
# IPs
