commit e9e06bcb91e7e24de29833e4f65e9154e76bd22b
author Weicai Yang <weicai@google.com> Mon Aug 17 17:37:03 2020 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Tue Aug 18 17:45:31 2020 -0700
tree a197bae6b3e023fd576f71310b89c917c3f3334a
parent 2f8a2bef3e96d8e51304582e98950a97b8223be5

[tlul/dv] Update test plan for tl errors

List all the error cases in testplan

Signed-off-by: Weicai Yang <weicai@google.com>

hw/dv/tools/testplans/tl_device_access_types_testplan.hjson

diff --git a/hw/dv/tools/testplans/tl_device_access_types_testplan.hjson b/hw/dv/tools/testplans/tl_device_access_types_testplan.hjson
index 97c5267..4e78eda 100644
--- a/hw/dv/tools/testplans/tl_device_access_types_testplan.hjson
+++ b/hw/dv/tools/testplans/tl_device_access_types_testplan.hjson
@@ -4,36 +4,53 @@
 {
   entries: [
     {
-      name: oob_addr_access
+      name: tl_d_oob_addr_access
       desc: "Access out of bounds address and verify correctness of response / behavior"
       milestone: V2
       tests: ["{name}_tl_errors"]
     }
     {
-      name: illegal_access
+      name: tl_d_illegal_access
       desc: '''Drive unsupported requests via TL interface and verify correctness of response
-            / behavior '''
+            / behavior. Below error cases are tested
+            - TL-UL protocol error cases
+              - Unsupported opcode. e.g a_opcode isn't Get, PutPartialData or PutFullData
+              - Mask isn't all active if opcode = PutFullData
+              - Mask isn't in enabled lanes, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
+              - Mask doesn't align with address, e.g. a_address = 0x01, a_mask = 'b0001
+              - Address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
+              - Size is over 2.
+            - OpenTitan defined error cases
+              - Access unmapped address, return d_error = 1 when devmode_i == 1
+              - Write CSR with unaligned address, e.g. a_address[1:0] != 0
+              - Write CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
+              - Write a memory without enabling all lanes (a_mask = '1) if memory doesn't support
+                byte enabled write
+              - Read a WO (write-only) memory'''
       milestone: V2
       tests: ["{name}_tl_errors"]
     }
     {
-      name: outstanding_access
+      name: tl_d_outstanding_access
       desc: '''Drive back-to-back requests without waiting for response to ensure there is one
             transaction outstanding within the TL device. Also, verify one outstanding when back-
             to-back accesses are made to the same address.'''
       milestone: V2
-      tests: ["{name}{intf}_csr_hw_reset",
-              "{name}{intf}_csr_rw",
-              "{name}{intf}_csr_aliasing",
-              "{name}{intf}_same_csr_outstanding"]
+      tests: ["{name}_csr_hw_reset",
+              "{name}_csr_rw",
+              "{name}_csr_aliasing",
+              "{name}_same_csr_outstanding"]
     }
     {
-      name: partial_access
-      desc: '''Do partial accesses.'''
+      name: tl_d_partial_access
+      desc: '''Access CSR with one or more bytes of data
+            For read, expect to return all word value of the CSR
+            For write, enabling bytes should cover all CSR valid fields'''
       milestone: V2
-      tests: ["{name}{intf}_csr_hw_reset",
-              "{name}{intf}_csr_rw",
-              "{name}{intf}_csr_aliasing"]
+      tests: ["{name}_csr_hw_reset",
+              "{name}_csr_rw",
+              "{name}_csr_aliasing",
+              "{name}_same_csr_outstanding"]
     }
   ]
 }