[syn] Revise constraints
Move mio_* to IO clock domain give 50% in/out delay.
Add IO, AON clocks into the constraint. Aiming 24MHz and 300kHz
Revised clock definition to find correct clock port for SPI Device clk.
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/hw/syn/data/dc.hjson b/hw/syn/data/dc.hjson
index 35c65ce..c9bcf40 100644
--- a/hw/syn/data/dc.hjson
+++ b/hw/syn/data/dc.hjson
@@ -14,7 +14,7 @@
{"SV_FLIST" : "{sv_flist}"}]
// Tool invocation
- build_cmd: "dc_shell-xg-t "
+ build_cmd: "{job_prefix} dc_shell-xg-t "
build_opts: ["-f run-syn.tcl"]
// DC-specific results parsing script that is called after running synthesis
diff --git a/hw/syn/tools/dc/run-syn.tcl b/hw/syn/tools/dc/run-syn.tcl
index ff75db8..53201e3 100644
--- a/hw/syn/tools/dc/run-syn.tcl
+++ b/hw/syn/tools/dc/run-syn.tcl
@@ -11,28 +11,48 @@
# tool setup
source setup.tcl
+# not exit remained in command line
+set RUN_INTERACTIVE $::env(INTERACTIVE)
+
# path to directory containing the source list file
set SV_FLIST $::env(SV_FLIST)
set BUILD_DIR $::env(BUILD_DIR)
+# just compile the "core" toplevel at the moment
+# might want to switch to top_earlgrey_asic later on (with pads)
+set DUT $::env(DUT)
+
# paths
set WORKLIB "${BUILD_DIR}/WORK"
set REPDIR "${BUILD_DIR}/REPORTS"
set DDCDIR "${BUILD_DIR}/DDC"
+set RESULTDIR "${BUILD_DIR}/results"
set VLOGDIR "${BUILD_DIR}/NETLISTS"
-exec mkdir -p ${REPDIR} ${DDCDIR} ${VLOGDIR} ${WORKLIB}
+exec mkdir -p ${REPDIR} ${DDCDIR} ${VLOGDIR} ${WORKLIB} ${RESULTDIR}
# define work lib path
define_design_lib WORK -path $WORKLIB
#######################
+## CONFIGURATIONS ###
+#######################
+
+# Define the verification setup file for Formality
+set_svf ${RESULTDIR}/${DUT}.svf
+
+# Setup SAIF Name Mapping Database
+saif_map -start
+
+###The following variable helps verification when there are differences between DC and FM while inferring logical hierarchies
+set_app_var hdlin_enable_hier_map true
+
+
+
+#######################
## DESIGN SOURCES ###
#######################
-# just compile the "core" toplevel at the moment
-# might want to switch to top_earlgrey_asic later on (with pads)
-set DUT $::env(DUT)
# this PRIM_DEFAULT_IMPL selects the appropriate technology by defining
# PRIM_DEFAULT_IMPL=prim_pkg::Impl<tech identifier>
@@ -55,6 +75,8 @@
link > "${REPDIR}/link.rpt"
check_design > "${REPDIR}/check.rpt"
+set_verification_top
+
write_file -format ddc -hierarchy -output "${DDCDIR}/elab.ddc"
write_file -format verilog -hierarchy -output "${DDCDIR}/elab.v"
@@ -96,6 +118,9 @@
sh echo ${NAND2_GATE_EQUIVALENT} > "${REPDIR}/gate_equiv.rpt"
report_clocks > "${REPDIR}/clocks.rpt"
+report_clock -groups > "${REPDIR}/clock.groups.rpt"
+report_path_group > "${REPDIR}/path_group.rpt"
+report_clock_gating -multi_stage -nosplit > "${REPDIR}/clock_gating.rpt"
report_timing -nosplit -slack_lesser_than 0.0 > "${REPDIR}/timing.rpt"
report_area -hier -nosplit > "${REPDIR}/area.rpt"
report_power -hier -nosplit > "${REPDIR}/power.rpt"
@@ -113,6 +138,10 @@
write_file -format ddc -hierarchy -output "${DDCDIR}/mapped.ddc"
write_file -format verilog -hierarchy -output "${VLOGDIR}/mapped.v"
+# Write final SDC
+write_sdc -nosplit ${RESULTDIR}/${DUT}.final.sdc
+# If SAIF is used, write out SAIF name mapping file for PrimeTime-PX
+saif_map -type ptpx -write_map ${RESULTDIR}/${DUT}.mapped.SAIF.namemap
# ##############################
# ## INCREMENTAL FLATTENING ##
# ##############################
@@ -136,4 +165,7 @@
# write_file -format ddc -hierarchy -output "${DDCDIR}/flat.ddc"
# write_file -format verilog -hierarchy -output "${VLOGDIR}/flat.v"
-exit
+if { ![info exists RUN_INTERACTIVE] } {
+ exit
+}
+
diff --git a/hw/top_earlgrey/syn/constraints.sdc b/hw/top_earlgrey/syn/constraints.sdc
index 4d6bdea..8a682c0 100644
--- a/hw/top_earlgrey/syn/constraints.sdc
+++ b/hw/top_earlgrey/syn/constraints.sdc
@@ -13,6 +13,27 @@
# there are no pads instantiated in the netlist (yet)
#####################
+# DIO pin mapping #
+#####################
+set PORT_SPI_DEVICE_SCK 14
+set PORT_SPI_DEVICE_CSB 13
+set PORT_SPI_DEVICE_MOSI 12
+set PORT_SPI_DEVICE_MISO 11
+
+set PORT_UART_RX 10
+set PORT_UART_TX 9
+
+set PORT_USBDEV_SENSE 8
+set PORT_USBDEV_SE0 7
+set PORT_USBDEV_DP_PULLUP 6
+set PORT_USBDEV_DN_PULLUP 5
+set PORT_USBDEV_TX_MODE_SE 4
+set PORT_USBDEV_SUSPEND 3
+set PORT_USBDEV_D 2
+set PORT_USBDEV_DP 1
+set PORT_USBDEV_DN 0
+
+#####################
# main clock #
#####################
set MAIN_CLK_PIN clk_i
@@ -22,47 +43,85 @@
set_ideal_network ${MAIN_CLK_PIN}
set_ideal_network ${MAIN_RST_PIN}
-create_clock ${MAIN_CLK_PIN} -period ${MAIN_TCK}
-set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} ${MAIN_CLK_PIN}
+create_clock -name MAIN_CLK -period ${MAIN_TCK} [get_ports ${MAIN_CLK_PIN}]
+set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} [get_clocks MAIN_CLK]
+
+# TODO: generated clock
+# TODO: clock gating setup/hold
+
set IN_DEL 5.5
set OUT_DEL 5.5
-set_input_delay ${IN_DEL} [get_ports mio_in_i*] -clock ${MAIN_CLK_PIN}
-set_input_delay ${IN_DEL} [get_ports scanmode_i] -clock ${MAIN_CLK_PIN}
-set_input_delay ${IN_DEL} [get_ports dio_uart_rx_i] -clock ${MAIN_CLK_PIN}
-
-set_output_delay ${OUT_DEL} [get_ports mio_out_o*] -clock ${MAIN_CLK_PIN}
-set_output_delay ${OUT_DEL} [get_ports mio_oe_o*] -clock ${MAIN_CLK_PIN}
-set_output_delay ${OUT_DEL} [get_ports dio_uart_tx_o] -clock ${MAIN_CLK_PIN}
-set_output_delay ${OUT_DEL} [get_ports dio_uart_tx_en_o] -clock ${MAIN_CLK_PIN}
+# Doesn't need
+#set_input_delay ${IN_DEL} [get_ports scanmode_i] -clock MAIN_CLK
#####################
# USB clock #
#####################
-set USB_CLK_PIN clk_usb_48mhz_i
+set USB_CLK_PIN clk_usb_i
# 50MHz
set USB_TCK 20.0
set_ideal_network ${USB_CLK_PIN}
-create_clock ${USB_CLK_PIN} -period ${USB_TCK}
-set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} ${USB_CLK_PIN}
+create_clock -name USB_CLK -period ${USB_TCK} [get_ports ${USB_CLK_PIN}]
+set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} [get_clocks USB_CLK]
set IN_DEL 17.0
set OUT_DEL 17.0
-set_input_delay ${IN_DEL} [get_ports dio_usbdev_sense_i] -clock ${USB_CLK_PIN}
-set_input_delay ${IN_DEL} [get_ports dio_usbdev_dp_i] -clock ${USB_CLK_PIN}
-set_input_delay ${IN_DEL} [get_ports dio_usbdev_dn_i] -clock ${USB_CLK_PIN}
+set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_USBDEV_SENSE]] -clock USB_CLK
+set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_USBDEV_DP]] -clock USB_CLK
+set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_USBDEV_DN]] -clock USB_CLK
-set_output_delay ${OUT_DEL} [get_ports dio_usbdev_dp_pullup_o] -clock ${USB_CLK_PIN}
-set_output_delay ${OUT_DEL} [get_ports dio_usbdev_dp_pullup_en_o] -clock ${USB_CLK_PIN}
-set_output_delay ${OUT_DEL} [get_ports dio_usbdev_dn_pullup_o] -clock ${USB_CLK_PIN}
-set_output_delay ${OUT_DEL} [get_ports dio_usbdev_dn_pullup_en_o] -clock ${USB_CLK_PIN}
-set_output_delay ${OUT_DEL} [get_ports dio_usbdev_dp_o] -clock ${USB_CLK_PIN}
-set_output_delay ${OUT_DEL} [get_ports dio_usbdev_dp_en_o] -clock ${USB_CLK_PIN}
-set_output_delay ${OUT_DEL} [get_ports dio_usbdev_dn_o] -clock ${USB_CLK_PIN}
-set_output_delay ${OUT_DEL} [get_ports dio_usbdev_dn_en_o] -clock ${USB_CLK_PIN}
+set_output_delay ${OUT_DEL} [get_ports dio_out_o[$PORT_USBDEV_DP_PULLUP]] -clock USB_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_oe_o[$PORT_USBDEV_DP_PULLUP]] -clock USB_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_out_o[$PORT_USBDEV_DN_PULLUP]] -clock USB_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_oe_o[$PORT_USBDEV_DN_PULLUP]] -clock USB_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_out_o[$PORT_USBDEV_DP]] -clock USB_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_oe_o[$PORT_USBDEV_DP]] -clock USB_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_out_o[$PORT_USBDEV_DN]] -clock USB_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_oe_o[$PORT_USBDEV_DN]] -clock USB_CLK
+
+#####################
+# IO clk (24MHz) #
+#####################
+set IO_CLK_PIN clk_io_i
+set IO_TCK 40.0
+set_ideal_network ${IO_CLK_PIN}
+
+create_clock -name IO_CLK -period ${IO_TCK} [get_ports ${IO_CLK_PIN}]
+set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} [get_clocks IO_CLK]
+
+# TODO: generated clock
+# TODO: clock gating setup/hold
+
+set IN_DEL 20.0
+set OUT_DEL 20.0
+
+set_input_delay ${IN_DEL} [get_ports mio_in_i*] -clock IO_CLK
+
+set_output_delay ${OUT_DEL} [get_ports mio_out_o*] -clock IO_CLK
+set_output_delay ${OUT_DEL} [get_ports mio_oe_o*] -clock IO_CLK
+
+# UART RX
+set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_UART_RX]] -clock IO_CLK
+
+# UART TX
+set_output_delay ${OUT_DEL} [get_ports dio_out_o[$PORT_UART_TX]] -clock IO_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_oe_o[$PORT_UART_TX]] -clock IO_CLK
+
+#####################
+# AON clk (300kHz) #
+#####################
+set AON_CLK_PIN clk_aon_i
+set AON_TCK 3333.0
+set_ideal_network ${AON_CLK_PIN}
+
+create_clock -name AON_CLK -perio ${AON_TCK} [get_ports ${AON_CLK_PIN}]
+set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} [get_clocks AON_CLK]
+
+# use same IO IN/OUT delay
#####################
# JTAG clock #
@@ -74,49 +133,53 @@
set_ideal_network ${JTAG_CLK_PIN}
set_ideal_network ${JTAG_RST_PIN}
-create_clock ${JTAG_CLK_PIN} -period ${JTAG_TCK}
-set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} ${JTAG_CLK_PIN}
+create_clock -name JTAG_CLK -period ${JTAG_TCK} [get_ports ${JTAG_CLK_PIN}]
+set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} [get_clocks JTAG_CLK]
set IN_DEL 10.0
set OUT_DEL 10.0
-set_input_delay ${IN_DEL} [get_ports jtag_tms_i] -clock ${JTAG_CLK_PIN}
-set_input_delay ${IN_DEL} [get_ports jtag_td_i] -clock ${JTAG_CLK_PIN}
+set_input_delay ${IN_DEL} [get_ports jtag_tms_i] -clock JTAG_CLK
+set_input_delay ${IN_DEL} [get_ports jtag_tdi_i] -clock JTAG_CLK
-set_output_delay ${OUT_DEL} [get_ports jtag_td_o] -clock ${JTAG_CLK_PIN}
+set_output_delay ${OUT_DEL} [get_ports jtag_tdo_o] -clock JTAG_CLK
#####################
# SPI clock #
#####################
-set SPI_CLK_PIN dio_spi_device_sck_i
+set SPI_CLK_PIN dio_in_i[$PORT_SPI_DEVICE_SCK]
# 62.5MHz
set SPI_TCK 16.0
set_ideal_network ${SPI_CLK_PIN}
-create_clock ${SPI_CLK_PIN} -period ${SPI_TCK}
-set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} ${SPI_CLK_PIN}
+create_clock -name SPID_CLK -period ${SPI_TCK} [get_ports ${SPI_CLK_PIN}]
+set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} [get_clocks SPID_CLK]
+
+## TODO: Create generated clock for negedge SPID_CLK. Then make them clock group
set IN_DEL 6.0
set OUT_DEL 6.0
-set_input_delay ${IN_DEL} [get_ports dio_spi_device_csb_i] -clock ${SPI_CLK_PIN}
-set_input_delay ${IN_DEL} [get_ports dio_spi_device_mosi_i] -clock ${SPI_CLK_PIN}
+set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_SPI_DEVICE_CSB]] -clock SPID_CLK
+set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_SPI_DEVICE_MOSI]] -clock SPID_CLK
-set_output_delay ${OUT_DEL} [get_ports dio_spi_device_miso_o] -clock ${SPI_CLK_PIN}
-set_output_delay ${OUT_DEL} [get_ports dio_spi_device_miso_en_o] -clock ${SPI_CLK_PIN}
+set_output_delay ${OUT_DEL} [get_ports dio_out_o[$PORT_SPI_DEVICE_MISO]] -clock SPID_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_oe_o[$PORT_SPI_DEVICE_MISO]] -clock SPID_CLK
#####################
# CDC #
#####################
# this may need some refinement (and max delay / skew needs to be constrained)
-set_clock_groups -name group1 -async -group ${MAIN_CLK_PIN} \
- -group ${JTAG_CLK_PIN} \
- -group ${USB_CLK_PIN} \
- -group ${SPI_CLK_PIN}
+set_clock_groups -name group1 -async -group [get_clocks MAIN_CLK] \
+ -group [get_clocks JTAG_CLK] \
+ -group [get_clocks USB_CLK ] \
+ -group [get_clocks SPID_CLK] \
+ -group [get_clocks IO_CLK ] \
+ -group [get_clocks AON_CLK ]
# loopback path can be considered to be a false path
-set_false_path -from dio_uart_rx_i -to dio_uart_tx_o
+set_false_path -from dio_in_i[$PORT_UART_RX] -to dio_out_o[$PORT_UART_TX]
#####################
# I/O drive/load #
