[flash_ctrl] update parameters
- update parameters to production values and fix related lint warnings
- only remaining parameter not to be updated is number of pages due to
fpga constraints
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
index 2a52979..e72ac97 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
@@ -1,6 +1,14 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
+
+<%
+ page_width = (cfg['pages_per_bank']-1).bit_length()
+ bank_width = (cfg['banks']-1).bit_length()
+ all_data_width = (cfg['banks']*cfg['pages_per_bank']-1).bit_length()
+ info_type_width = (cfg['info_types']-1).bit_length()
+%>
+
{ name: "FLASH_CTRL",
clock_primary: "clk_i",
other_clock_list: [ "clk_otp_i" ],
@@ -148,6 +156,20 @@
local: "true"
},
+ { name: "RegPageWidth",
+ desc: "Number of bits needed to represent the pages within a bank",
+ type: "int",
+ default: "${page_width}",
+ local: "true"
+ },
+
+ { name: "RegBankWidth",
+ desc: "Number of bits needed to represent the number of banks",
+ type: "int",
+ default: "${bank_width}",
+ local: "true"
+ },
+
{ name: "NumRegions",
desc: "Number of configurable flash regions",
type: "int",
@@ -337,7 +359,7 @@
'''
resval: "0"
},
- { bits: "9",
+ { bits: "${9 + info_type_width -1}:9",
name: "INFO_SEL",
desc: '''
Informational partions can have multiple types.
@@ -514,14 +536,14 @@
''',
resval: "0"
}
- { bits: "16:8",
+ { bits: "${8 + bank_width + page_width - 1}:8",
name: "BASE",
desc: '''
Region base page. Note the granularity is page, not byte or word
''',
resval: "0"
},
- { bits: "29:20", // need to template this term long term for flash size
+ { bits: "${8 + 2*bank_width + 2*page_width}:${8 + bank_width + page_width}",
name: "SIZE",
desc: '''
Region size in number of pages
@@ -755,7 +777,7 @@
{ bits: "2", name: "prog_full", desc: "Flash program FIFO full"},
{ bits: "3", name: "prog_empty", desc: "Flash program FIFO empty, software must provide data", resval: "1"},
{ bits: "4", name: "init_wip", desc: "Flash controller undergoing init, inclusive of phy init"},
- { bits: "16:8", name: "error_addr", desc: "Flash controller error address."},
+ { bits: "${8 + bank_width + page_width -1}:8", name: "error_addr", desc: "Flash controller error address."},
]
},
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
index 7709d19..a3ea1ac 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
@@ -612,11 +612,13 @@
//////////////////////////////////////
info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] reg2hw_info_page_cfgs;
info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] info_page_cfgs;
+ localparam int InfoBits = $bits(info_page_cfg_t) * InfosPerBank;
// transform from reg output to structure
+ // Not all types have the maximum number of banks, so those are packed to 0
% for bank in range(cfg['banks']):
% for idx in range(cfg['info_types']):
- assign reg2hw_info_page_cfgs[${bank}][${idx}] = reg2hw.bank${bank}_info${idx}_page_cfg;
+ assign reg2hw_info_page_cfgs[${bank}][${idx}] = InfoBits'(reg2hw.bank${bank}_info${idx}_page_cfg);
% endfor
% endfor
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl_pkg.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl_pkg.sv.tpl
index df5b8b9..f8090fc 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl_pkg.sv.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl_pkg.sv.tpl
@@ -65,9 +65,15 @@
// The end address in bus words for each kind of partition in each bank
parameter logic [PageW-1:0] DataPartitionEndAddr = PagesPerBank - 1;
+ //parameter logic [PageW-1:0] InfoPartitionEndAddr [InfoTypes] = '{
+ % for type in range((cfg['info_types'])):
+ // ${cfg['infos_per_bank'][type]-1}${"," if not loop.last else ""}
+ % endfor
+ //};
parameter logic [PageW-1:0] InfoPartitionEndAddr [InfoTypes] = '{
- InfoTypeSize[0] - 1,
- InfoTypeSize[1] - 1
+ % for type in range((cfg['info_types'])):
+ InfoTypeSize[${type}] - 1${"," if not loop.last else ""}
+ % endfor
};
////////////////////////////
diff --git a/hw/ip/flash_ctrl/lint/flash_ctrl.waiver b/hw/ip/flash_ctrl/lint/flash_ctrl.waiver
index 192c86b..9c6f697 100644
--- a/hw/ip/flash_ctrl/lint/flash_ctrl.waiver
+++ b/hw/ip/flash_ctrl/lint/flash_ctrl.waiver
@@ -8,6 +8,10 @@
waive -rules TERMINAL_STATE -location {flash_ctrl_lcmgr.sv} -regexp {.*StInvalid.*} \
-comment "StInvalid is intended to be a terminal state"
+# Not all configurations for every info type is used
+waive -rules INPUT_NOT_READ: -location {flash_ctrl_info_cfg.sv} -regexp {.*cfgs_i.*} \
+ -comment "For info types that have fewer pages, the full config is not used"
+
# Remove errors from prim_* modules
# TBD These should be directly addressed in primgen modules long term
waive -rules INPUT_NOT_READ -location {prim_flop.sv} -regexp {Input port.*} \
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy.sv b/hw/ip/flash_ctrl/rtl/flash_phy.sv
index 72fb1a4..935be6c 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy.sv
@@ -235,6 +235,7 @@
.NumBanks(NumBanks),
.InfosPerBank(InfosPerBank),
.InfoTypes(InfoTypes),
+ .InfoTypesWidth(InfoTypesWidth),
.PagesPerBank(PagesPerBank),
.WordsPerPage(WordsPerPage),
.DataWidth(flash_phy_pkg::FullDataWidth),
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 4f0cd19..6a2bcbe 100755
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -455,8 +455,8 @@
type: "eflash",
base_addr: "0x20000000",
banks: 2,
- pages_per_bank: 256,
- program_resolution: 128, // maximum number of flash words allowed to program at one time
+ pages_per_bank: 128,
+ program_resolution: 8, // maximum number of flash words allowed to program at one time
swaccess: "ro",
inter_signal_list: [
{ struct: "flash", // flash_req_t, flash_rsp_t
diff --git a/util/reggen/validate.py b/util/reggen/validate.py
index 6287659..2de341b 100644
--- a/util/reggen/validate.py
+++ b/util/reggen/validate.py
@@ -1236,13 +1236,13 @@
('swaccess', mreg['swaccess']),
('hwaccess', mreg['hwaccess']),
('shadowed', mreg['shadowed']),
- ('regwen_multi', mreg['regwen_multi']),
('compact', mreg['compact']),
('fields', []),
])
template_reg['tags'] = mreg['tags'] if 'tags' in mreg else []
template_reg['regwen'] = mreg['regwen'] if 'regwen' in mreg else []
+ template_reg['regwen_multi'] = False if mcount == 1 else mreg['regwen_multi']
# msb of the field bitmask
# Should probably consider making the validate_field return a class so that we do not
diff --git a/util/topgen/validate.py b/util/topgen/validate.py
index 5bfefbd..fa23e1f 100644
--- a/util/topgen/validate.py
+++ b/util/topgen/validate.py
@@ -169,11 +169,11 @@
self.banks = mem['banks']
self.pages_per_bank = mem['pages_per_bank']
self.program_resolution = mem['program_resolution']
- self.words_per_page = 128
+ self.words_per_page = 256
self.data_width = 64
self.metadata_width = 12
- self.info_types = 2
- self.infos_per_bank = [4, 4]
+ self.info_types = 3
+ self.infos_per_bank = [10, 1, 2]
def is_pow2(self, n):
return (n != 0) and (n & (n - 1) == 0)
