[otbn] Remove auto-inferred latch in controller
This is related to lowRISC/OpenTitan#3773.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
diff --git a/hw/ip/otbn/rtl/otbn_controller.sv b/hw/ip/otbn/rtl/otbn_controller.sv
index 8f8a049..8f0d949 100644
--- a/hw/ip/otbn/rtl/otbn_controller.sv
+++ b/hw/ip/otbn/rtl/otbn_controller.sv
@@ -284,7 +284,13 @@
insn_dec_bignum_i.a_wlen_word_inc: begin
increment_out = {{32-DmemAddrWidth{1'b0}}, rf_base_rd_data_a_wlen_word_inc};
end
- default: ;
+ default: begin
+ // Whenever increment_out is written back to the register file, exactly one of the
+ // increment selector signals is high. To prevent the automatic inference of latches in
+ // case nothing is written back (rf_wdata_sel != RfWdSelIncr) and to save logic, we choose
+ // a valid output as default.
+ increment_out = {27'b0, rf_base_rd_data_a_inc};
+ end
endcase
end
diff --git a/hw/ip/otbn/rtl/otbn_decoder.sv b/hw/ip/otbn/rtl/otbn_decoder.sv
index 215f352..4e38e88 100644
--- a/hw/ip/otbn/rtl/otbn_decoder.sv
+++ b/hw/ip/otbn/rtl/otbn_decoder.sv
@@ -872,6 +872,10 @@
`ASSERT(BignumRegIncOnehot,
insn_valid_o |-> $onehot0({a_inc_bignum, a_wlen_word_inc_bignum, b_inc_bignum, d_inc_bignum}))
+ // RfWdSelIncr requires active selection
+ `ASSERT(BignumRegIncReq, rf_wdata_sel_base == RfWdSelIncr
+ |-> $onehot({a_inc_bignum, a_wlen_word_inc_bignum, b_inc_bignum, d_inc_bignum}))
+
`ASSERT(BaseRenOnBignumIndirectA, insn_valid_o & rf_a_indirect_bignum |-> rf_ren_a_base);
`ASSERT(BaseRenOnBignumIndirectB, insn_valid_o & rf_b_indirect_bignum |-> rf_ren_b_base);
`ASSERT(BaseRenOnBignumIndirectD, insn_valid_o & rf_d_indirect_bignum |-> rf_ren_b_base);
