[top] Auto-generated files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index a889a7b..563fcb7 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -28,7 +28,7 @@
{
name: io
aon: no
- freq: "100000000"
+ freq: "96000000"
derived: no
params: {}
}
@@ -54,7 +54,14 @@
aon: no
div: 2
src: io
- freq: "50000000"
+ freq: "48000000"
+ }
+ {
+ name: io_div4
+ aon: no
+ div: 4
+ src: io
+ freq: "24000000"
}
]
groups:
@@ -197,6 +204,13 @@
clk: io_div2
}
{
+ name: por_io_div4
+ gen: true
+ type: top
+ parent: por_aon
+ clk: io_div4
+ }
+ {
name: por_usb
gen: true
type: top
@@ -1557,6 +1571,7 @@
rst_io_ni: por_io
rst_usb_ni: por_usb
rst_io_div2_ni: por_io_div2
+ rst_io_div4_ni: por_io_div4
}
base_addr: 0x400C0000
generated: "true"
@@ -4492,6 +4507,7 @@
por: rstmgr_resets.rst_por_n
por_io: rstmgr_resets.rst_por_io_n
por_io_div2: rstmgr_resets.rst_por_io_div2_n
+ por_io_div4: rstmgr_resets.rst_por_io_div4_n
por_usb: rstmgr_resets.rst_por_usb_n
lc: rstmgr_resets.rst_lc_n
sys: rstmgr_resets.rst_sys_n
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
index 2cbcfef..f86a4ee 100644
--- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -61,7 +61,7 @@
clk_rst_if_main.set_active(.drive_rst_n_val(0));
clk_rst_if_main.set_freq_khz(100000000 / 1000);
clk_rst_if_io.set_active(.drive_rst_n_val(0));
- clk_rst_if_io.set_freq_khz(100000000 / 1000);
+ clk_rst_if_io.set_freq_khz(96000000 / 1000);
// bypass clkmgr, force clocks directly
force tb.dut.top_earlgrey.u_xbar_main.clk_main_i = clk_main;
diff --git a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
index 28efddf..949af54 100644
--- a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
+++ b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
@@ -24,6 +24,7 @@
"rst_io_ni"
"rst_usb_ni"
"rst_io_div2_ni"
+ "rst_io_div4_ni"
]
bus_device: "tlul",
regwidth: "32",
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
index c8593e1..a6278ae 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -33,6 +33,7 @@
// Resets for derived clocks
// clocks are derived locally
input rst_io_div2_ni,
+ input rst_io_div4_ni,
// Bus Interface
input tlul_pkg::tl_h2d_t tl_i,
@@ -74,9 +75,22 @@
// Divided clocks
////////////////////////////////////////////////////
logic clk_io_div2_i;
+ logic clk_io_div4_i;
- assign clk_io_div2_i = clk_io_i;
-
+ prim_clock_div #(
+ .Divisor(2)
+ ) u_io_div2_div (
+ .clk_i(clk_io_i),
+ .rst_ni(rst_io_ni),
+ .clk_o(clk_io_div2_i)
+ );
+ prim_clock_div #(
+ .Divisor(4)
+ ) u_io_div4_div (
+ .clk_i(clk_io_i),
+ .rst_ni(rst_io_ni),
+ .clk_o(clk_io_div4_i)
+ );
////////////////////////////////////////////////////
@@ -105,8 +119,10 @@
logic clk_usb_en;
logic clk_io_div2_root;
logic clk_io_div2_en;
+ logic clk_io_div4_root;
+ logic clk_io_div4_en;
- prim_clock_gating_sync i_main_cg (
+ prim_clock_gating_sync u_main_cg (
.clk_i(clk_main_i),
.rst_ni(rst_main_ni),
.test_en_i(dft_i.test_en),
@@ -114,7 +130,7 @@
.en_o(clk_main_en),
.clk_o(clk_main_root)
);
- prim_clock_gating_sync i_io_cg (
+ prim_clock_gating_sync u_io_cg (
.clk_i(clk_io_i),
.rst_ni(rst_io_ni),
.test_en_i(dft_i.test_en),
@@ -122,7 +138,7 @@
.en_o(clk_io_en),
.clk_o(clk_io_root)
);
- prim_clock_gating_sync i_usb_cg (
+ prim_clock_gating_sync u_usb_cg (
.clk_i(clk_usb_i),
.rst_ni(rst_usb_ni),
.test_en_i(dft_i.test_en),
@@ -130,7 +146,7 @@
.en_o(clk_usb_en),
.clk_o(clk_usb_root)
);
- prim_clock_gating_sync i_io_div2_cg (
+ prim_clock_gating_sync u_io_div2_cg (
.clk_i(clk_io_div2_i),
.rst_ni(rst_io_div2_ni),
.test_en_i(dft_i.test_en),
@@ -138,20 +154,29 @@
.en_o(clk_io_div2_en),
.clk_o(clk_io_div2_root)
);
+ prim_clock_gating_sync u_io_div4_cg (
+ .clk_i(clk_io_div4_i),
+ .rst_ni(rst_io_div4_ni),
+ .test_en_i(dft_i.test_en),
+ .async_en_i(pwr_i.ip_clk_en),
+ .en_o(clk_io_div4_en),
+ .clk_o(clk_io_div4_root)
+ );
// an async OR of all the synchronized enables
assign async_roots_en =
clk_main_en |
clk_io_en |
clk_usb_en |
- clk_io_div2_en;
+ clk_io_div2_en |
+ clk_io_div4_en;
// Sync the OR back into clkmgr domain for feedback to pwrmgr.
// Since the signal is combo / converged on the other side, de-bounce
// the signal prior to output
prim_flop_2sync #(
.Width(1)
- ) i_roots_en_sync (
+ ) u_roots_en_sync (
.clk_i,
.rst_ni,
.d_i(async_roots_en),
@@ -192,14 +217,14 @@
prim_flop_2sync #(
.Width(1)
- ) i_clk_io_peri_sw_en_sync (
+ ) u_clk_io_peri_sw_en_sync (
.clk_i(clk_io_i),
.rst_ni(rst_io_ni),
.d_i(reg2hw.clk_enables.clk_io_peri_en.q),
.q_o(clk_io_peri_sw_en)
);
- prim_clock_gating i_clk_io_peri_cg (
+ prim_clock_gating u_clk_io_peri_cg (
.clk_i(clk_io_i),
.en_i(clk_io_peri_sw_en & clk_io_en),
.test_en_i(dft_i.test_en),
@@ -208,14 +233,14 @@
prim_flop_2sync #(
.Width(1)
- ) i_clk_usb_peri_sw_en_sync (
+ ) u_clk_usb_peri_sw_en_sync (
.clk_i(clk_usb_i),
.rst_ni(rst_usb_ni),
.d_i(reg2hw.clk_enables.clk_usb_peri_en.q),
.q_o(clk_usb_peri_sw_en)
);
- prim_clock_gating i_clk_usb_peri_cg (
+ prim_clock_gating u_clk_usb_peri_cg (
.clk_i(clk_usb_i),
.en_i(clk_usb_peri_sw_en & clk_usb_en),
.test_en_i(dft_i.test_en),
@@ -240,14 +265,14 @@
prim_flop_2sync #(
.Width(1)
- ) i_clk_main_aes_hint_sync (
+ ) u_clk_main_aes_hint_sync (
.clk_i(clk_main_i),
.rst_ni(rst_main_ni),
.d_i(reg2hw.clk_hints.clk_main_aes_hint.q),
.q_o(clk_main_aes_hint)
);
- prim_clock_gating i_clk_main_aes_cg (
+ prim_clock_gating u_clk_main_aes_cg (
.clk_i(clk_main_i),
.en_i(clk_main_aes_en & clk_main_en),
.test_en_i(dft_i.test_en),
@@ -258,14 +283,14 @@
prim_flop_2sync #(
.Width(1)
- ) i_clk_main_hmac_hint_sync (
+ ) u_clk_main_hmac_hint_sync (
.clk_i(clk_main_i),
.rst_ni(rst_main_ni),
.d_i(reg2hw.clk_hints.clk_main_hmac_hint.q),
.q_o(clk_main_hmac_hint)
);
- prim_clock_gating i_clk_main_hmac_cg (
+ prim_clock_gating u_clk_main_hmac_cg (
.clk_i(clk_main_i),
.en_i(clk_main_hmac_en & clk_main_en),
.test_en_i(dft_i.test_en),
@@ -276,14 +301,14 @@
prim_flop_2sync #(
.Width(1)
- ) i_clk_main_otbn_hint_sync (
+ ) u_clk_main_otbn_hint_sync (
.clk_i(clk_main_i),
.rst_ni(rst_main_ni),
.d_i(reg2hw.clk_hints.clk_main_otbn_hint.q),
.q_o(clk_main_otbn_hint)
);
- prim_clock_gating i_clk_main_otbn_cg (
+ prim_clock_gating u_clk_main_otbn_cg (
.clk_i(clk_main_i),
.en_i(clk_main_otbn_en & clk_main_en),
.test_en_i(dft_i.test_en),
@@ -305,4 +330,4 @@
////////////////////////////////////////////////////
-endmodule // rstmgr
+endmodule // clkmgr
diff --git a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
index d46a75f..7de0089 100644
--- a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
+++ b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
@@ -20,6 +20,7 @@
"clk_io_div2_i"
"clk_main_i"
"clk_io_i"
+ "clk_io_div4_i"
"clk_usb_i"
],
bus_device: "tlul",
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
index 5a56bd8..3b7ad24 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -23,6 +23,7 @@
input clk_io_div2_i,
input clk_main_i,
input clk_io_i,
+ input clk_io_div4_i,
input clk_usb_i,
// Bus Interface
@@ -173,6 +174,16 @@
prim_flop_2sync #(
.Width(1),
.ResetValue('0)
+ ) u_por_io_div4 (
+ .clk_i(clk_io_div4_i),
+ .rst_ni(rst_por_aon_n),
+ .d_i(1'b1),
+ .q_o(resets_o.rst_por_io_div4_n)
+ );
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
) u_por_usb (
.clk_i(clk_usb_i),
.rst_ni(rst_por_aon_n),
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
index 07e9169..ccc692f 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
@@ -44,6 +44,7 @@
logic rst_por_n;
logic rst_por_io_n;
logic rst_por_io_div2_n;
+ logic rst_por_io_div4_n;
logic rst_por_usb_n;
logic rst_lc_n;
logic rst_sys_n;
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 744f5dd..f05f4df 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -838,7 +838,8 @@
.rst_main_ni (rstmgr_resets.rst_por_n),
.rst_io_ni (rstmgr_resets.rst_por_io_n),
.rst_usb_ni (rstmgr_resets.rst_por_usb_n),
- .rst_io_div2_ni (rstmgr_resets.rst_por_io_div2_n)
+ .rst_io_div2_ni (rstmgr_resets.rst_por_io_div2_n),
+ .rst_io_div4_ni (rstmgr_resets.rst_por_io_div4_n)
);
nmi_gen u_nmi_gen (
