[dif, rv_core_ibex] Create the dif
- Fixes the `rv_core_ibex.hjson` in order autogenerate the dif.
Signed-off-by: Douglas Reis <doreis@lowrisc.org>
diff --git a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
index 222ffd1..6a2c225 100644
--- a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
+++ b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
@@ -171,33 +171,25 @@
# Random netlist constants
{ name: "RndCnstLfsrSeed",
type: "ibex_pkg::lfsr_seed_t",
- desc: '''
- Default seed of the PRNG used for random instructions.
- '''
+ desc: "Default seed of the PRNG used for random instructions."
randcount: "32",
randtype: "data"
},
{ name: "RndCnstLfsrPerm",
type: "ibex_pkg::lfsr_perm_t",
- desc: '''
- Permutation applied to the LFSR of the PRNG used for random instructions.
- '''
+ desc: "Permutation applied to the LFSR of the PRNG used for random instructions."
randcount: "32",
randtype: "perm"
},
{ name: "RndCnstIbexKeyDefault",
type: "logic [ibex_pkg::SCRAMBLE_KEY_W-1:0]",
- desc: '''
- Default icache scrambling key
- '''
+ desc: "Default icache scrambling key"
randcount: "128",
randtype: "data"
},
{ name: "RndCnstIbexNonceDefault",
type: "logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0]",
- desc: '''
- Default icache scrambling nonce
- '''
+ desc: "Default icache scrambling nonce"
randcount: "64",
randtype: "data"
},
@@ -205,9 +197,7 @@
{ name: "PMPEnable"
type: "bit"
default: "1'b0"
- desc: '''
- Enable PMP
- '''
+ desc: "Enable PMP"
local: "false"
expose: "true"
},
@@ -215,6 +205,7 @@
{ name: "PMPGranularity"
type: "int unsigned"
default: "0"
+ desc: "PMP Granularity"
local: "false"
expose: "true"
},
@@ -222,6 +213,7 @@
{ name: "PMPNumRegions"
type: "int unsigned"
default: "4"
+ desc: "PMP number of regions"
local: "false"
expose: "true"
},
@@ -229,6 +221,7 @@
{ name: "MHPMCounterNum"
type: "int unsigned"
default: "10"
+ desc: "Number of the MHPM counter "
local: "false"
expose: "true"
},
@@ -236,6 +229,7 @@
{ name: "MHPMCounterWidth"
type: "int unsigned"
default: "32"
+ desc: "Width of the MHPM Counter "
local: "false"
expose: "true"
},
@@ -243,6 +237,7 @@
{ name: "RV32E"
type: "bit"
default: "0"
+ desc: "RV32E"
local: "false"
expose: "true"
},
@@ -250,6 +245,7 @@
{ name: "RV32M"
type: "ibex_pkg::rv32m_e"
default: "ibex_pkg::RV32MSingleCycle"
+ desc: "RV32M"
local: "false"
expose: "true"
},
@@ -257,6 +253,7 @@
{ name: "RV32B"
type: "ibex_pkg::rv32b_e"
default: "ibex_pkg::RV32BNone"
+ desc: "RV32B"
local: "false"
expose: "true"
},
@@ -264,6 +261,7 @@
{ name: "RegFile"
type: "ibex_pkg::regfile_e"
default: "ibex_pkg::RegFileFF"
+ desc: "Reg file"
local: "false"
expose: "true"
},
@@ -271,6 +269,7 @@
{ name: "BranchTargetALU"
type: "bit"
default: "1'b1"
+ desc: "Branch target ALU"
local: "false"
expose: "true"
},
@@ -278,6 +277,7 @@
{ name: "WritebackStage"
type: "bit"
default: "1'b1"
+ desc: "Write back stage"
local: "false"
expose: "true"
},
@@ -285,6 +285,7 @@
{ name: "ICache"
type: "bit"
default: "0"
+ desc: "Instruction cache"
local: "false"
expose: "true"
},
@@ -292,6 +293,7 @@
{ name: "ICacheECC"
type: "bit"
default: "0"
+ desc: "Instruction cache ECC"
local: "false"
expose: "true"
},
@@ -299,6 +301,7 @@
{ name: "ICacheScramble"
type: "bit"
default: "0"
+ desc: "Scramble instruction cach"
local: "false"
expose: "true"
},
@@ -306,6 +309,7 @@
{ name: "BranchPredictor"
type: "bit"
default: "0"
+ desc: "Branch predictor"
local: "false"
expose: "true"
},
@@ -313,6 +317,7 @@
{ name: "DbgTriggerEn"
type: "bit"
default: "1"
+ desc: "Enable degug trigger"
local: "false"
expose: "true"
},
@@ -320,6 +325,7 @@
{ name: "DbgHwBreakNum"
type: "int"
default: "1"
+ desc: "Number of debug hardware break"
local: "false"
expose: "true"
},
@@ -327,6 +333,7 @@
{ name: "SecureIbex"
type: "bit"
default: "0"
+ desc: "Width of the MHPM Counter "
local: "false"
expose: "true"
},
@@ -334,6 +341,7 @@
{ name: "DmHaltAddr"
type: "int unsigned"
default: "437323776" //"32'h1A110800"
+ desc: "Halt address"
local: "false"
expose: "true"
},
@@ -341,6 +349,7 @@
{ name: "DmExceptionAddr"
type: "int unsigned"
default: "437323784" //"32'h1A110808"
+ desc: "Exception address"
local: "false"
expose: "true"
},
@@ -348,6 +357,7 @@
{ name: "PipeLine"
type: "bit"
default: "1'b0"
+ desc: "Pipe line"
local: "false"
expose: "true"
},
@@ -367,9 +377,7 @@
},
{ name: "NumScratchWords",
type: "int",
- desc: '''
- Number of scratch words maintained.
- '''
+ desc: "Number of scratch words maintained."
default: "8"
},
],
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 1910b70..4514dfa 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -7108,6 +7108,7 @@
}
{
name: PMPGranularity
+ desc: PMP Granularity
type: int unsigned
default: "0"
expose: "true"
@@ -7115,6 +7116,7 @@
}
{
name: PMPNumRegions
+ desc: PMP number of regions
type: int unsigned
default: "16"
expose: "true"
@@ -7122,6 +7124,7 @@
}
{
name: MHPMCounterNum
+ desc: "Number of the MHPM counter "
type: int unsigned
default: "10"
expose: "true"
@@ -7129,6 +7132,7 @@
}
{
name: MHPMCounterWidth
+ desc: "Width of the MHPM Counter "
type: int unsigned
default: "32"
expose: "true"
@@ -7136,6 +7140,7 @@
}
{
name: RV32E
+ desc: RV32E
type: bit
default: "0"
expose: "true"
@@ -7143,6 +7148,7 @@
}
{
name: RV32M
+ desc: RV32M
type: ibex_pkg::rv32m_e
default: ibex_pkg::RV32MSingleCycle
expose: "true"
@@ -7150,6 +7156,7 @@
}
{
name: RV32B
+ desc: RV32B
type: ibex_pkg::rv32b_e
default: ibex_pkg::RV32BOTEarlGrey
expose: "true"
@@ -7157,6 +7164,7 @@
}
{
name: RegFile
+ desc: Reg file
type: ibex_pkg::regfile_e
default: ibex_pkg::RegFileFF
expose: "true"
@@ -7164,6 +7172,7 @@
}
{
name: BranchTargetALU
+ desc: Branch target ALU
type: bit
default: "1"
expose: "true"
@@ -7171,6 +7180,7 @@
}
{
name: WritebackStage
+ desc: Write back stage
type: bit
default: "1"
expose: "true"
@@ -7178,6 +7188,7 @@
}
{
name: ICache
+ desc: Instruction cache
type: bit
default: "1"
expose: "true"
@@ -7185,6 +7196,7 @@
}
{
name: ICacheECC
+ desc: Instruction cache ECC
type: bit
default: "1"
expose: "true"
@@ -7192,6 +7204,7 @@
}
{
name: ICacheScramble
+ desc: Scramble instruction cach
type: bit
default: "1"
expose: "true"
@@ -7199,6 +7212,7 @@
}
{
name: BranchPredictor
+ desc: Branch predictor
type: bit
default: "0"
expose: "true"
@@ -7206,6 +7220,7 @@
}
{
name: DbgTriggerEn
+ desc: Enable degug trigger
type: bit
default: "1"
expose: "true"
@@ -7213,6 +7228,7 @@
}
{
name: DbgHwBreakNum
+ desc: Number of debug hardware break
type: int
default: "4"
expose: "true"
@@ -7220,6 +7236,7 @@
}
{
name: SecureIbex
+ desc: "Width of the MHPM Counter "
type: bit
default: "1"
expose: "true"
@@ -7227,6 +7244,7 @@
}
{
name: DmHaltAddr
+ desc: Halt address
type: int unsigned
default: tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::HaltAddress[31:0]
expose: "true"
@@ -7234,6 +7252,7 @@
}
{
name: DmExceptionAddr
+ desc: Exception address
type: int unsigned
default: tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::ExceptionAddress[31:0]
expose: "true"
@@ -7241,6 +7260,7 @@
}
{
name: PipeLine
+ desc: Pipe line
type: bit
default: "0"
expose: "true"
diff --git a/sw/device/lib/dif/BUILD b/sw/device/lib/dif/BUILD
index 038d957..3e5ee1e 100644
--- a/sw/device/lib/dif/BUILD
+++ b/sw/device/lib/dif/BUILD
@@ -822,6 +822,34 @@
)
cc_library(
+ name = "rv_core_ibex",
+ srcs = [
+ "autogen/dif_rv_core_ibex_autogen.c",
+ "autogen/dif_rv_core_ibex_autogen.h",
+ ],
+ hdrs = [
+ ],
+ deps = [
+ ":base",
+ "//hw/ip/rv_core_ibex/data:rv_core_ibex_regs",
+ "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+ "//sw/device/lib/base:mmio",
+ ],
+)
+
+cc_test(
+ name = "rv_core_ibex_unittest",
+ srcs = [
+ "autogen/dif_rv_core_ibex_autogen_unittest.cc",
+ ],
+ deps = [
+ ":rv_core_ibex",
+ ":test_base",
+ "@googletest//:gtest_main",
+ ],
+)
+
+cc_library(
name = "rv_plic",
srcs = [
"autogen/dif_rv_plic_autogen.c",
diff --git a/sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen.c b/sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen.c
new file mode 100644
index 0000000..1f82223
--- /dev/null
+++ b/sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen.c
@@ -0,0 +1,54 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
+// util/make_new_dif.py --mode=regen --only=autogen
+
+#include "sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen.h"
+#include <stdint.h>
+
+#include "rv_core_ibex_regs.h" // Generated.
+
+OT_WARN_UNUSED_RESULT
+dif_result_t dif_rv_core_ibex_init(mmio_region_t base_addr,
+ dif_rv_core_ibex_t *rv_core_ibex) {
+ if (rv_core_ibex == NULL) {
+ return kDifBadArg;
+ }
+
+ rv_core_ibex->base_addr = base_addr;
+
+ return kDifOk;
+}
+
+dif_result_t dif_rv_core_ibex_alert_force(
+ const dif_rv_core_ibex_t *rv_core_ibex, dif_rv_core_ibex_alert_t alert) {
+ if (rv_core_ibex == NULL) {
+ return kDifBadArg;
+ }
+
+ bitfield_bit32_index_t alert_idx;
+ switch (alert) {
+ case kDifRvCoreIbexAlertFatalSwErr:
+ alert_idx = RV_CORE_IBEX_ALERT_TEST_FATAL_SW_ERR_BIT;
+ break;
+ case kDifRvCoreIbexAlertRecovSwErr:
+ alert_idx = RV_CORE_IBEX_ALERT_TEST_RECOV_SW_ERR_BIT;
+ break;
+ case kDifRvCoreIbexAlertFatalHwErr:
+ alert_idx = RV_CORE_IBEX_ALERT_TEST_FATAL_HW_ERR_BIT;
+ break;
+ case kDifRvCoreIbexAlertRecovHwErr:
+ alert_idx = RV_CORE_IBEX_ALERT_TEST_RECOV_HW_ERR_BIT;
+ break;
+ default:
+ return kDifBadArg;
+ }
+
+ uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
+ mmio_region_write32(rv_core_ibex->base_addr,
+ RV_CORE_IBEX_ALERT_TEST_REG_OFFSET, alert_test_reg);
+
+ return kDifOk;
+}
diff --git a/sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen.h b/sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen.h
new file mode 100644
index 0000000..2e2a6b9
--- /dev/null
+++ b/sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen.h
@@ -0,0 +1,93 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef OPENTITAN_SW_DEVICE_LIB_DIF_AUTOGEN_DIF_RV_CORE_IBEX_AUTOGEN_H_
+#define OPENTITAN_SW_DEVICE_LIB_DIF_AUTOGEN_DIF_RV_CORE_IBEX_AUTOGEN_H_
+
+// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
+// util/make_new_dif.py --mode=regen --only=autogen
+
+/**
+ * @file
+ * @brief <a href="/hw/ip/rv_core_ibex/doc/">RV_CORE_IBEX</a> Device Interface
+ * Functions
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "sw/device/lib/base/macros.h"
+#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_base.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+/**
+ * A handle to rv_core_ibex.
+ *
+ * This type should be treated as opaque by users.
+ */
+typedef struct dif_rv_core_ibex {
+ /**
+ * The base address for the rv_core_ibex hardware registers.
+ */
+ mmio_region_t base_addr;
+} dif_rv_core_ibex_t;
+
+/**
+ * Creates a new handle for a(n) rv_core_ibex peripheral.
+ *
+ * This function does not actuate the hardware.
+ *
+ * @param base_addr The MMIO base address of the rv_core_ibex peripheral.
+ * @param[out] rv_core_ibex Out param for the initialized handle.
+ * @return The result of the operation.
+ */
+OT_WARN_UNUSED_RESULT
+dif_result_t dif_rv_core_ibex_init(mmio_region_t base_addr,
+ dif_rv_core_ibex_t *rv_core_ibex);
+
+/**
+ * A rv_core_ibex alert type.
+ */
+typedef enum dif_rv_core_ibex_alert {
+ /**
+ * Software triggered alert for fatal faults
+ */
+ kDifRvCoreIbexAlertFatalSwErr = 0,
+ /**
+ * Software triggered Alert for recoverable faults
+ */
+ kDifRvCoreIbexAlertRecovSwErr = 1,
+ /**
+ * Triggered when - Ibex raises `alert_major_internal_o` - Ibex raises
+ * `alert_major_bus_o` - A double fault is seen (Ibex raises
+ * `double_fault_seen_o`) - A bus integrity error is seen
+ */
+ kDifRvCoreIbexAlertFatalHwErr = 2,
+ /**
+ * Triggered when Ibex raises `alert_minor_o`
+ */
+ kDifRvCoreIbexAlertRecovHwErr = 3,
+} dif_rv_core_ibex_alert_t;
+
+/**
+ * Forces a particular alert, causing it to be escalated as if the hardware
+ * had raised it.
+ *
+ * @param rv_core_ibex A rv_core_ibex handle.
+ * @param alert The alert to force.
+ * @return The result of the operation.
+ */
+OT_WARN_UNUSED_RESULT
+dif_result_t dif_rv_core_ibex_alert_force(
+ const dif_rv_core_ibex_t *rv_core_ibex, dif_rv_core_ibex_alert_t alert);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif // __cplusplus
+
+#endif // OPENTITAN_SW_DEVICE_LIB_DIF_AUTOGEN_DIF_RV_CORE_IBEX_AUTOGEN_H_
diff --git a/sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen_unittest.cc
new file mode 100644
index 0000000..670664c
--- /dev/null
+++ b/sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen_unittest.cc
@@ -0,0 +1,66 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
+// util/make_new_dif.py --mode=regen --only=autogen
+
+#include "sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen.h"
+
+#include "gtest/gtest.h"
+#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
+
+#include "rv_core_ibex_regs.h" // Generated.
+
+namespace dif_rv_core_ibex_autogen_unittest {
+namespace {
+using ::mock_mmio::MmioTest;
+using ::mock_mmio::MockDevice;
+using ::testing::Eq;
+using ::testing::Test;
+
+class RvCoreIbexTest : public Test, public MmioTest {
+ protected:
+ dif_rv_core_ibex_t rv_core_ibex_ = {.base_addr = dev().region()};
+};
+
+class InitTest : public RvCoreIbexTest {};
+
+TEST_F(InitTest, NullArgs) {
+ EXPECT_DIF_BADARG(dif_rv_core_ibex_init(dev().region(), nullptr));
+}
+
+TEST_F(InitTest, Success) {
+ EXPECT_DIF_OK(dif_rv_core_ibex_init(dev().region(), &rv_core_ibex_));
+}
+
+class AlertForceTest : public RvCoreIbexTest {};
+
+TEST_F(AlertForceTest, NullArgs) {
+ EXPECT_DIF_BADARG(
+ dif_rv_core_ibex_alert_force(nullptr, kDifRvCoreIbexAlertFatalSwErr));
+}
+
+TEST_F(AlertForceTest, BadAlert) {
+ EXPECT_DIF_BADARG(dif_rv_core_ibex_alert_force(
+ nullptr, static_cast<dif_rv_core_ibex_alert_t>(32)));
+}
+
+TEST_F(AlertForceTest, Success) {
+ // Force first alert.
+ EXPECT_WRITE32(RV_CORE_IBEX_ALERT_TEST_REG_OFFSET,
+ {{RV_CORE_IBEX_ALERT_TEST_FATAL_SW_ERR_BIT, true}});
+ EXPECT_DIF_OK(dif_rv_core_ibex_alert_force(&rv_core_ibex_,
+ kDifRvCoreIbexAlertFatalSwErr));
+
+ // Force last alert.
+ EXPECT_WRITE32(RV_CORE_IBEX_ALERT_TEST_REG_OFFSET,
+ {{RV_CORE_IBEX_ALERT_TEST_RECOV_HW_ERR_BIT, true}});
+ EXPECT_DIF_OK(dif_rv_core_ibex_alert_force(&rv_core_ibex_,
+ kDifRvCoreIbexAlertRecovHwErr));
+}
+
+} // namespace
+} // namespace dif_rv_core_ibex_autogen_unittest
diff --git a/sw/device/lib/dif/dif_rv_core_ibex.md b/sw/device/lib/dif/dif_rv_core_ibex.md
new file mode 100644
index 0000000..834fe6b
--- /dev/null
+++ b/sw/device/lib/dif/dif_rv_core_ibex.md
@@ -0,0 +1,52 @@
+---
+title: "Rv core ibex DIF Checklist"
+---
+
+This checklist is for [Development Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [Rv core ibex DIF]({{< relref "hw/ip/rv_core_ibex/doc" >}}).
+All checklist items refer to the content in the [Checklist]({{< relref "/doc/project/checklist.md" >}}).
+
+<h2>DIF Checklist</h2>
+
+<h3>S1</h3>
+
+Type | Item | Resolution | Note/Collaterals
+---------------|----------------------|-------------|------------------
+Implementation | [DIF_EXISTS][] | In Progress |
+Implementation | [DIF_USED_IN_TREE][] | In Progress |
+Tests | [DIF_TEST_SMOKE][] | In Progress |
+
+[DIF_EXISTS]: {{< relref "/doc/project/checklist.md#dif_exists" >}}
+[DIF_USED_IN_TREE]: {{< relref "/doc/project/checklist.md#dif_used_in_tree" >}}
+[DIF_TEST_SMOKE]: {{< relref "/doc/project/checklist.md#dif_test_smoke" >}}
+
+<h3>S2</h3>
+
+Type | Item | Resolution | Note/Collaterals
+---------------|-----------------------------|-------------|------------------
+Coordination | [DIF_HW_FEATURE_COMPLETE][] | Not Started | [HW Dashboard]({{< relref "hw" >}})
+Implementation | [DIF_FEATURES][] | In Progress |
+Coordination | [DIF_DV_TESTS][] | Not Started |
+
+[DIF_HW_FEATURE_COMPLETE]: {{< relref "/doc/project/checklist.md#dif_hw_feature_complete" >}}
+[DIF_FEATURES]: {{< relref "/doc/project/checklist.md#dif_features" >}}
+[DIF_DV_TESTS]: {{< relref "/doc/project/checklist.md#dif_dv_tests" >}}
+
+<h3>S3</h3>
+
+Type | Item | Resolution | Note/Collaterals
+---------------|----------------------------------|-------------|------------------
+Coordination | [DIF_HW_DESIGN_COMPLETE][] | Not Started |
+Coordination | [DIF_HW_VERIFICATION_COMPLETE][] | Not Started |
+Documentation | [DIF_DOC_HW][] | Not Started |
+Code Quality | [DIF_CODE_STYLE][] | Not Started |
+Tests | [DIF_TEST_UNIT][] | In Progress |
+Review | [DIF_TODO_COMPLETE][] | Not Started |
+Review | Reviewer(s) | Not Started |
+Review | Signoff date | Not Started |
+
+[DIF_HW_DESIGN_COMPLETE]: {{< relref "/doc/project/checklist.md#dif_hw_design_complete" >}}
+[DIF_HW_VERIFICATION_COMPLETE]: {{< relref "/doc/project/checklist.md#dif_hw_verification_complete" >}}
+[DIF_DOC_HW]: {{< relref "/doc/project/checklist.md#dif_doc_hw" >}}
+[DIF_CODE_STYLE]: {{< relref "/doc/project/checklist.md#dif_code_style" >}}
+[DIF_TEST_UNIT]: {{< relref "/doc/project/checklist.md#dif_test_unit" >}}
+[DIF_TODO_COMPLETE]: {{< relref "/doc/project/checklist.md#dif_todo_complete" >}}
