[alert_handler] Add SEC_CM labels
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip_templates/alert_handler/data/alert_handler.hjson.tpl b/hw/ip_templates/alert_handler/data/alert_handler.hjson.tpl
index f8ecf82..4852d8c 100644
--- a/hw/ip_templates/alert_handler/data/alert_handler.hjson.tpl
+++ b/hw/ip_templates/alert_handler/data/alert_handler.hjson.tpl
@@ -233,16 +233,13 @@
{ name: "PING_TIMER.CONFIG.REGWEN",
desc: "The ping timer configuration registers are REGWEN protected."
}
- {
- name: "ALERT.CONFIG.REGWEN",
+ { name: "ALERT.CONFIG.REGWEN",
desc: "The individual alert enables are REGWEN protected."
}
- {
- name: "ALERT_LOC.CONFIG.REGWEN",
+ { name: "ALERT_LOC.CONFIG.REGWEN",
desc: "The individual local alert enables are REGWEN protected."
}
- {
- name: "CLASS.CONFIG.REGWEN",
+ { name: "CLASS.CONFIG.REGWEN",
desc: "The class configuration registers are REGWEN protected."
}
{ name: "ALERT.INTERSIG.DIFF",
diff --git a/hw/ip_templates/alert_handler/rtl/alert_handler.sv b/hw/ip_templates/alert_handler/rtl/alert_handler.sv
index 5b3ffc5..1f6b4d1 100644
--- a/hw/ip_templates/alert_handler/rtl/alert_handler.sv
+++ b/hw/ip_templates/alert_handler/rtl/alert_handler.sv
@@ -29,6 +29,7 @@
output logic intr_classc_o,
output logic intr_classd_o,
// Clock gating and reset info from rstmgr and clkmgr
+ // SEC_CM: LPG.INTERSIG.MUBI
input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_cg_en_i,
input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_rst_en_i,
// State information for HW crashdump
@@ -37,9 +38,11 @@
output edn_pkg::edn_req_t edn_o,
input edn_pkg::edn_rsp_t edn_i,
// Alert Sources
+ // SEC_CM: ALERT.INTERSIG.DIFF
input alert_tx_t [NAlerts-1:0] alert_tx_i,
output alert_rx_t [NAlerts-1:0] alert_rx_o,
// Escalation outputs
+ // SEC_CM: ESC.INTERSIG.DIFF
input esc_rx_t [N_ESC_SEV-1:0] esc_rx_i,
output esc_tx_t [N_ESC_SEV-1:0] esc_tx_o
);
@@ -59,6 +62,11 @@
intr_classb_o,
intr_classa_o} = irq;
+ // SEC_CM: CONFIG.SHADOW
+ // SEC_CM: PING_TIMER.CONFIG.REGWEN
+ // SEC_CM: ALERT.CONFIG.REGWEN
+ // SEC_CM: ALERT_LOC.CONFIG.REGWEN
+ // SEC_CM: CLASS.CONFIG.REGWEN
alert_handler_reg_wrap u_reg_wrap (
.clk_i,
.rst_ni,
@@ -70,9 +78,11 @@
.crashdump_o,
.hw2reg_wrap,
.reg2hw_wrap,
+ // SEC_CM: BUS.INTEGRITY
.fatal_integ_alert_o(loc_alert_trig[4])
);
+ // SEC_CM: CONFIG.SHADOW
assign loc_alert_trig[5] = reg2hw_wrap.shadowed_err_update;
assign loc_alert_trig[6] = reg2hw_wrap.shadowed_err_storage;
@@ -121,7 +131,9 @@
// set this to the maximum width in the design.
// can be overridden in DV and FPV to shorten the wait periods.
.wait_cyc_mask_i ( {PING_CNT_DW{1'b1}} ),
+ // SEC_CM: ALERT_RX.INTERSIG.BKGN_CHK
.alert_ping_req_o ( alert_ping_req ),
+ // SEC_CM: ESC_TX.INTERSIG.BKGN_CHK
.esc_ping_req_o ( esc_ping_req ),
.alert_ping_ok_i ( alert_ping_ok ),
.esc_ping_ok_i ( esc_ping_ok ),
@@ -137,6 +149,7 @@
alert_handler_lpg_ctrl u_alert_handler_lpg_ctrl (
.clk_i,
.rst_ni,
+ // SEC_CM: LPG.INTERSIG.MUBI
.lpg_cg_en_i,
.lpg_rst_en_i,
.alert_init_trig_o ( alert_init_trig )
@@ -161,6 +174,7 @@
.ping_ok_o ( alert_ping_ok[k] ),
.integ_fail_o ( alert_integfail[k] ),
.alert_o ( alert_trig[k] ),
+ // SEC_CM: ALERT.INTERSIG.DIFF
.alert_rx_o ( alert_rx_o[k] ),
.alert_tx_i ( alert_tx_i[k] )
);
@@ -241,7 +255,11 @@
end
assign esc_sig_req[k] = |esc_sig_req_trsp[k];
-
+ // SEC_CM: ESC_RX.INTERSIG.BKGN_CHK
+ // Note: This countermeasure is actually implemented on the receiver side. We currently cannot
+ // put this RTL label inside that module due to the way our countermeasure annotation check
+ // script discovers the RTL files. The label is thus put here. Please refer to
+ // prim_esc_receiver.sv for the actual implementation of this mechanism.
prim_esc_sender u_esc_sender (
.clk_i,
.rst_ni,
@@ -249,6 +267,7 @@
.ping_ok_o ( esc_ping_ok[k] ),
.integ_fail_o ( esc_integfail[k] ),
.esc_req_i ( esc_sig_req[k] ),
+ // SEC_CM: ESC.INTERSIG.DIFF
.esc_rx_i ( esc_rx_i[k] ),
.esc_tx_o ( esc_tx_o[k] )
);
diff --git a/hw/ip_templates/alert_handler/rtl/alert_handler_accu.sv b/hw/ip_templates/alert_handler/rtl/alert_handler_accu.sv
index f8d5bd7..c7b7dec 100644
--- a/hw/ip_templates/alert_handler/rtl/alert_handler_accu.sv
+++ b/hw/ip_templates/alert_handler/rtl/alert_handler_accu.sv
@@ -28,6 +28,7 @@
assign trig_gated = class_trig_i & class_en_i;
assign accu_en = trig_gated && !(&accu_cnt_o);
+ // SEC_CM: ACCU.CTR.REDUN
// We employ two redundant counters to guard against FI attacks.
// If any of the two is glitched and the two counter states do not agree,
// the check_fail_o signal is asserted which will move the corresponding escalation
diff --git a/hw/ip_templates/alert_handler/rtl/alert_handler_esc_timer.sv b/hw/ip_templates/alert_handler/rtl/alert_handler_esc_timer.sv
index e5d2f2e..e12bb77 100644
--- a/hw/ip_templates/alert_handler/rtl/alert_handler_esc_timer.sv
+++ b/hw/ip_templates/alert_handler/rtl/alert_handler_esc_timer.sv
@@ -52,6 +52,7 @@
// are permanently asserted.
logic cnt_en, cnt_clr, cnt_error;
+ // SEC_CM: ESC_TIMER.CTR.REDUN
prim_count #(
.Width(EscCntDw),
.OutSelDnCnt(0), // count up
@@ -83,6 +84,7 @@
logic [N_PHASES-1:0] phase_oh;
+ // SEC_CM: ESC_TIMER.FSM.SPARSE
// Encoding generated with:
// $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
// -s 784905746 --language=sv
@@ -260,6 +262,7 @@
esc_state_o = FsmError;
fsm_error = 1'b1;
end
+ // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
// catch glitches.
default: begin
state_d = FsmErrorSt;
@@ -267,6 +270,7 @@
end
endcase
+ // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
// if any of the duplicate counter pairs has an inconsistent state
// we move into the terminal FSM error state.
if (accu_fail_i || cnt_error) begin
@@ -279,6 +283,7 @@
// generate configuration mask for escalation enable signals
assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
// mask reduce current phase state vector
+ // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
end
diff --git a/hw/ip_templates/alert_handler/rtl/alert_handler_ping_timer.sv b/hw/ip_templates/alert_handler/rtl/alert_handler_ping_timer.sv
index 346c2ad..3734413 100644
--- a/hw/ip_templates/alert_handler/rtl/alert_handler_ping_timer.sv
+++ b/hw/ip_templates/alert_handler/rtl/alert_handler_ping_timer.sv
@@ -88,6 +88,7 @@
logic [PING_CNT_DW + IdDw - 1:0] lfsr_state;
assign entropy = (reseed_en) ? edn_data_i[LfsrWidth-1:0] : '0;
+ // SEC_CM: PING_TIMER.LFSR.REDUN
// We employ two redundant LFSRs to guard against FI attacks.
// If any of the two is glitched and the two LFSR states do not agree,
// the FSM below is moved into a terminal error state and all ping alerts
@@ -164,6 +165,7 @@
logic [PING_CNT_DW-1:0] esc_cnt;
assign esc_cnt_clr = (esc_cnt >= PING_CNT_DW'(N_ESC_SEV-1)) && esc_cnt_en;
+ // SEC_CM: PING_TIMER.CTR.REDUN
prim_count #(
.Width(PING_CNT_DW),
.OutSelDnCnt(0), // count up
@@ -196,6 +198,7 @@
assign timer_expired = (cnt == '0);
assign cnt_set = wait_cnt_set || timeout_cnt_set;
+ // SEC_CM: PING_TIMER.CTR.REDUN
prim_count #(
.Width(PING_CNT_DW),
.OutSelDnCnt(1), // count down
@@ -248,6 +251,7 @@
.out_o(spurious_esc_ping)
);
+ // SEC_CM: PING_TIMER.FSM.SPARSE
// Encoding generated with:
// $ ./util/design/sparse-fsm-encode.py -d 5 -m 6 -n 9 \
// -s 728582219 --language=sv
@@ -311,6 +315,7 @@
timeout_cnt_set = 1'b1;
end
end
+ // SEC_CM: ALERT_RX.INTERSIG.BKGN_CHK
// send out an alert ping request and wait for a ping
// response or a ping timeout (whatever comes first).
// if the alert ID is not valid, we drop the request and
@@ -332,6 +337,7 @@
timeout_cnt_set = 1'b1;
end
end
+ // SEC_CM: ESC_TX.INTERSIG.BKGN_CHK
// send out an escalation ping request and wait for a ping
// response or a ping timeout (whatever comes first)
EscPingSt: begin
@@ -345,6 +351,7 @@
end
end
end
+ // SEC_CM: PING_TIMER.FSM.LOCAL_ESC
// terminal FSM error state.
// if we for some reason end up in this state (e.g. malicious glitching)
// we are going to assert both ping fails continuously
@@ -357,6 +364,7 @@
end
endcase
+ // SEC_CM: PING_TIMER.FSM.LOCAL_ESC
// if the two LFSR or counter states do not agree,
// we move into the terminal state.
if (lfsr_err || cnt_error || esc_cnt_error) begin
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
index 720d79f..0470c75 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
@@ -333,16 +333,13 @@
{ name: "PING_TIMER.CONFIG.REGWEN",
desc: "The ping timer configuration registers are REGWEN protected."
}
- {
- name: "ALERT.CONFIG.REGWEN",
+ { name: "ALERT.CONFIG.REGWEN",
desc: "The individual alert enables are REGWEN protected."
}
- {
- name: "ALERT_LOC.CONFIG.REGWEN",
+ { name: "ALERT_LOC.CONFIG.REGWEN",
desc: "The individual local alert enables are REGWEN protected."
}
- {
- name: "CLASS.CONFIG.REGWEN",
+ { name: "CLASS.CONFIG.REGWEN",
desc: "The class configuration registers are REGWEN protected."
}
{ name: "ALERT.INTERSIG.DIFF",
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler.sv
index 5b3ffc5..1f6b4d1 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler.sv
@@ -29,6 +29,7 @@
output logic intr_classc_o,
output logic intr_classd_o,
// Clock gating and reset info from rstmgr and clkmgr
+ // SEC_CM: LPG.INTERSIG.MUBI
input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_cg_en_i,
input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_rst_en_i,
// State information for HW crashdump
@@ -37,9 +38,11 @@
output edn_pkg::edn_req_t edn_o,
input edn_pkg::edn_rsp_t edn_i,
// Alert Sources
+ // SEC_CM: ALERT.INTERSIG.DIFF
input alert_tx_t [NAlerts-1:0] alert_tx_i,
output alert_rx_t [NAlerts-1:0] alert_rx_o,
// Escalation outputs
+ // SEC_CM: ESC.INTERSIG.DIFF
input esc_rx_t [N_ESC_SEV-1:0] esc_rx_i,
output esc_tx_t [N_ESC_SEV-1:0] esc_tx_o
);
@@ -59,6 +62,11 @@
intr_classb_o,
intr_classa_o} = irq;
+ // SEC_CM: CONFIG.SHADOW
+ // SEC_CM: PING_TIMER.CONFIG.REGWEN
+ // SEC_CM: ALERT.CONFIG.REGWEN
+ // SEC_CM: ALERT_LOC.CONFIG.REGWEN
+ // SEC_CM: CLASS.CONFIG.REGWEN
alert_handler_reg_wrap u_reg_wrap (
.clk_i,
.rst_ni,
@@ -70,9 +78,11 @@
.crashdump_o,
.hw2reg_wrap,
.reg2hw_wrap,
+ // SEC_CM: BUS.INTEGRITY
.fatal_integ_alert_o(loc_alert_trig[4])
);
+ // SEC_CM: CONFIG.SHADOW
assign loc_alert_trig[5] = reg2hw_wrap.shadowed_err_update;
assign loc_alert_trig[6] = reg2hw_wrap.shadowed_err_storage;
@@ -121,7 +131,9 @@
// set this to the maximum width in the design.
// can be overridden in DV and FPV to shorten the wait periods.
.wait_cyc_mask_i ( {PING_CNT_DW{1'b1}} ),
+ // SEC_CM: ALERT_RX.INTERSIG.BKGN_CHK
.alert_ping_req_o ( alert_ping_req ),
+ // SEC_CM: ESC_TX.INTERSIG.BKGN_CHK
.esc_ping_req_o ( esc_ping_req ),
.alert_ping_ok_i ( alert_ping_ok ),
.esc_ping_ok_i ( esc_ping_ok ),
@@ -137,6 +149,7 @@
alert_handler_lpg_ctrl u_alert_handler_lpg_ctrl (
.clk_i,
.rst_ni,
+ // SEC_CM: LPG.INTERSIG.MUBI
.lpg_cg_en_i,
.lpg_rst_en_i,
.alert_init_trig_o ( alert_init_trig )
@@ -161,6 +174,7 @@
.ping_ok_o ( alert_ping_ok[k] ),
.integ_fail_o ( alert_integfail[k] ),
.alert_o ( alert_trig[k] ),
+ // SEC_CM: ALERT.INTERSIG.DIFF
.alert_rx_o ( alert_rx_o[k] ),
.alert_tx_i ( alert_tx_i[k] )
);
@@ -241,7 +255,11 @@
end
assign esc_sig_req[k] = |esc_sig_req_trsp[k];
-
+ // SEC_CM: ESC_RX.INTERSIG.BKGN_CHK
+ // Note: This countermeasure is actually implemented on the receiver side. We currently cannot
+ // put this RTL label inside that module due to the way our countermeasure annotation check
+ // script discovers the RTL files. The label is thus put here. Please refer to
+ // prim_esc_receiver.sv for the actual implementation of this mechanism.
prim_esc_sender u_esc_sender (
.clk_i,
.rst_ni,
@@ -249,6 +267,7 @@
.ping_ok_o ( esc_ping_ok[k] ),
.integ_fail_o ( esc_integfail[k] ),
.esc_req_i ( esc_sig_req[k] ),
+ // SEC_CM: ESC.INTERSIG.DIFF
.esc_rx_i ( esc_rx_i[k] ),
.esc_tx_o ( esc_tx_o[k] )
);
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_accu.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_accu.sv
index f8d5bd7..c7b7dec 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_accu.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_accu.sv
@@ -28,6 +28,7 @@
assign trig_gated = class_trig_i & class_en_i;
assign accu_en = trig_gated && !(&accu_cnt_o);
+ // SEC_CM: ACCU.CTR.REDUN
// We employ two redundant counters to guard against FI attacks.
// If any of the two is glitched and the two counter states do not agree,
// the check_fail_o signal is asserted which will move the corresponding escalation
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv
index e5d2f2e..e12bb77 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv
@@ -52,6 +52,7 @@
// are permanently asserted.
logic cnt_en, cnt_clr, cnt_error;
+ // SEC_CM: ESC_TIMER.CTR.REDUN
prim_count #(
.Width(EscCntDw),
.OutSelDnCnt(0), // count up
@@ -83,6 +84,7 @@
logic [N_PHASES-1:0] phase_oh;
+ // SEC_CM: ESC_TIMER.FSM.SPARSE
// Encoding generated with:
// $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
// -s 784905746 --language=sv
@@ -260,6 +262,7 @@
esc_state_o = FsmError;
fsm_error = 1'b1;
end
+ // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
// catch glitches.
default: begin
state_d = FsmErrorSt;
@@ -267,6 +270,7 @@
end
endcase
+ // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
// if any of the duplicate counter pairs has an inconsistent state
// we move into the terminal FSM error state.
if (accu_fail_i || cnt_error) begin
@@ -279,6 +283,7 @@
// generate configuration mask for escalation enable signals
assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
// mask reduce current phase state vector
+ // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
end
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv
index 346c2ad..3734413 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv
@@ -88,6 +88,7 @@
logic [PING_CNT_DW + IdDw - 1:0] lfsr_state;
assign entropy = (reseed_en) ? edn_data_i[LfsrWidth-1:0] : '0;
+ // SEC_CM: PING_TIMER.LFSR.REDUN
// We employ two redundant LFSRs to guard against FI attacks.
// If any of the two is glitched and the two LFSR states do not agree,
// the FSM below is moved into a terminal error state and all ping alerts
@@ -164,6 +165,7 @@
logic [PING_CNT_DW-1:0] esc_cnt;
assign esc_cnt_clr = (esc_cnt >= PING_CNT_DW'(N_ESC_SEV-1)) && esc_cnt_en;
+ // SEC_CM: PING_TIMER.CTR.REDUN
prim_count #(
.Width(PING_CNT_DW),
.OutSelDnCnt(0), // count up
@@ -196,6 +198,7 @@
assign timer_expired = (cnt == '0);
assign cnt_set = wait_cnt_set || timeout_cnt_set;
+ // SEC_CM: PING_TIMER.CTR.REDUN
prim_count #(
.Width(PING_CNT_DW),
.OutSelDnCnt(1), // count down
@@ -248,6 +251,7 @@
.out_o(spurious_esc_ping)
);
+ // SEC_CM: PING_TIMER.FSM.SPARSE
// Encoding generated with:
// $ ./util/design/sparse-fsm-encode.py -d 5 -m 6 -n 9 \
// -s 728582219 --language=sv
@@ -311,6 +315,7 @@
timeout_cnt_set = 1'b1;
end
end
+ // SEC_CM: ALERT_RX.INTERSIG.BKGN_CHK
// send out an alert ping request and wait for a ping
// response or a ping timeout (whatever comes first).
// if the alert ID is not valid, we drop the request and
@@ -332,6 +337,7 @@
timeout_cnt_set = 1'b1;
end
end
+ // SEC_CM: ESC_TX.INTERSIG.BKGN_CHK
// send out an escalation ping request and wait for a ping
// response or a ping timeout (whatever comes first)
EscPingSt: begin
@@ -345,6 +351,7 @@
end
end
end
+ // SEC_CM: PING_TIMER.FSM.LOCAL_ESC
// terminal FSM error state.
// if we for some reason end up in this state (e.g. malicious glitching)
// we are going to assert both ping fails continuously
@@ -357,6 +364,7 @@
end
endcase
+ // SEC_CM: PING_TIMER.FSM.LOCAL_ESC
// if the two LFSR or counter states do not agree,
// we move into the terminal state.
if (lfsr_err || cnt_error || esc_cnt_error) begin
