[alert-handler/doc] Move into D2
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/ip_templates/alert_handler/data/alert_handler.prj.hjson b/hw/ip_templates/alert_handler/data/alert_handler.prj.hjson
index 80e59fd..c707017 100644
--- a/hw/ip_templates/alert_handler/data/alert_handler.prj.hjson
+++ b/hw/ip_templates/alert_handler/data/alert_handler.prj.hjson
@@ -8,9 +8,9 @@
dv_doc: "../doc/dv",
hw_checklist: "../doc/checklist",
sw_checklist: "/sw/device/lib/dif/dif_alert_handler"
- version: "0.5",
+ version: "1.0",
life_stage: "L1",
- design_stage: "D1",
+ design_stage: "D2",
verification_stage: "V1",
dif_stage: "S0",
notes: "Use both FPV and DV to perform block level verification.",
diff --git a/hw/ip_templates/alert_handler/doc/checklist.md b/hw/ip_templates/alert_handler/doc/checklist.md
index 512c7ad..316626b 100644
--- a/hw/ip_templates/alert_handler/doc/checklist.md
+++ b/hw/ip_templates/alert_handler/doc/checklist.md
@@ -35,23 +35,23 @@
Type | Item | Resolution | Note/Collaterals
--------------|-------------------------|-------------|------------------
-Documentation | [NEW_FEATURES][] | Not Started |
+Documentation | [NEW_FEATURES][] | Done |
Documentation | [BLOCK_DIAGRAM][] | Done |
Documentation | [DOC_INTERFACE][] | Done |
-Documentation | [MISSING_FUNC][] | Not Started |
-Documentation | [FEATURE_FROZEN][] | Not Started |
-RTL | [FEATURE_COMPLETE][] | Not Started |
-RTL | [AREA_CHECK][] | Not Started |
-RTL | [PORT_FROZEN][] | Not Started |
-RTL | [ARCHITECTURE_FROZEN][] | Not Started |
-RTL | [REVIEW_TODO][] | Not Started |
-RTL | [STYLE_X][] | Not Started |
+Documentation | [MISSING_FUNC][] | Done |
+Documentation | [FEATURE_FROZEN][] | Done |
+RTL | [FEATURE_COMPLETE][] | Done |
+RTL | [AREA_CHECK][] | Done |
+RTL | [PORT_FROZEN][] | Done |
+RTL | [ARCHITECTURE_FROZEN][] | Done |
+RTL | [REVIEW_TODO][] | Done |
+RTL | [STYLE_X][] | Done |
Code Quality | [LINT_PASS][] | Done |
-Code Quality | [CDC_SETUP][] | Done |
-Code Quality | [FPGA_TIMING][] | Not Started |
+Code Quality | [CDC_SETUP][] | Waived | CDC flow is not available yet.
+Code Quality | [FPGA_TIMING][] | Done |
Code Quality | [CDC_SYNCMACRO][] | Done |
-Security | [SEC_CM_DOCUMENTED][] | Not Started |
-Security | [SEC_RND_CNST][] | Not Started |
+Security | [SEC_CM_DOCUMENTED][] | Done |
+Security | [SEC_RND_CNST][] | Done |
[NEW_FEATURES]: {{<relref "/doc/project/checklist.md#new_features" >}}
[BLOCK_DIAGRAM]: {{<relref "/doc/project/checklist.md#block_diagram" >}}
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.prj.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.prj.hjson
index 80e59fd..c707017 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.prj.hjson
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.prj.hjson
@@ -8,9 +8,9 @@
dv_doc: "../doc/dv",
hw_checklist: "../doc/checklist",
sw_checklist: "/sw/device/lib/dif/dif_alert_handler"
- version: "0.5",
+ version: "1.0",
life_stage: "L1",
- design_stage: "D1",
+ design_stage: "D2",
verification_stage: "V1",
dif_stage: "S0",
notes: "Use both FPV and DV to perform block level verification.",
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/doc/checklist.md b/hw/top_earlgrey/ip_autogen/alert_handler/doc/checklist.md
index 512c7ad..316626b 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/doc/checklist.md
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/doc/checklist.md
@@ -35,23 +35,23 @@
Type | Item | Resolution | Note/Collaterals
--------------|-------------------------|-------------|------------------
-Documentation | [NEW_FEATURES][] | Not Started |
+Documentation | [NEW_FEATURES][] | Done |
Documentation | [BLOCK_DIAGRAM][] | Done |
Documentation | [DOC_INTERFACE][] | Done |
-Documentation | [MISSING_FUNC][] | Not Started |
-Documentation | [FEATURE_FROZEN][] | Not Started |
-RTL | [FEATURE_COMPLETE][] | Not Started |
-RTL | [AREA_CHECK][] | Not Started |
-RTL | [PORT_FROZEN][] | Not Started |
-RTL | [ARCHITECTURE_FROZEN][] | Not Started |
-RTL | [REVIEW_TODO][] | Not Started |
-RTL | [STYLE_X][] | Not Started |
+Documentation | [MISSING_FUNC][] | Done |
+Documentation | [FEATURE_FROZEN][] | Done |
+RTL | [FEATURE_COMPLETE][] | Done |
+RTL | [AREA_CHECK][] | Done |
+RTL | [PORT_FROZEN][] | Done |
+RTL | [ARCHITECTURE_FROZEN][] | Done |
+RTL | [REVIEW_TODO][] | Done |
+RTL | [STYLE_X][] | Done |
Code Quality | [LINT_PASS][] | Done |
-Code Quality | [CDC_SETUP][] | Done |
-Code Quality | [FPGA_TIMING][] | Not Started |
+Code Quality | [CDC_SETUP][] | Waived | CDC flow is not available yet.
+Code Quality | [FPGA_TIMING][] | Done |
Code Quality | [CDC_SYNCMACRO][] | Done |
-Security | [SEC_CM_DOCUMENTED][] | Not Started |
-Security | [SEC_RND_CNST][] | Not Started |
+Security | [SEC_CM_DOCUMENTED][] | Done |
+Security | [SEC_RND_CNST][] | Done |
[NEW_FEATURES]: {{<relref "/doc/project/checklist.md#new_features" >}}
[BLOCK_DIAGRAM]: {{<relref "/doc/project/checklist.md#block_diagram" >}}
