| commit | 31b925a58e6183db4ca11537d2ff3e7021c5ca80 | [log] [tgz] |
|---|---|---|
| author | Weicai Yang <weicai@google.com> | Tue Jun 08 17:43:18 2021 -0700 |
| committer | weicaiyang <49293026+weicaiyang@users.noreply.github.com> | Wed Jun 16 21:03:48 2021 -0700 |
| tree | 14c4e1849eb7d8630959b059ae57130a234c54cf | |
| parent | cb201339e2d8533f16d23e25068deb0e2fd9cfff [diff] |
[dv] Update tl_intg for chip-level 1. address Sri's comments at #6852 2. Move cpu_stub point prior to the place where design generates ecc values, so that the ecc gen and ecc check are in the design data path 3. add knob `en_tl_intg_gen` to decide if TB need to generate ecc or not. For block level, set to 1, for chip, set to 0 Signed-off-by: Weicai Yang <weicai@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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