[dv/doc] Update dv resource note
this PR removes four blocks' comments about pending DV resource.
Signed-off-by: Cindy Chen <chencindy@opentitan.org>
diff --git a/hw/ip/adc_ctrl/data/adc_ctrl.prj.hjson b/hw/ip/adc_ctrl/data/adc_ctrl.prj.hjson
index 77eadf5..5154211 100644
--- a/hw/ip/adc_ctrl/data/adc_ctrl.prj.hjson
+++ b/hw/ip/adc_ctrl/data/adc_ctrl.prj.hjson
@@ -13,5 +13,4 @@
design_stage: "D2S",
verification_stage: "V1",
dif_stage: "S0",
- notes: "DV resource allocation pending.",
}
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.prj.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.prj.hjson
index 598b356..889b9de 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.prj.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.prj.hjson
@@ -27,7 +27,6 @@
design_stage: "D2",
verification_stage: "V1",
dif_stage: "S0",
- notes: "DV resource allocation pending.",
},
]
}
diff --git a/hw/ip/gpio/data/gpio.prj.hjson b/hw/ip/gpio/data/gpio.prj.hjson
index 8ad7dea..79251b8 100644
--- a/hw/ip/gpio/data/gpio.prj.hjson
+++ b/hw/ip/gpio/data/gpio.prj.hjson
@@ -23,7 +23,6 @@
design_stage: "D2S",
verification_stage: "V2",
dif_stage: "S2",
- notes: "Rolled back to D2 as the register module is updated",
}
]
}
diff --git a/hw/ip/rv_timer/data/rv_timer.prj.hjson b/hw/ip/rv_timer/data/rv_timer.prj.hjson
index 9264474..3872363 100644
--- a/hw/ip/rv_timer/data/rv_timer.prj.hjson
+++ b/hw/ip/rv_timer/data/rv_timer.prj.hjson
@@ -23,7 +23,6 @@
design_stage: "D2S",
verification_stage: "V2",
dif_stage: "S2",
- notes: "Rolled back to D2 as the register module is updated",
}
]
}
diff --git a/hw/ip/sysrst_ctrl/data/sysrst_ctrl.prj.hjson b/hw/ip/sysrst_ctrl/data/sysrst_ctrl.prj.hjson
index 4f6deeb..2a31a56 100644
--- a/hw/ip/sysrst_ctrl/data/sysrst_ctrl.prj.hjson
+++ b/hw/ip/sysrst_ctrl/data/sysrst_ctrl.prj.hjson
@@ -13,5 +13,4 @@
design_stage: "D2S",
verification_stage: "V1",
dif_stage: "S0",
- notes: "DV resource allocation pending.",
}
diff --git a/hw/ip/uart/data/uart.prj.hjson b/hw/ip/uart/data/uart.prj.hjson
index 5d14ce3..a50a301 100644
--- a/hw/ip/uart/data/uart.prj.hjson
+++ b/hw/ip/uart/data/uart.prj.hjson
@@ -23,7 +23,6 @@
design_stage: "D2S",
verification_stage: "V2",
dif_stage: "S2",
- notes: "Rolled back to D2 as the register module is updated"
}
]
}
diff --git a/hw/ip/usbdev/data/usbdev.prj.hjson b/hw/ip/usbdev/data/usbdev.prj.hjson
index e7aeb39..b674f22 100644
--- a/hw/ip/usbdev/data/usbdev.prj.hjson
+++ b/hw/ip/usbdev/data/usbdev.prj.hjson
@@ -13,5 +13,4 @@
design_stage: "D2S",
verification_stage: "V0",
dif_stage: "S1",
- notes: "DV resource allocation pending.",
}
