[keymgr/dv] Enable cfgen sequence and scb
Steal some good ideals from Cindy's PR #5005 to improve cfgen
Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/hw/ip/keymgr/dv/env/keymgr_env_pkg.sv b/hw/ip/keymgr/dv/env/keymgr_env_pkg.sv
index 7e3652a..aebba86 100644
--- a/hw/ip/keymgr/dv/env/keymgr_env_pkg.sv
+++ b/hw/ip/keymgr/dv/env/keymgr_env_pkg.sv
@@ -10,6 +10,7 @@
import dv_lib_pkg::*;
import tl_agent_pkg::*;
import cip_base_pkg::*;
+ import dv_base_reg_pkg::*;
import csr_utils_pkg::*;
import keymgr_ral_pkg::*;
import keymgr_kmac_agent_pkg::*;
diff --git a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
index 54de944..9741302 100644
--- a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
+++ b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
@@ -274,6 +274,7 @@
endfunction
virtual task process_tl_access(tl_seq_item item, tl_channels_e channel = DataChannel);
+ dv_base_reg dv_reg;
uvm_reg csr;
bit do_read_check = 1'b1;
bit write = item.is_write();
@@ -288,6 +289,7 @@
if (csr_addr inside {cfg.csr_addrs}) begin
csr = ral.default_map.get_reg_by_offset(csr_addr);
`DV_CHECK_NE_FATAL(csr, null)
+ `downcast(dv_reg, csr)
end
else begin
`uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr))
@@ -297,9 +299,7 @@
if (addr_phase_write) begin
// if OP WIP or keymgr_en=0, will clear cfgen and below csr can't be written
if ((current_op_status == keymgr_pkg::OpWip || cfg.keymgr_vif.keymgr_en != lc_ctrl_pkg::On) &&
- csr.get_name() inside {"control", "key_version",
- "sw_binding_0", "sw_binding_1", "sw_binding_2", "sw_binding_3",
- "salt_0", "salt_1", "salt_2", "salt_3"}) begin
+ ral.cfgen.is_inside_locked_regs(dv_reg)) begin
`uvm_info(`gfn, $sformatf("Reg write to %0s is ignored due to cfgen=0", csr.get_name()),
UVM_MEDIUM)
return;
diff --git a/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfgen_vseq.sv b/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfgen_vseq.sv
index 6a1b76e..ed9b172 100644
--- a/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfgen_vseq.sv
+++ b/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfgen_vseq.sv
@@ -54,27 +54,25 @@
wait_no_outstanding_access();
csr_rd(ral.op_status, op_status_val, .backdoor(1));
if (op_status_val == keymgr_pkg::OpWip && cfg.keymgr_vif.kmac_data_rsp.done) begin
- write_cfgen_gated_reg();
+ write_and_check_regwen_locked_reg();
end
end
endtask
- virtual task write_cfgen_gated_reg();
+ virtual task write_and_check_regwen_locked_reg();
bit [TL_DW-1:0] val = $urandom;
-
- `uvm_info(`gfn, "Write cfgen gated reg, and this write should be ignored", UVM_HIGH)
// since it's timing sensitive, only write one of these reg
- randcase
- 1: csr_wr(ral.control, val);
- 1: csr_wr(ral.key_version, val);
- 1: csr_wr(ral.sw_binding_0, val);
- 1: csr_wr(ral.sw_binding_1, val);
- 1: csr_wr(ral.sw_binding_2, val);
- 1: csr_wr(ral.sw_binding_3, val);
- 1: csr_wr(ral.salt_0, val);
- 1: csr_wr(ral.salt_1, val);
- 1: csr_wr(ral.salt_2, val);
- 1: csr_wr(ral.salt_3, val);
- endcase
- endtask : write_cfgen_gated_reg
+ dv_base_reg locked_reg;
+ dv_base_reg locked_regs[$];
+
+ ral.cfgen.get_locked_regs(locked_regs);
+ locked_regs.shuffle();
+ locked_reg = locked_regs[0];
+
+ `uvm_info(`gfn, $sformatf("Write regwen locked reg %0s, and this write should be ignored",
+ locked_reg.get_name()), UVM_MEDIUM)
+ csr_wr(locked_reg, val);
+ csr_rd(locked_reg, val); // checking is done with scb
+ endtask : write_and_check_regwen_locked_reg
+
endclass : keymgr_cfgen_vseq
