| commit | e60202e75df68bdd497b435e54dd763e3f336aca | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@opentitan.org> | Tue Mar 15 14:34:52 2022 -0700 |
| committer | Eunchan Kim <github@eunchan.kim> | Wed Mar 23 18:36:14 2022 -0700 |
| tree | a276960f9792083d7f42dffa1fa0eff37940d6d4 | |
| parent | 1299fa100c688038ea4cce098d9b49b9bfebb9fb [diff] |
[spi_device] Queue SW req of clr BUSY when active Design Doc: https://docs.google.com/document/d/1wUIynMYVfVg9HmCL0q5-6r9BuN-XM0z--wGqU0bXRQ0 This commit adds a flag register to store the SW request of clearing the BUSY bit in the STATUS register when the HW is not able to accept the request due to the CDC issue. The HW then checks the flag and clears the BUSY bit when the SPI is in idle state. Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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