[dv/otp] OTP V1 status
Update OTP testbench status to V1.
Signed-off-by: Cindy Chen <chencindy@google.com>
diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.prj.hjson b/hw/ip/otp_ctrl/data/otp_ctrl.prj.hjson
index 9bfc19d..64c1ba9 100644
--- a/hw/ip/otp_ctrl/data/otp_ctrl.prj.hjson
+++ b/hw/ip/otp_ctrl/data/otp_ctrl.prj.hjson
@@ -5,12 +5,12 @@
{
name: "otp_ctrl",
design_spec: "hw/ip/otp_ctrl/doc",
- dv_plan: "",
+ dv_plan: "hw/ip/otp_ctrl/doc/dv_plan",
hw_checklist: "hw/ip/otp_ctrl/doc/checklist",
sw_checklist: ""
version: "0.1",
life_stage: "L1",
design_stage: "D1",
- verification_stage: "V0",
+ verification_stage: "V1",
notes: "",
}
diff --git a/hw/ip/otp_ctrl/doc/checklist.md b/hw/ip/otp_ctrl/doc/checklist.md
index 7d99d9d..2fcc5bf 100644
--- a/hw/ip/otp_ctrl/doc/checklist.md
+++ b/hw/ip/otp_ctrl/doc/checklist.md
@@ -113,27 +113,27 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_PLAN_DRAFT_COMPLETED][] | Not Started | [OTP_CTRL DV Plan]({{<relref "hw/ip/otp_ctrl/doc/dv_plan" >}})
-Documentation | [TESTPLAN_COMPLETED][] | Not Started | [OTP_CTRL Testplan]({{<relref "hw/ip/otp_ctrl/doc/dv_plan/index.md#testplan" >}})
-Testbench | [TB_TOP_CREATED][] | Not Started |
-Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
-Testbench | [SIM_TB_ENV_CREATED][] | Not Started |
-Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started |
-Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started |
-Testbench | [TB_GEN_AUTOMATED][] | Not Started |
-Tests | [SIM_SANITY_TEST_PASSING][] | Not Started |
-Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started |
-Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started |
-Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started |
-Regression | [SIM_SANITY_REGRESSION_SETUP][] | Not Started |
-Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started |
-Regression | [FPV_REGRESSION_SETUP][] | Not Started |
-Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started |
-Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started |
-Review | [DESIGN_SPEC_REVIEWED][] | Not Started |
-Review | [DV_PLAN_TESTPLAN_REVIEWED][] | Not Started |
-Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?)
-Review | [V2_CHECKLIST_SCOPED][] | Not Started |
+Documentation | [DV_PLAN_DRAFT_COMPLETED][] | Done | [OTP_CTRL DV Plan]({{<relref "hw/ip/otp_ctrl/doc/dv_plan" >}})
+Documentation | [TESTPLAN_COMPLETED][] | Done | [OTP_CTRL Testplan]({{<relref "hw/ip/otp_ctrl/doc/dv_plan/index.md#testplan" >}})
+Testbench | [TB_TOP_CREATED][] | Done |
+Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
+Testbench | [SIM_TB_ENV_CREATED][] | Done |
+Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done |
+Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done |
+Testbench | [TB_GEN_AUTOMATED][] | Done |
+Tests | [SIM_SANITY_TEST_PASSING][] | Done |
+Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done |
+Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A |
+Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done |
+Regression | [SIM_SANITY_REGRESSION_SETUP][] | Done |
+Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done |
+Regression | [FPV_REGRESSION_SETUP][] | N/A |
+Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done |
+Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A | Exception for IP modules
+Review | [DESIGN_SPEC_REVIEWED][] | Done |
+Review | [DV_PLAN_TESTPLAN_REVIEWED][] | Done |
+Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception (Security, Power, Debug)
+Review | [V2_CHECKLIST_SCOPED][] | Done |
[DV_PLAN_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_plan_draft_completed" >}}
[TESTPLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#testplan_completed" >}}
