[dv common] Minor enhancements to dv_reg_block
- These address few of the suggestions made in #3971.
- It updates some of the dv_base_reg_block methods to be free from reg
map assumptions.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/dv/sv/cip_lib/cip_base_scoreboard.sv b/hw/dv/sv/cip_lib/cip_base_scoreboard.sv
index 8398e38..16bffc3 100644
--- a/hw/dv/sv/cip_lib/cip_base_scoreboard.sv
+++ b/hw/dv/sv/cip_lib/cip_base_scoreboard.sv
@@ -107,12 +107,12 @@
endtask
virtual task process_mem_write(tl_seq_item item);
- uvm_reg_addr_t addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t addr = ral.get_word_aligned_addr(item.a_addr);
if (!cfg.under_reset) exp_mem.write(addr, item.a_data, item.a_mask);
endtask
virtual task process_mem_read(tl_seq_item item);
- uvm_reg_addr_t addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t addr = ral.get_word_aligned_addr(item.a_addr);
if (!cfg.under_reset && get_mem_access_by_addr(ral, addr) == "RW") begin
exp_mem.compare(addr, item.d_data, item.a_mask);
end
@@ -120,7 +120,7 @@
// check if it's mem addr
virtual function bit is_mem_addr(tl_seq_item item);
- uvm_reg_addr_t addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t addr = ral.get_word_aligned_addr(item.a_addr);
foreach (cfg.mem_ranges[i]) begin
if (addr inside {[cfg.mem_ranges[i].start_addr : cfg.mem_ranges[i].end_addr]}) begin
return 1;
@@ -166,7 +166,7 @@
// check if address is mapped
virtual function bit is_tl_access_mapped_addr(tl_seq_item item);
- uvm_reg_addr_t addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t addr = ral.get_word_aligned_addr(item.a_addr);
// check if it's mem addr or reg addr
if (is_mem_addr(item) || addr inside {cfg.csr_addrs}) return 1;
else return 0;
@@ -177,7 +177,7 @@
if (is_mem_addr(item)) begin
bit mem_partial_write_support;
dv_base_mem mem;
- uvm_reg_addr_t addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t addr = ral.get_word_aligned_addr(item.a_addr);
string mem_access = get_mem_access_by_addr(ral, addr);
`downcast(mem, get_mem_by_addr(ral, addr))
@@ -205,7 +205,7 @@
if (!is_tl_access_mapped_addr(item) || is_mem_addr(item)) return 1;
if (item.is_write()) begin
dv_base_reg csr;
- uvm_reg_addr_t addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t addr = ral.get_word_aligned_addr(item.a_addr);
`DV_CHECK_FATAL($cast(csr,
ral.default_map.get_reg_by_offset(addr)))
if (csr.get_msb_pos >= 24 && item.a_mask[3:0] != 'b1111 ||
diff --git a/hw/dv/sv/dv_base_reg/dv_base_reg_block.sv b/hw/dv/sv/dv_base_reg/dv_base_reg_block.sv
index 93230a3..20702b5 100644
--- a/hw/dv/sv/dv_base_reg/dv_base_reg_block.sv
+++ b/hw/dv/sv/dv_base_reg/dv_base_reg_block.sv
@@ -8,14 +8,13 @@
csr_excl_item csr_excl;
- // The address mask for the register block. This will be (1 << K) - 1 for some K. All relative
- // offsets in the register block have addresses less than (1 << K), so an address decoder that
- // starts by discarding all higher bits will work correctly so long as the chosen base address of
- // the register block has no bits in common with this mask.
+ // The address mask for the register block specific to a map. This will be (1 << K) - 1 for some
+ // K. All relative offsets in the register block have addresses less than (1 << K), so an address
+ // decoder that starts by discarding all higher bits will work correctly so long as the chosen
+ // base address of the register block has no bits in common with this mask.
//
- // This is initialized to zero (which means "unset") and then set by compute_mask(), which must
- // run after locking the model.
- protected uvm_reg_addr_t addr_mask = 0;
+ // This is set by compute_addr_mask(), which must run after locking the model.
+ protected uvm_reg_addr_t addr_mask[uvm_reg_map];
function new (string name = "", int has_coverage = UVM_NO_COVERAGE);
super.new(name, has_coverage);
@@ -27,17 +26,6 @@
`uvm_fatal(`gfn, "this method is not supposed to be called directly!")
endfunction
- // Get the address mask. This should only be called after locking the model (because it depends on
- // the layout of registers and memories in the block).
- function uvm_reg_addr_t get_addr_mask();
- `DV_CHECK_FATAL(is_locked())
- if (this.addr_mask == 0) begin
- this.compute_mask();
- `DV_CHECK_FATAL(this.addr_mask != 0)
- end
- return addr_mask;
- endfunction
-
function void get_dv_base_reg_blocks(ref dv_base_reg_block blks[$]);
uvm_reg_block uvm_blks[$];
this.get_blocks(uvm_blks);
@@ -52,7 +40,7 @@
function void get_enable_regs(ref dv_base_reg enable_regs[$]);
dv_base_reg_block blks[$];
- this.get_dv_base_reg_blocks(blks);
+ get_dv_base_reg_blocks(blks);
if (blks.size() == 0) begin
dv_base_reg all_regs[$];
this.get_dv_base_regs(all_regs);
@@ -77,11 +65,10 @@
// Internal function, used to compute the address mask for this register block.
//
- // This is quite an expensive computation, so we memoize the results in addr_mask
- //
- // use below to get the addr map size #3317
+ // This is quite an expensive computation, so we memoize the results in addr_mask[map].
+ // Use below to get the addr map size #3317
// max2(biggest_reg_offset+reg_size, biggest_mem_offset+mem_size) and then round up to 2**N
- protected function void compute_mask();
+ protected function void compute_addr_mask(uvm_reg_map map);
uvm_reg_addr_t max_addr, max_offset;
uvm_reg_block blocks[$];
uvm_reg regs[$];
@@ -90,31 +77,32 @@
// TODO: assume IP only contains 1 reg block, find a better way to handle chip-level and IP
// with multiple reg blocks
- this.get_blocks(blocks);
+ get_blocks(blocks);
if (blocks.size > 0) begin
- this.addr_mask = '1;
+ addr_mask[map] = '1;
return;
end
- this.get_registers(regs);
- this.get_memories(mems);
- `DV_CHECK_GT_FATAL(regs.size + mems.size, 0)
+ get_registers(regs);
+ get_memories(mems);
+ `DV_CHECK_GT_FATAL(regs.size() + mems.size(), 0)
// Walk the known registers and memories, calculating the largest byte address visible. Note
// that the get_offset() calls will return absolute addresses, including any base address in the
// default register map.
max_addr = 0;
foreach (regs[i]) begin
- max_addr = max2(regs[i].get_offset() + regs[i].get_n_bytes() - 1, max_addr);
+ max_addr = max2(regs[i].get_offset(map) + regs[i].get_n_bytes() - 1, max_addr);
end
foreach (mems[i]) begin
- max_addr = max2(mems[i].get_offset() + mems[i].get_size() * mems[i].get_n_bytes() - 1,
- max_addr);
+ uvm_reg_addr_t mem_size;
+ mem_size = mems[i].get_offset(.map(map)) + mems[i].get_size() * mems[i].get_n_bytes() - 1;
+ max_addr = max2(mem_size, max_addr);
end
// Subtract the base address in the default register map to get the maximum relative offset.
- max_offset = max_addr - this.default_map.get_base_addr();
+ max_offset = max_addr - map.get_base_addr();
// Set alignment to be ceil(log2(biggest_offset))
alignment = 0;
@@ -128,17 +116,31 @@
`DV_CHECK_GT_FATAL(alignment, 0)
// Finally, extract a mask corresponding to the alignment
- this.addr_mask = (1 << alignment) - 1;
+ addr_mask[map] = (1 << alignment) - 1;
+ // Computed mask must be non-zero.
+ `DV_CHECK_FATAL(addr_mask[map])
endfunction
- // Pick or check a base address for the given register map
+ // Get the address mask. This should only be called after locking the model (because it depends on
+ // the layout of registers and memories in the block).
+ function uvm_reg_addr_t get_addr_mask(uvm_reg_map map = null);
+ `DV_CHECK_FATAL(is_locked())
+ if (map == null) map = get_default_map();
+ if (!addr_mask.exists(map)) compute_addr_mask(map);
+ return addr_mask[map];
+ endfunction
+
+ // Set the base address for the given register map
//
- // Check that base_addr is aligned as required by the register block and return it again. If
- // base_addr is the "magic" address '1, randomly pick an appropriately aligned base address and
- // return it.
- function uvm_reg_addr_t pick_base_addr(uvm_reg_addr_t base_addr);
- uvm_reg_addr_t mask = this.get_addr_mask();
+ // Check that base_addr is aligned as required by the register block. If the supplied base_addr is
+ // the "magic" address '1, randomly pick an appropriately aligned base address and set it for the
+ // specified map.
+ function void set_base_addr(uvm_reg_addr_t base_addr = '1, uvm_reg_map map = null);
+ uvm_reg_addr_t mask;
+
+ if (map == null) map = get_default_map();
+ mask = get_addr_mask(map);
// If base_addr is '1, randomly pick an aligned base address
if (base_addr == '1) begin
@@ -148,8 +150,8 @@
// Check base addr alignment (which should be guaranteed if we just picked it, but needs
// checking if not).
`DV_CHECK_FATAL((base_addr & mask) == '0)
-
- return base_addr;
+ `uvm_info(`gfn, $sformatf("Setting register base address to 0x%0h", base_addr), UVM_HIGH)
+ map.set_base_addr(base_addr);
endfunction
// Round the given address down to the start of the containing word. For example, if the address
@@ -157,15 +159,19 @@
//
// This is useful if you have a possibly misaligned address and you want to know whether it hits a
// register (since get_reg_by_offset needs the aligned address for the start of the register).
- function uvm_reg_addr_t align_to_word_addr(uvm_reg_addr_t byte_addr);
- return (byte_addr >> 2) << 2;
+ function uvm_reg_addr_t get_word_aligned_addr(uvm_reg_addr_t byte_addr);
+ uvm_reg_addr_t shift = $clog2(`UVM_REG_BYTENABLE_WIDTH);
+ return (byte_addr >> shift) << shift;
endfunction
// Get the absolute address (in the default register map) for the given offset. For example, if
- // the base address is 'h100 and offset is 'h13, this will return 'h113.
- function uvm_reg_addr_t offset_to_addr(uvm_reg_addr_t byte_offset);
- uvm_reg_addr_t word_offset = byte_offset >> 2;
- return (word_offset << 2) + this.default_map.get_base_addr();
+ // the base address is 'h100 and offset is 'h13, this will return 'h113 ('h110 if word_aligned is
+ // set).
+ function uvm_reg_addr_t get_addr_from_offset(uvm_reg_addr_t byte_offset,
+ bit word_aligned = 1'b1,
+ uvm_reg_map map = null);
+ if (map == null) map = get_default_map();
+ return (word_aligned ? get_word_aligned_addr(byte_offset) : byte_offset) + map.get_base_addr();
endfunction
endclass
diff --git a/hw/dv/sv/dv_lib/dv_base_env_cfg.sv b/hw/dv/sv/dv_lib/dv_base_env_cfg.sv
index 851776a..233937e 100644
--- a/hw/dv/sv/dv_lib/dv_base_env_cfg.sv
+++ b/hw/dv/sv/dv_lib/dv_base_env_cfg.sv
@@ -53,12 +53,10 @@
apply_ral_fixes();
ral.lock_model();
- // Now the model is locked, we know its layout. Ask the register block to sanity-check
- // csr_base_addr (if it's not '1) or pick a sensible one otherwise. Then install that base
- // address in the default map.
- base_addr = ral.pick_base_addr(csr_base_addr);
- `uvm_info(`gfn, $sformatf("Setting register base address to 0x%0h", base_addr), UVM_HIGH)
- ral.default_map.set_base_addr(base_addr);
+ // Now the model is locked, we know its layout. Set the base address for the register block.
+ // The function internally picks a random one if we pass '1 to it, and performs an integrity
+ // check on the set address.
+ ral.set_base_addr(csr_base_addr);
// Get list of valid csr addresses (useful in seq to randomize addr as well as in scb checks)
get_csr_addrs(ral, csr_addrs);
diff --git a/hw/ip/aes/dv/env/aes_scoreboard.sv b/hw/ip/aes/dv/env/aes_scoreboard.sv
index d897332..3efd7fd 100644
--- a/hw/ip/aes/dv/env/aes_scoreboard.sv
+++ b/hw/ip/aes/dv/env/aes_scoreboard.sv
@@ -69,7 +69,7 @@
aes_seq_item complete_clone;
bit do_read_check = 1'b0;
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
// if access was to a valid csr, get the csr handle
if (csr_addr inside {cfg.csr_addrs}) begin
diff --git a/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv b/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
index eb5bf75..24f78e8 100644
--- a/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
+++ b/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
@@ -36,7 +36,7 @@
// TODO Turned off do_read_check for polling, add prediction
bit do_read_check = 1'b1;
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
// if access was to a valid csr, get the csr handle
if (csr_addr inside {cfg.csr_addrs}) begin
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv
index fafeea1..ebcc55a 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv
@@ -60,7 +60,7 @@
uvm_reg csr;
bit do_read_check = 1'b1;
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
bit addr_phase_read = (!write && channel == AddrChannel);
bit addr_phase_write = (write && channel == AddrChannel);
diff --git a/hw/ip/gpio/dv/env/gpio_scoreboard.sv b/hw/ip/gpio/dv/env/gpio_scoreboard.sv
index 0b02e20..d1417cd 100644
--- a/hw/ip/gpio/dv/env/gpio_scoreboard.sv
+++ b/hw/ip/gpio/dv/env/gpio_scoreboard.sv
@@ -60,7 +60,7 @@
uvm_reg csr;
bit do_read_check = 1'b1;
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
// if access was to a valid csr, get the csr handle
if (csr_addr inside {cfg.csr_addrs}) begin
diff --git a/hw/ip/hmac/dv/env/hmac_env.sv b/hw/ip/hmac/dv/env/hmac_env.sv
index 35490dc..e6ff21c 100644
--- a/hw/ip/hmac/dv/env/hmac_env.sv
+++ b/hw/ip/hmac/dv/env/hmac_env.sv
@@ -17,7 +17,7 @@
dv_base_mem mem;
super.end_of_elaboration_phase(phase);
// hmac mem supports partial write, set it after ral model is locked
- `downcast(mem, get_mem_by_addr(cfg.ral, cfg.ral.offset_to_addr(HMAC_MSG_FIFO_BASE)))
+ `downcast(mem, get_mem_by_addr(cfg.ral, cfg.ral.get_addr_from_offset(HMAC_MSG_FIFO_BASE)))
mem.set_mem_partial_write_support(1);
endfunction
diff --git a/hw/ip/hmac/dv/env/hmac_scoreboard.sv b/hw/ip/hmac/dv/env/hmac_scoreboard.sv
index d55fc76..822a141 100644
--- a/hw/ip/hmac/dv/env/hmac_scoreboard.sv
+++ b/hw/ip/hmac/dv/env/hmac_scoreboard.sv
@@ -35,7 +35,7 @@
bit write = item.is_write();
string csr_name;
bit [TL_AW-1:0] addr_mask = ral.get_addr_mask();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
// if access was to a valid csr, get the csr handle
if (csr_addr inside {cfg.csr_addrs}) begin
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
index 8ad99f2..8650691 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
@@ -171,7 +171,7 @@
word = {>>byte{word_unpack}};
`uvm_info(`gfn, $sformatf("wr_addr = %0h, wr_mask = %0h, words = 0x%0h",
wr_addr, wr_mask, word), UVM_HIGH)
- tl_access(.addr(cfg.ral.offset_to_addr(wr_addr)),
+ tl_access(.addr(cfg.ral.get_addr_from_offset(wr_addr)),
.write(1'b1), .data(word), .mask(wr_mask), .blocking(non_blocking));
if (ral.cfg.sha_en.get_mirrored_value()) begin
@@ -207,7 +207,7 @@
`uvm_info(`gfn, $sformatf("wr_addr = %0h, wr_mask = %0h, words = 0x%0h",
wr_addr, wr_mask, word), UVM_HIGH)
`DV_CHECK_FATAL(randomize(wr_addr, wr_mask) with {wr_mask == '1;})
- tl_access(.addr(cfg.ral.offset_to_addr(wr_addr)),
+ tl_access(.addr(cfg.ral.get_addr_from_offset(wr_addr)),
.write(1'b1), .data(word), .mask(wr_mask), .blocking($urandom_range(0, 1)));
end
if (ral.cfg.sha_en.get_mirrored_value()) begin
diff --git a/hw/ip/i2c/dv/env/i2c_scoreboard.sv b/hw/ip/i2c/dv/env/i2c_scoreboard.sv
index 69300bf..d5f27d8 100644
--- a/hw/ip/i2c/dv/env/i2c_scoreboard.sv
+++ b/hw/ip/i2c/dv/env/i2c_scoreboard.sv
@@ -61,7 +61,7 @@
bit do_read_check = 1'b0; // TODO: Enable this bit later
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
// if access was to a valid csr, get the csr handle
if (csr_addr inside {cfg.csr_addrs}) begin
csr = ral.default_map.get_reg_by_offset(csr_addr);
diff --git a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
index ea4aaf5..5a80b0e 100644
--- a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
+++ b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
@@ -35,7 +35,7 @@
uvm_reg csr;
bit do_read_check = 1'b1;
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
bit addr_phase_read = (!write && channel == AddrChannel);
bit addr_phase_write = (write && channel == AddrChannel);
diff --git a/hw/ip/kmac/dv/env/kmac_scoreboard.sv b/hw/ip/kmac/dv/env/kmac_scoreboard.sv
index f581e6f..89b48bb 100644
--- a/hw/ip/kmac/dv/env/kmac_scoreboard.sv
+++ b/hw/ip/kmac/dv/env/kmac_scoreboard.sv
@@ -35,7 +35,7 @@
uvm_reg csr;
bit do_read_check = 1'b1;
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
bit addr_phase_read = (!write && channel == AddrChannel);
bit addr_phase_write = (write && channel == AddrChannel);
diff --git a/hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv b/hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv
index a4635a0..dc74dac 100644
--- a/hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv
+++ b/hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv
@@ -63,7 +63,7 @@
// the DUT internals. Of course, we need to check this is true exactly when we expect it to be.
// Here, we set a flag to say that we expect the "start" signal to be high. See the
// check_start() task, which checks it's true at the right time.
- csr_addr = ral.align_to_word_addr(item.a_addr);
+ csr_addr = ral.get_word_aligned_addr(item.a_addr);
csr = ral.default_map.get_reg_by_offset(csr_addr);
// csr might be null and that's ok (it's probably a write to memory).
diff --git a/hw/ip/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv b/hw/ip/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv
index f2ae0aa..0eb9675 100644
--- a/hw/ip/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv
+++ b/hw/ip/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv
@@ -47,7 +47,7 @@
uvm_reg csr;
bit do_read_check = 1'b0;
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
bit [TL_AW-1:0] addr_mask = ral.get_addr_mask();
bit addr_phase_read = (!write && channel == AddrChannel);
diff --git a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_sanity_vseq.sv b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_sanity_vseq.sv
index 99da49c..4fe7691 100644
--- a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_sanity_vseq.sv
+++ b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_sanity_vseq.sv
@@ -87,7 +87,7 @@
// if write sw partitions, check tlul window
if (part_idx inside {CreatorSwCfgIdx, OwnerSwCfgIdx}) begin
- uvm_reg_addr_t tlul_addr = cfg.ral.offset_to_addr(get_sw_window_offset(dai_addr));
+ uvm_reg_addr_t tlul_addr = cfg.ral.get_addr_from_offset(get_sw_window_offset(dai_addr));
// random issue reset, OTP content should not be cleared
if ($urandom_range(0, 1)) dut_init();
diff --git a/hw/ip/pattgen/dv/env/pattgen_scoreboard.sv b/hw/ip/pattgen/dv/env/pattgen_scoreboard.sv
index 7ecaf7e..311daa1 100644
--- a/hw/ip/pattgen/dv/env/pattgen_scoreboard.sv
+++ b/hw/ip/pattgen/dv/env/pattgen_scoreboard.sv
@@ -48,7 +48,7 @@
bit do_read_check = 1'b0; // TODO: temporaly disable
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
// if access was to a valid csr, get the csr handle
if (csr_addr inside {cfg.csr_addrs}) begin
csr = ral.default_map.get_reg_by_offset(csr_addr);
diff --git a/hw/ip/rv_timer/dv/env/rv_timer_scoreboard.sv b/hw/ip/rv_timer/dv/env/rv_timer_scoreboard.sv
index 681dad1..f36320f 100644
--- a/hw/ip/rv_timer/dv/env/rv_timer_scoreboard.sv
+++ b/hw/ip/rv_timer/dv/env/rv_timer_scoreboard.sv
@@ -39,7 +39,7 @@
string csr_name;
bit do_read_check = 1'b1;
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
// if access was to a valid csr, get the csr handle
if (csr_addr inside {cfg.csr_addrs}) begin
diff --git a/hw/ip/spi_device/dv/env/spi_device_env_cfg.sv b/hw/ip/spi_device/dv/env/spi_device_env_cfg.sv
index 03e2a2b..1e508cb 100644
--- a/hw/ip/spi_device/dv/env/spi_device_env_cfg.sv
+++ b/hw/ip/spi_device/dv/env/spi_device_env_cfg.sv
@@ -20,7 +20,7 @@
// set num_interrupts & num_alerts which will be used to create coverage and more
num_interrupts = ral.intr_state.get_n_used_bits();
- sram_start_addr = ral.offset_to_addr(SRAM_OFFSET);
+ sram_start_addr = ral.get_addr_from_offset(SRAM_OFFSET);
sram_end_addr = sram_start_addr + SRAM_SIZE - 1;
endfunction
diff --git a/hw/ip/spi_device/dv/env/spi_device_scoreboard.sv b/hw/ip/spi_device/dv/env/spi_device_scoreboard.sv
index d0e2930..226f6e1 100644
--- a/hw/ip/spi_device/dv/env/spi_device_scoreboard.sv
+++ b/hw/ip/spi_device/dv/env/spi_device_scoreboard.sv
@@ -68,7 +68,7 @@
uvm_reg csr;
bit do_read_check = 1'b0; // TODO: fixme
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
// if access was to a valid csr, get the csr handle
if (csr_addr inside {cfg.csr_addrs}) begin
diff --git a/hw/ip/uart/dv/env/uart_scoreboard.sv b/hw/ip/uart/dv/env/uart_scoreboard.sv
index ae071b3..5cf8eed 100644
--- a/hw/ip/uart/dv/env/uart_scoreboard.sv
+++ b/hw/ip/uart/dv/env/uart_scoreboard.sv
@@ -163,7 +163,7 @@
uvm_reg csr;
bit do_read_check = 1'b1;
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
// if access was to a valid csr, get the csr handle
if (csr_addr inside {cfg.csr_addrs}) begin
diff --git a/hw/ip/usbdev/dv/env/usbdev_scoreboard.sv b/hw/ip/usbdev/dv/env/usbdev_scoreboard.sv
index 85eb877..346b0ee 100644
--- a/hw/ip/usbdev/dv/env/usbdev_scoreboard.sv
+++ b/hw/ip/usbdev/dv/env/usbdev_scoreboard.sv
@@ -51,7 +51,7 @@
uvm_reg csr;
bit do_read_check = 1'b1;
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
// if access was to a valid csr, get the csr handle
if (csr_addr inside {cfg.csr_addrs}) begin
diff --git a/util/uvmdvgen/scoreboard.sv.tpl b/util/uvmdvgen/scoreboard.sv.tpl
index 13098b0..f3cdf5c 100644
--- a/util/uvmdvgen/scoreboard.sv.tpl
+++ b/util/uvmdvgen/scoreboard.sv.tpl
@@ -64,7 +64,7 @@
uvm_reg csr;
bit do_read_check = 1'b1;
bit write = item.is_write();
- uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
bit addr_phase_read = (!write && channel == AddrChannel);
bit addr_phase_write = (write && channel == AddrChannel);
