commit e36d3d88b3c9fce7205273dddc6e3b1ac6971157
author Alphan Ulusoy <alphan@google.com> Wed Aug 17 12:57:53 2022 -0400
committer Alphan Ulusoy <alphan@google.com> Thu Aug 18 10:44:42 2022 -0400
tree 6d2f020b897dbefee802f029704567ccbaccd25c
parent 3c169948777c1c53b3e0f0203a6083dfe9fbaa85

[sw/silicon_creator] Use generated defines for the MMIO region

Fixes #7117

Signed-off-by: Alphan Ulusoy <alphan@google.com>

sw/device/silicon_creator/rom/rom_epmp.c

diff --git a/sw/device/silicon_creator/rom/rom_epmp.c b/sw/device/silicon_creator/rom/rom_epmp.c
index 2f53232..2299988 100644
--- a/sw/device/silicon_creator/rom/rom_epmp.c
+++ b/sw/device/silicon_creator/rom/rom_epmp.c
@@ -14,6 +14,21 @@
 extern char _text_start[];   // Start of executable code.
 extern char _text_end[];     // End of executable code.
 
+// Note: Hardcoding these values since the way we generate this range is not
+// very robust at the moment. See #14345 and #14336.
+static_assert(TOP_EARLGREY_MMIO_BASE_ADDR == 0x40000000,
+              "MMIO region changed, update ePMP configuration if needed");
+static_assert(TOP_EARLGREY_MMIO_SIZE_BYTES == 0x10000000,
+              "MMIO region changed, update ePMP configuration if needed");
+
+static_assert(TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR >=
+                      TOP_EARLGREY_MMIO_BASE_ADDR &&
+                  TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR +
+                          TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES <
+                      TOP_EARLGREY_MMIO_BASE_ADDR +
+                          TOP_EARLGREY_MMIO_SIZE_BYTES,
+              "Retention SRAM must be in the MMIO address space.");
+
 void rom_epmp_state_init(epmp_state_t *state, lifecycle_state_t lc_state) {
   // Address space definitions.
   //
@@ -27,8 +42,9 @@
   const epmp_region_t eflash = {
       .start = TOP_EARLGREY_EFLASH_BASE_ADDR,
       .end = TOP_EARLGREY_EFLASH_BASE_ADDR + TOP_EARLGREY_EFLASH_SIZE_BYTES};
-  // TODO(#7117): generate MMIO addresses.
-  const epmp_region_t mmio = {.start = 0x40000000, .end = 0x50000000};
+  const epmp_region_t mmio = {
+      .start = TOP_EARLGREY_MMIO_BASE_ADDR,
+      .end = TOP_EARLGREY_MMIO_BASE_ADDR + TOP_EARLGREY_MMIO_SIZE_BYTES};
   const epmp_region_t debug_rom = {.start = TOP_EARLGREY_RV_DM_ROM_BASE_ADDR,
                                    .end = TOP_EARLGREY_RV_DM_ROM_BASE_ADDR +
                                           TOP_EARLGREY_RV_DM_ROM_SIZE_BYTES};

sw/device/silicon_creator/rom/rom_epmp_init.S

diff --git a/sw/device/silicon_creator/rom/rom_epmp_init.S b/sw/device/silicon_creator/rom/rom_epmp_init.S
index bad9489..3657c56 100644
--- a/sw/device/silicon_creator/rom/rom_epmp_init.S
+++ b/sw/device/silicon_creator/rom/rom_epmp_init.S
@@ -74,9 +74,9 @@
   csrw pmpaddr5, t0
 
   // MMIO
-  li   t0, TOR(0x40000000) // TODO(#7117): generate MMIO start address.
+  li   t0, TOR(TOP_EARLGREY_MMIO_BASE_ADDR)
   csrw pmpaddr10, t0
-  li   t0, TOR(0x50000000) // TODO(#7117): generate MMIO end address.
+  li   t0, TOR(TOP_EARLGREY_MMIO_BASE_ADDR + TOP_EARLGREY_MMIO_SIZE_BYTES)
   csrw pmpaddr11, t0
 
   // Debug ROM