[chip/dv] Generate TLUL data intg for top-level CSR tests
Addressed #7966
In chip level stub_cpu mode, TB needs to generate data intg as data intg
is generated in Ibex and we bypass the Ibex to drive the TL interface.
For cmd intg, we force it to random value as it can be generated in the
design data path.
Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/hw/dv/sv/cip_lib/cip_base_env.sv b/hw/dv/sv/cip_lib/cip_base_env.sv
index 6d75161..0330b18 100644
--- a/hw/dv/sv/cip_lib/cip_base_env.sv
+++ b/hw/dv/sv/cip_lib/cip_base_env.sv
@@ -22,7 +22,7 @@
// use cip_tl_seq_item to create tl_seq_item with correct integrity values and obtain integrity
// related functions
- if (cfg.en_tl_intg_gen) tl_seq_item::type_id::set_type_override(cip_tl_seq_item::get_type());
+ tl_seq_item::type_id::set_type_override(cip_tl_seq_item::get_type());
// Retrieve the virtual interfaces from uvm_config_db.
if (!uvm_config_db#(intr_vif)::get(this, "", "intr_vif", cfg.intr_vif) &&
diff --git a/hw/dv/sv/cip_lib/cip_base_env_cfg.sv b/hw/dv/sv/cip_lib/cip_base_env_cfg.sv
index 34a0c8b..a8a3744 100644
--- a/hw/dv/sv/cip_lib/cip_base_env_cfg.sv
+++ b/hw/dv/sv/cip_lib/cip_base_env_cfg.sv
@@ -25,10 +25,6 @@
uvm_reg_data_t shadow_update_err_status_fields[dv_base_reg_field];
uvm_reg_data_t shadow_storage_err_status_fields[dv_base_reg_field];
- // Enables TL integrity generation & checking with *_user bits.
- // Assume ALL TL agents have integrity check enabled or disabled altogether.
- bit en_tl_intg_gen = 1;
-
alert_esc_agent_cfg m_alert_agent_cfg[string];
push_pull_agent_cfg#(.DeviceDataWidth(EDN_DATA_WIDTH)) m_edn_pull_agent_cfg[];
diff --git a/hw/dv/sv/cip_lib/cip_base_scoreboard.sv b/hw/dv/sv/cip_lib/cip_base_scoreboard.sv
index 522e003..eafa277 100644
--- a/hw/dv/sv/cip_lib/cip_base_scoreboard.sv
+++ b/hw/dv/sv/cip_lib/cip_base_scoreboard.sv
@@ -86,10 +86,8 @@
$sformatf("tl_intg_err_mem_subword_cgs_wrap[%0s]", ral_name));
end
- if (cfg.en_tl_intg_gen) begin
- tl_intg_err_cgs_wrap[ral_name] = new($sformatf("tl_intg_err_cgs_wrap[%0s]", ral_name));
- if (!has_mem) tl_intg_err_cgs_wrap[ral_name].tl_intg_err_cg.cp_is_mem.option.weight = 0;
- end
+ tl_intg_err_cgs_wrap[ral_name] = new($sformatf("tl_intg_err_cgs_wrap[%0s]", ral_name));
+ if (!has_mem) tl_intg_err_cgs_wrap[ral_name].tl_intg_err_cg.cp_is_mem.option.weight = 0;
end
endfunction
@@ -347,35 +345,33 @@
csr_size_err = !is_tl_csr_write_size_gte_csr_width(item, ral_name);
tl_item_err = item.get_exp_d_error();
- if (cfg.en_tl_intg_gen) begin
- has_intg_err = !item.is_a_chan_intg_ok(.throw_error(0));
+ has_intg_err = !item.is_a_chan_intg_ok(.throw_error(0));
- // If we got an error response caused by an integrity failure, update the mirrored value for
- // any bus integrity alert field (if there is one).
- if (has_intg_err) begin
- update_tl_alert_field_prediction();
- end
+ // If we got an error response caused by an integrity failure, update the mirrored value for
+ // any bus integrity alert field (if there is one).
+ if (has_intg_err) begin
+ update_tl_alert_field_prediction();
+ end
- if (channel == DataChannel) begin
- cip_tl_seq_item cip_item;
- tl_intg_err_e tl_intg_err_type;
- uint num_cmd_err_bits, num_data_err_bits;
+ if (channel == DataChannel) begin
+ cip_tl_seq_item cip_item;
+ tl_intg_err_e tl_intg_err_type;
+ uint num_cmd_err_bits, num_data_err_bits;
- // integrity at d_user is from DUT, which should be always correct
- void'(item.is_d_chan_intg_ok(.throw_error(1)));
+ // integrity at d_user is from DUT, which should be always correct
+ void'(item.is_d_chan_intg_ok(.throw_error(1)));
- // sample covergroup
- `downcast(cip_item, item)
- cip_item.get_a_chan_err_info(tl_intg_err_type, num_cmd_err_bits, num_data_err_bits);
- tl_intg_err_cgs_wrap[ral_name].sample(tl_intg_err_type, num_cmd_err_bits, num_data_err_bits,
- is_mem_addr(item, ral_name));
+ // sample covergroup
+ `downcast(cip_item, item)
+ cip_item.get_a_chan_err_info(tl_intg_err_type, num_cmd_err_bits, num_data_err_bits);
+ tl_intg_err_cgs_wrap[ral_name].sample(tl_intg_err_type, num_cmd_err_bits, num_data_err_bits,
+ is_mem_addr(item, ral_name));
- if (tl_intg_err_mem_subword_cgs_wrap.exists(ral_name)) begin
- tl_intg_err_mem_subword_cgs_wrap[ral_name].sample(
- .tl_intg_err_type(tl_intg_err_type),
- .write(item.a_opcode != tlul_pkg::Get),
- .num_enable_bytes($countones(item.a_mask)));
- end
+ if (tl_intg_err_mem_subword_cgs_wrap.exists(ral_name)) begin
+ tl_intg_err_mem_subword_cgs_wrap[ral_name].sample(
+ .tl_intg_err_type(tl_intg_err_type),
+ .write(item.a_opcode != tlul_pkg::Get),
+ .num_enable_bytes($countones(item.a_mask)));
end
end
diff --git a/hw/dv/sv/cip_lib/doc/index.md b/hw/dv/sv/cip_lib/doc/index.md
index b7a5f17..e871fa4 100644
--- a/hw/dv/sv/cip_lib/doc/index.md
+++ b/hw/dv/sv/cip_lib/doc/index.md
@@ -85,8 +85,6 @@
super.initialize(csr_base_addr); // ral model is created in `super.initialize`
tl_intg_alert_fields[ral.a_status_reg.a_field] = value;
```
-* **en_tl_intg_gen**: Controls whether the TLUL integrity error is generated in
- sequences / checked by the scoreboard.
Apart from these, there are several common settings such as `zero_delays`,
`clk_freq_mhz`, which are randomized as well as knobs such as `en_scb` and
@@ -277,10 +275,7 @@
### cip_tl_seq_item
This is extended class of tl_seq_item to generate correct integrity values in
-a_user and d_user. If DUT relies on the agent to generate integrity for TLUL, set
-`cfg.en_tl_intg_gen = 1`, cip_tl_seq_item will override tl_seq_item, and integrity
-values will be generated. If TLUL integrity is handled in the DUT, set
-`cfg.en_tl_intg_gen = 0`, then `a_user` and `d_user` will be fully randomized.
+`a_user` and `d_user`.
## Extending from CIP library classes
Let's say we are verifying an actual comportable IP `uart` which has `uart_tx`
diff --git a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq__tl_errors.svh b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq__tl_errors.svh
index e455543..5ea4693 100644
--- a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq__tl_errors.svh
+++ b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq__tl_errors.svh
@@ -266,8 +266,6 @@
endtask
virtual task run_tl_intg_err_vseq_sub(int num_times = 1, string ral_name);
- `DV_CHECK_EQ(cfg.en_tl_intg_gen, 1)
-
fork
// run csr_rw seq to send some normal CSR accesses in parallel
begin
@@ -283,7 +281,6 @@
check_tl_intg_error_response();
end
join
-
endtask
virtual task issue_tl_access_w_intg_err(string ral_name);
diff --git a/hw/dv/sv/cip_lib/seq_lib/cip_tl_seq_item.sv b/hw/dv/sv/cip_lib/seq_lib/cip_tl_seq_item.sv
index 0132fda..4c907a6 100644
--- a/hw/dv/sv/cip_lib/seq_lib/cip_tl_seq_item.sv
+++ b/hw/dv/sv/cip_lib/seq_lib/cip_tl_seq_item.sv
@@ -12,8 +12,8 @@
int max_ecc_errors = MAX_TL_ECC_ERRORS;
`uvm_object_utils_begin(cip_tl_seq_item)
- `uvm_field_enum(tl_intg_err_e, tl_intg_err_type, UVM_DEFAULT)
- `uvm_field_int(max_ecc_errors, UVM_DEFAULT)
+ `uvm_field_enum(tl_intg_err_e, tl_intg_err_type, UVM_DEFAULT)
+ `uvm_field_int(max_ecc_errors, UVM_DEFAULT)
`uvm_object_utils_end
function void post_randomize();
@@ -54,8 +54,8 @@
user.rsvd = '0;
user.instr_type = instr_type;
- user.cmd_intg = cmd_with_intg[H2DCmdFullWidth -1 -: H2DCmdIntgWidth];
- user.data_intg = data_with_intg[DataFullWidth -1 -: DataIntgWidth];
+ user.cmd_intg = cmd_with_intg[H2DCmdFullWidth - 1 -: H2DCmdIntgWidth];
+ user.data_intg = data_with_intg[DataFullWidth - 1 -: DataIntgWidth];
return user;
endfunction : compute_a_user
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl.sv b/hw/ip/lc_ctrl/rtl/lc_ctrl.sv
index e94ddeb..ff635d6 100644
--- a/hw/ip/lc_ctrl/rtl/lc_ctrl.sv
+++ b/hw/ip/lc_ctrl/rtl/lc_ctrl.sv
@@ -209,7 +209,9 @@
);
// DMI to TL-UL transducing
- tlul_adapter_host u_tap_tlul_host (
+ tlul_adapter_host #(
+ .EnableDataIntgGen(1)
+ ) u_tap_tlul_host (
.clk_i,
.rst_ni,
// do not make a request unless there is room for the response
diff --git a/hw/ip/rv_dm/rtl/rv_dm.sv b/hw/ip/rv_dm/rtl/rv_dm.sv
index 4abe918..4e518ec 100644
--- a/hw/ip/rv_dm/rtl/rv_dm.sv
+++ b/hw/ip/rv_dm/rtl/rv_dm.sv
@@ -304,6 +304,7 @@
end
tlul_adapter_host #(
+ .EnableDataIntgGen(1),
.MAX_REQS(1)
) tl_adapter_host_sba (
.clk_i,
diff --git a/hw/ip/tlul/rtl/tlul_adapter_host.sv b/hw/ip/tlul/rtl/tlul_adapter_host.sv
index a54690d..eecec8b 100644
--- a/hw/ip/tlul/rtl/tlul_adapter_host.sv
+++ b/hw/ip/tlul/rtl/tlul_adapter_host.sv
@@ -26,8 +26,7 @@
import prim_mubi_pkg::mubi4_t;
#(
parameter int unsigned MAX_REQS = 2,
- // TODO(#7966) disable data intgrity overwrite once dv support available
- parameter bit EnableDataIntgGen = 1
+ parameter bit EnableDataIntgGen = 0
) (
input clk_i,
input rst_ni,
@@ -107,7 +106,6 @@
d_ready: 1'b1
};
- // TODO #7966 disable data intgrity overwrite once dv support available
tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
.tl_i(tl_out),
.tl_o(tl_o)
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index 3a383b6..9748dfb 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -398,11 +398,22 @@
force `CPU_CORE_HIER.clk_i = 1'b0;
force `CPU_HIER.u_ibus_trans.rst_ni = 1'b0;
force `CPU_HIER.u_dbus_trans.rst_ni = 1'b0;
- // tl type is used to calculate ECC and we use DataType for cpu data interface
- force cpu_d_tl_if.h2d.a_user.instr_type = prim_mubi_pkg::MuBi4False;
force `CPU_TL_ADAPT_D_HIER.tl_out = cpu_d_tl_if.h2d;
force cpu_d_tl_if.d2h = `CPU_TL_ADAPT_D_HIER.tl_i;
+ // TL command integrity gen is in the design data path. TL driver provides correct cmd intg.
+ // Here forces it to random value to ensure that design generates the cmd intg
+ fork
+ forever begin
+ @(cpu_d_tl_if.h2d.a_valid);
+ if (cpu_d_tl_if.h2d.a_valid) begin
+ force `CPU_TL_ADAPT_D_HIER.tl_out.a_user.cmd_intg = $urandom;
+ end else begin
+ release `CPU_TL_ADAPT_D_HIER.tl_out.a_user.cmd_intg;
+ end
+ end
+ join_none
+
// In stub_cpu mode, disable these assertions because writing rand value to clkmgr's CSR
// `extclk_sel` can violate these assertions.
$assertoff(0, tb.dut.u_ast.u_ast_clks_byp.u_all_clk_byp_req.PrimMubi4SyncCheckTransients_A);
diff --git a/hw/top_earlgrey/dv/tests/chip_base_test.sv b/hw/top_earlgrey/dv/tests/chip_base_test.sv
index 3433d8d..b001817 100644
--- a/hw/top_earlgrey/dv/tests/chip_base_test.sv
+++ b/hw/top_earlgrey/dv/tests/chip_base_test.sv
@@ -22,9 +22,6 @@
super.build_phase(phase);
- // TL integrity gen is in the design data path, no need to generate it in the agent
- cfg.en_tl_intg_gen = 0;
-
// Knob to en/dis stubbing cpu (disabled by default).
void'($value$plusargs("stub_cpu=%0b", cfg.stub_cpu));
// Set tl_agent's is_active bit based on the retrieved stub_cpu value.
