commit e34ccdc62e89fef3fbb7382bba64d4bb4817150c
author Cindy Chen <chencindy@google.com> Tue Oct 22 15:58:38 2019 -0700
committer cindychip <cindy.chen0316@gmail.com> Thu Oct 24 14:43:12 2019 -0700
tree d12ea9eadd35d059b596bbb0bda42cd59cfeb4a2
parent afd0505619074190ed659965d16e030d8ca00439

[hmac/dv] Enable mem_read err and fix minor issue

Enable mem_read error in hmac_env_cfg
Fix hmac typo
Use an enum type for hmac cmd reg fields

hw/ip/hmac/dv/env/hmac_env_cfg.sv

diff --git a/hw/ip/hmac/dv/env/hmac_env_cfg.sv b/hw/ip/hmac/dv/env/hmac_env_cfg.sv
index e541ee0..2295f2b 100644
--- a/hw/ip/hmac/dv/env/hmac_env_cfg.sv
+++ b/hw/ip/hmac/dv/env/hmac_env_cfg.sv
@@ -11,9 +11,7 @@
     mem_addr_s mem_addr;
     super.initialize(csr_base_addr, csr_addr_map_size);
     en_mem_byte_write   = 1;
-    // TODO uncommented below to test mem read trigger error
-    // when issue is solved at github.com/lowRISC/opentitan/issues/236
-    // en_mem_read       = 0;
+    en_mem_read         = 0;
     mem_addr.start_addr = HMAC_MSG_FIFO_BASE;
     mem_addr.end_addr   = HMAC_MSG_FIFO_LAST_ADDR;
     mem_addrs.push_back(mem_addr);

hw/ip/hmac/dv/env/hmac_env_pkg.sv

diff --git a/hw/ip/hmac/dv/env/hmac_env_pkg.sv b/hw/ip/hmac/dv/env/hmac_env_pkg.sv
index 156b2b2..8abb2bb 100644
--- a/hw/ip/hmac/dv/env/hmac_env_pkg.sv
+++ b/hw/ip/hmac/dv/env/hmac_env_pkg.sv
@@ -50,6 +50,11 @@
     DigestSwap
   } hmac_cfg_e;
 
+  typedef enum {
+    HashStart,
+    HashProcess
+  } hmac_cmd_e;
+
   typedef class hmac_env_cfg;
   typedef class hmac_env_cov;
   typedef cip_base_virtual_sequencer #(hmac_env_cfg, hmac_env_cov) hmac_virtual_sequencer;

hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv

diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
index 9a32a7b..0b07bcc 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
@@ -81,11 +81,11 @@
 
   // trigger hash computation to start
   virtual task trigger_hash();
-    csr_wr(.csr(ral.cmd), .value(1'b1));
+    csr_wr(.csr(ral.cmd), .value(1'b1 << HashStart));
   endtask
 
   virtual task trigger_process();
-    csr_wr(.csr(ral.cmd), .value(2'b10));
+    csr_wr(.csr(ral.cmd), .value(1'b1 << HashProcess));
   endtask
 
   // read digest value
@@ -217,13 +217,14 @@
     end else begin
       csr_rd_check(.ptr(ral.intr_state), .compare_value(msg_fifo_full),
                    .compare_mask(1 << HmacMsgFifoFull));
-      csr_wr(.csr(ral.intr_state), .value(1 << HmacDone));
+      csr_wr(.csr(ral.intr_state), .value(1 << HmacMsgFifoFull));
     end
   endtask
 
   // when msg fifo full interrupt is set, this task clears the interrupt
   // checking the correctness of the fifo full interrupt is done in scb
   virtual task clear_intr_fifo_full();
+    csr_utils_pkg::wait_no_outstanding_access();
     if (ral.intr_enable.fifo_full.get_mirrored_value()) begin
       if (cfg.intr_vif.pins[HmacMsgFifoFull] === 1'b1) begin
         check_interrupts(.interrupts((1 << HmacMsgFifoFull)), .check_set(1'b1));