[dv/chip] Enhance pwrmgr_smoketest
Add rstmgr RESET_INFO CSR checks.
Cross-reference test from aon_timer and rstmgr testpoints.
Signed-off-by: Guillermo Maturana <maturana@google.com>
diff --git a/hw/top_earlgrey/data/chip_testplan.hjson b/hw/top_earlgrey/data/chip_testplan.hjson
index b09443d..88465cd 100644
--- a/hw/top_earlgrey/data/chip_testplan.hjson
+++ b/hw/top_earlgrey/data/chip_testplan.hjson
@@ -539,7 +539,7 @@
not be reset.
'''
milestone: V2
- tests: []
+ tests: ["chip_pwrmgr_smoketest"]
}
{
name: chip_aon_timer_clks_resets
@@ -868,7 +868,7 @@
TODO(maturana) Add specific tests once they are developed.
'''
milestone: V2
- tests: []
+ tests: ["chip_pwrmgr_smoketest"]
}
{
name: chip_rstrmgr_sys_reset_info
diff --git a/sw/device/tests/meson.build b/sw/device/tests/meson.build
index 7abdc20..1b1c8ae 100644
--- a/sw/device/tests/meson.build
+++ b/sw/device/tests/meson.build
@@ -292,6 +292,7 @@
sources: ['pwrmgr_smoketest.c'],
dependencies: [
sw_lib_dif_pwrmgr,
+ sw_lib_dif_rstmgr,
sw_lib_dif_aon_timer,
sw_lib_mmio,
sw_lib_runtime_log,
diff --git a/sw/device/tests/pwrmgr_smoketest.c b/sw/device/tests/pwrmgr_smoketest.c
index a317889..2ed8896 100644
--- a/sw/device/tests/pwrmgr_smoketest.c
+++ b/sw/device/tests/pwrmgr_smoketest.c
@@ -5,6 +5,7 @@
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/dif/dif_aon_timer.h"
#include "sw/device/lib/dif/dif_pwrmgr.h"
+#include "sw/device/lib/dif/dif_rstmgr.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/testing/check.h"
#include "sw/device/lib/testing/test_framework/test_main.h"
@@ -49,6 +50,7 @@
bool test_main(void) {
dif_pwrmgr_t pwrmgr;
+ dif_rstmgr_t rstmgr;
dif_aon_timer_t aon_timer;
// Initialize pwrmgr
@@ -59,13 +61,31 @@
},
&pwrmgr) == kDifPwrmgrOk);
+ // Initialize rstmgr since this will check some registers.
+ CHECK(dif_rstmgr_init(
+ (dif_rstmgr_params_t){
+ .base_addr =
+ mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR),
+ },
+ &rstmgr) == kDifRstmgrOk);
+
// Assuming the chip hasn't slept yet, wakeup reason should be empty.
+ // Notice we are clear rstmgr's RESET_INFO, so after the aon wakeup there
+ // is only one bit set.
dif_pwrmgr_wakeup_reason_t wakeup_reason;
CHECK(dif_pwrmgr_wakeup_reason_get(&pwrmgr, &wakeup_reason) == kDifPwrmgrOk);
if (compare_wakeup_reasons(&wakeup_reason, &kWakeUpReasonPor)) {
LOG_INFO("Powered up for the first time, begin test");
+ LOG_INFO("Check the rstmgr reset_info is POR");
+ dif_rstmgr_reset_info_bitfield_t info;
+ CHECK(dif_rstmgr_reset_info_get(&rstmgr, &info) == kDifRstmgrOk);
+ CHECK(info == (dif_rstmgr_reset_info_bitfield_t)(kDifRstmgrResetInfoPor));
+
+ // Clear reset_info.
+ CHECK(dif_rstmgr_reset_info_clear(&rstmgr) == kDifRstmgrOk);
+
// Initialize aon_timer
dif_aon_timer_params_t params = {
.base_addr =
@@ -73,7 +93,7 @@
};
CHECK(dif_aon_timer_init(params, &aon_timer) == kDifAonTimerOk);
- // Issue a wakeup singal in ~150us through the AON timer.
+ // Issue a wakeup signal in ~150us through the AON timer.
//
// At 200kHz, threshold of 30 is equal to 150us. There is an additional
// ~4 cycle overhead for the CSR value to synchronize with the AON clock.
@@ -106,6 +126,11 @@
} else if (compare_wakeup_reasons(&wakeup_reason, &kWakeUpReasonTest)) {
LOG_INFO("Aon timer wakeup detected");
+ LOG_INFO("Check the rstmgr reset_info is LOW_POWER timer wakeup detected");
+ dif_rstmgr_reset_info_bitfield_t info;
+ CHECK(dif_rstmgr_reset_info_get(&rstmgr, &info) == kDifRstmgrOk);
+ CHECK(info ==
+ (dif_rstmgr_reset_info_bitfield_t)(kDifRstmgrResetInfoLowPowerExit));
return true;
} else {
