| commit | e2de5d92977826085545844d155c36d2259edbaa | [log] [tgz] |
|---|---|---|
| author | Martin Lueker-Boden <martin.lueker-boden@wdc.com> | Fri Oct 15 14:44:32 2021 -0700 |
| committer | Martin Lueker-Boden <47870387+martin-lueker@users.noreply.github.com> | Tue Oct 19 14:35:55 2021 -0700 |
| tree | 94baca522855f76ccd06806a466fe4990095677d | |
| parent | 619e3124398b90f562aa6eb18834514fcaf53ea9 [diff] |
[ spi_host rtl ] Prepare to move entire SPI_HOST IP the peripheral clock domain This is the first of two commits which aim to standardize the CDC strategy for SPI_HOST In this first commit: - An explicit tlul_async_fifo is created inside spi_host.sv. This FIFO will eventually move to the TLUL fabric or the register interface. However putting it inside the IP for now allows for testing of changes to other blocks without changing the interface, which would disrupt DV testing. - The command_cdc has been removed in favor of a shallow synchronous FIFO in spi_host_command_queue. - spi_host_data_cdc with its async fifos have also been removed in favor of spi_host_data_fifos, in which the fifos are synchronous Pending until next commit: - Migration of TLUL fifo to some automated system (TLUL fabric? Regtool?) - Removal of "Core" clocks & resets - Change COMMAND register to hw_ext - DV Interface updates to change clocks Signed-off-by: Martin Lueker-Boden <martin.lueker-boden@wdc.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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