commit e2dc7da55c962d5c9e76e2c06cdd24f6b8185160
author Cindy Chen <chencindy@google.com> Fri Oct 25 13:28:30 2019 -0700
committer cindychip <cindy.chen0316@gmail.com> Fri Oct 25 14:16:42 2019 -0700
tree d5a22b37b8dc24b65b68528dd85e373bfddcfe86
parent ae281b6cfd6d49e11710e74c3693bd4d043b66b6

[dv/hmac] interrupt test fix not always reset

Fix intr_test sequence not always reset intr_state signal

hw/ip/hmac/dv/env/hmac_scoreboard.sv

diff --git a/hw/ip/hmac/dv/env/hmac_scoreboard.sv b/hw/ip/hmac/dv/env/hmac_scoreboard.sv
index c17b7a2..5d38e38 100644
--- a/hw/ip/hmac/dv/env/hmac_scoreboard.sv
+++ b/hw/ip/hmac/dv/env/hmac_scoreboard.sv
@@ -80,7 +80,8 @@
             end
           end
           "intr_test": begin // testmode, intr_state is W1C, cannot use UVM_PREDICT_WRITE
-            void'(ral.intr_state.predict(.value(item.a_data), .kind(UVM_PREDICT_DIRECT)));
+            bit [TL_DW-1:0] intr_state_exp = item.a_data | ral.intr_state.get_mirrored_value();
+            void'(ral.intr_state.predict(.value(intr_state_exp), .kind(UVM_PREDICT_DIRECT)));
           end
           "cfg": begin
             cov.cfg_cg.sample(item.a_data);