[sysrst_ctrl,dv] Updated SYSRST_CTRL DV documents
Signed-off-by: Madhuri Patel <madhuri.patel@ensilica.com>
diff --git a/hw/ip/sysrst_ctrl/doc/dv/index.md b/hw/ip/sysrst_ctrl/doc/dv/index.md
index 2113694..25bd9f5 100644
--- a/hw/ip/sysrst_ctrl/doc/dv/index.md
+++ b/hw/ip/sysrst_ctrl/doc/dv/index.md
@@ -53,10 +53,8 @@
### Global types & methods
All common types and methods defined at the package level can be found in
-`sysrst_ctrl_env_pkg`. Some of them in use are:
-```systemverilog
-[list a few parameters, types & methods; no need to mention all]
-```
+`sysrst_ctrl_env_pkg`.
+
### TL_agent
The SYSRST_CTRL testbench instantiates (already handled in CIP base env) [tl_agent]({{< relref "hw/dv/sv/tl_agent/README.md" >}}).
This provides the ability to drive and independently monitor random traffic via the TL host interface into the SYSRST_CTRL device.
@@ -76,29 +74,40 @@
The test sequences reside in `hw/ip/sysrst_ctrl/dv/env/seq_lib`.
All test sequences are extended from `sysrst_ctrl_base_vseq`, which is extended from `cip_base_vseq` and serves as a starting point.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
-Some of the most commonly used tasks / functions are as follows:
-* task 1:
-* task 2:
#### Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model.
The following covergroups have been developed to prove that the test intent has been adequately met:
-* cg1:
-* cg2:
+* sysrst_ctrl_combo_detect_action_cg: This covergroup will cover all the combo detect actions for combo detect register set 0-3.
+* sysrst_ctrl_combo_detect_sel_cg: This covergroup will sample the input selected for combo detect.
+* sysrst_ctrl_combo_detect_det_cg: This covergroup will cover the combo detect debounce timer value.
+* sysrst_ctrl_auto_block_debounce_ctl_cg: This will cover the auto block enable/disable feature, debounce timer value.
+* sysrst_ctrl_combo_intr_status_cg: This covergroup will capture the combo detect interrupt status.
+* sysrst_ctrl_key_intr_status_cg: This covergroup will capture the edge detect status for all the inputs.
+* sysrst_ctrl_ulp_status_cg: This covergroup will cover the ultra low power status.
+* sysrst_ctrl_wkup_status_cg: This will capture the wakeup status event after the low power event is triggered.
+* sysrst_ctrl_pin_in_value_cg: This covergroup will cover the raw input values of all the input pins.
+* sysrst_ctrl_auto_blk_out_ctl_cg: This covergroup will cover the input selected for auto block and the output value status for the selected input pin.
+* pin_cfg_cg: This is the generic covergroup to cover the override and allowed values for the selected input and output values. An array of this covergroup is
+created for all the input pins.
+* debounce_timer_cg: This is the generic covergroup to cover the debounce timer values for the below register.
+key_intr_debounce_ctl
+ulp_ac_debounce_ctl
+ulp_pwrb_debounce_ctl
+ulp_lid_debounce_ctl
+ec_rst_ctl
+* sysrst_ctrl_key_invert_ctl_cg: This covergroup will cover which input/output pins are allowed to invert their values.The invert values are crossed with the input/output values.
### Self-checking strategy
#### Scoreboard
The `sysrst_ctrl_scoreboard` is primarily used for end to end checking.
-It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
-* analysis port1:
-* analysis port2:
-<!-- explain inputs monitored, flow of data and outputs checked -->
#### Assertions
-* TLUL assertions: The `tb/sysrst_ctrl_bind.sv` file binds the `tlul_assert` [assertions]({{< relref "hw/ip/tlul/doc/TlulProtocolChecker.md" >}}) to the IP to ensure TileLink interface protocol compliance.
+* TLUL assertions: The `sva/sysrst_ctrl_bind.sv` file binds the `tlul_assert` [assertions]({{< relref "hw/ip/tlul/doc/TlulProtocolChecker.md" >}}) to the IP to ensure TileLink interface protocol compliance.
* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
-* assert prop 1:
-* assert prop 2:
+* Assertions in `tb.sv`
+* CheckFlashWrProtRst: Checks flash_wp_l output pin is asserted active low which it is in reset.
+* CheckEcPwrOnRst: Checks ec_rst_l_o is asserted active low when it is in reset.
## Building and running tests
We are using our in-house developed [regression tool]({{< relref "hw/dv/tools/README.md" >}}) for building and running our tests and regressions.
