[dv] Port HMAC to use dvsim regr tool
- added HMAC sim configuration hjson file with test specifications
- minor fixes and enhancements
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/dv/data/common_sim_cfg.hjson b/hw/dv/data/common_sim_cfg.hjson
index f6bc1ef..4c56946 100644
--- a/hw/dv/data/common_sim_cfg.hjson
+++ b/hw/dv/data/common_sim_cfg.hjson
@@ -94,18 +94,24 @@
// tests.
regressions: [
{
+ name: sanity
+ tests: ["{name}_sanity"]
+ }
+
+ {
name: all
tests: []
}
+
{
name: all_once
reseed: 1
tests: []
}
+
{
name: nightly
tests: []
- // excl_tests: []
en_sim_modes: ["cov"]
}
]
diff --git a/hw/dv/data/tests/csr_tests.hjson b/hw/dv/data/tests/csr_tests.hjson
index 07172e1..ceee220 100644
--- a/hw/dv/data/tests/csr_tests.hjson
+++ b/hw/dv/data/tests/csr_tests.hjson
@@ -36,6 +36,11 @@
regressions: [
{
+ name: sanity
+ tests: ["{name}_csr_hw_reset", "{name}_csr_rw"]
+ }
+
+ {
name: sw_access
tests: ["{name}_csr_hw_reset",
"{name}_csr_rw",
diff --git a/hw/ip/hmac/dv/hmac_sim_cfg.hjson b/hw/ip/hmac/dv/hmac_sim_cfg.hjson
new file mode 100644
index 0000000..177fc77
--- /dev/null
+++ b/hw/ip/hmac/dv/hmac_sim_cfg.hjson
@@ -0,0 +1,93 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // Name of the sim cfg - typically same as the IP under test.
+ name: hmac
+
+ // Top level dut name (sv module).
+ dut: hmac
+
+ // Top level testbench name (sv module).
+ tb: tb
+
+ // Fusesoc core file used for building the file list.
+ fusesoc_core: lowrisc:dv:hmac_sim:0.1
+
+ // Testplan hjson file.
+ testplan: "{proj_root}/hw/ip/hmac/data/hmac_testplan.hjson"
+
+ // RAL spec - used to generate the RAL model.
+ ral_spec: "{proj_root}/hw/ip/hmac/data/hmac.hjson"
+
+ // Import additional common sim cfg files.
+ import_cfgs: [// Project wide common sim cfg file
+ "{proj_root}/hw/dv/data/common_sim_cfg.hjson",
+ // Common CIP test lists
+ "{proj_root}/hw/dv/data/tests/csr_tests.hjson",
+ "{proj_root}/hw/dv/data/tests/intr_test.hjson",
+ "{proj_root}/hw/dv/data/tests/tl_access_tests.hjson",
+ "{proj_root}/hw/dv/data/tests/stress_tests.hjson"]
+
+ // Default iterations for all tests - each test entry can override this.
+ reseed: 50
+
+ // Default UVM test and seq class name.
+ uvm_test: hmac_base_test
+ uvm_test_seq: hmac_base_vseq
+
+ // List of test specifications.
+ tests: [
+ {
+ name: hmac_sanity
+ uvm_test_seq: hmac_sanity_vseq
+ }
+
+ {
+ name: hmac_long_msg
+ uvm_test_seq: hmac_long_msg_vseq
+ }
+
+ {
+ name: hmac_back_pressure
+ uvm_test_seq: hmac_back_pressure_vseq
+ run_opts: ["+zero_delays=1"]
+ }
+
+ {
+ name: hmac_datapath_stress
+ uvm_test_seq: hmac_datapath_stress_vseq
+ run_opts: ["+zero_delays=1"]
+ }
+
+ {
+ name: hmac_burst_wr
+ uvm_test_seq: hmac_burst_wr_vseq
+ }
+
+ {
+ name: hmac_test_sha_vectors
+ uvm_test_seq: hmac_test_vectors_sha_vseq
+ run_opts: ["+test_vectors_dir={proj_root}/hw/dv/sv/test_vectors"]
+ }
+
+ {
+ name: hmac_test_hmac_vectors
+ uvm_test_seq: hmac_test_vectors_hmac_vseq
+ run_opts: ["+test_vectors_dir={proj_root}/hw/dv/sv/test_vectors"]
+ }
+
+ {
+ // Append the common stress_tests.hjson entry for more run_opts.
+ name: hmac_stress_all
+ run_opts: ["+test_vectors_dir={proj_root}/hw/dv/sv/test_vectors"]
+ }
+
+ {
+ // Append the common stress_tests.hjson entry for more run_opts.
+ name: hmac_stress_all_with_rand_reset
+ run_opts: ["+test_vectors_dir={proj_root}/hw/dv/sv/test_vectors"]
+ }
+ ]
+}
+
diff --git a/hw/ip/uart/dv/sim_cfg.hjson b/hw/ip/uart/dv/sim_cfg.hjson
index 05fbf21..39e6574 100644
--- a/hw/ip/uart/dv/sim_cfg.hjson
+++ b/hw/ip/uart/dv/sim_cfg.hjson
@@ -23,7 +23,7 @@
// Import additional common sim cfg files.
import_cfgs: [// Project wide common sim cfg file
"{proj_root}/hw/dv/data/common_sim_cfg.hjson",
- // List of common CIP test lists that apply to UART
+ // Common CIP test lists
"{proj_root}/hw/dv/data/tests/csr_tests.hjson",
"{proj_root}/hw/dv/data/tests/intr_test.hjson",
"{proj_root}/hw/dv/data/tests/tl_access_tests.hjson",
@@ -32,8 +32,9 @@
// Default iterations for all tests - each test entry can override this.
reseed: 50
- // Default UVM test class name.
+ // Default UVM test and seq class name.
uvm_test: uart_base_test
+ uvm_test_seq: uart_base_vseq
// List of test specifications.
tests: [
@@ -49,13 +50,11 @@
{
name: uart_fifo_full
- reseed: 20
uvm_test_seq: uart_fifo_full_vseq
}
{
name: uart_fifo_overflow
- reseed: 100
uvm_test_seq: uart_fifo_overflow_vseq
}
@@ -106,12 +105,4 @@
run_opts: ["+zero_delays=1"]
}
]
-
- // List of regression specifications.
- regressions: [
- {
- name: sanity
- tests: ["uart_sanity", "uart_csr_hw_reset"]
- }
- ]
}
diff --git a/util/dvsim/Deploy.py b/util/dvsim/Deploy.py
index f587d1b..34eacaf 100644
--- a/util/dvsim/Deploy.py
+++ b/util/dvsim/Deploy.py
@@ -311,7 +311,7 @@
while all_done == 0:
time.sleep(1)
num_secs += 1
- trig_print = False
+ trig_print = ((num_secs % Deploy.print_interval) == 0)
for item in Deploy.items:
if item.target not in status.keys():
status[item.target] = {}
@@ -335,13 +335,14 @@
all_done = 1
else:
num_slots = Deploy.max_parallel - Deploy.dispatch_counter
- trig_print = True
- if len(dispatch_items_queue) > num_slots:
- dispatch_items(dispatch_items_queue[0:num_slots])
- dispatch_items_queue = dispatch_items_queue[num_slots:]
- else:
- dispatch_items(dispatch_items_queue)
- dispatch_items_queue = []
+ if num_slots > 0:
+ trig_print = True
+ if len(dispatch_items_queue) > num_slots:
+ dispatch_items(dispatch_items_queue[0:num_slots])
+ dispatch_items_queue = dispatch_items_queue[num_slots:]
+ else:
+ dispatch_items(dispatch_items_queue)
+ dispatch_items_queue = []
status_str = {}
for target in status.keys():
@@ -354,7 +355,7 @@
status_str[target] += "]"
# Print the status string periodically
- if trig_print or (num_secs % Deploy.print_interval) == 0:
+ if trig_print:
for target in status_str.keys():
if targets_done[target] is True: continue
log.info("[dvsim]: [%06ds] [%s]: %s", num_secs, target,
