commit e16009bcc6c0c7fbbe56c733a3a6358eda63003e
author Cindy Chen <chencindy@opentitan.org> Mon Nov 01 19:35:51 2021 -0700
committer cindychip <cindy.chen0316@gmail.com> Mon Nov 08 10:04:34 2021 -0800
tree 27909786d4b7c0da5a6f4a6d93dbd388bcb2b2b9
parent 0f60351bd8a440e5db031cf20f6d31d099700380

[dv/ralgen] Update the `dv-base-prefix` optional input

This PR supports a more flexible `--dv-base-prefix` optional input
argument when using ralgen to create uvm_ral classes.
This PR allows user to override base class for any IP, and any types of
base classes (include reg, reg_field, reg_block, and reg_pkg)

Signed-off-by: Cindy Chen <chencindy@opentitan.org>

util/topgen/gen_dv.py

diff --git a/util/topgen/gen_dv.py b/util/topgen/gen_dv.py
index 5e2beaa..2a59d9c 100644
--- a/util/topgen/gen_dv.py
+++ b/util/topgen/gen_dv.py
@@ -20,7 +20,7 @@
 
 
 def gen_dv(top: Top,
-           dv_base_prefix: str,
+           dv_base_names: str,
            outdir: str) -> int:
     '''Generate DV RAL model for a Top'''
     # Read template
@@ -31,7 +31,7 @@
     # Expand template
     try:
         to_write = uvm_reg_tpl.render(top=top,
-                                      dv_base_prefix=dv_base_prefix)
+                                      dv_base_names=dv_base_names)
     except:  # noqa: E722
         log.error(exceptions.text_error_template().render())
         return 1
@@ -41,6 +41,6 @@
     with open(dest_path, 'w') as fout:
         fout.write(to_write)
 
-    gen_core_file(outdir, 'chip', dv_base_prefix, ['chip_ral_pkg.sv'])
+    gen_core_file(outdir, 'chip', dv_base_names, ['chip_ral_pkg.sv'])
 
     return 0