[topgen] Don't generate empty clock_reset_export entries
The check_clk_rst_export function was essentially the same thing as
setdefault(). Since topgen's merge.py is actually the only thing that
reads this key, keep the same defaulting behaviour but don't actually
generate extra entries.
If we don't do this, we have to add clock_reset_export to the optional
fields list for every type in topgen/validate.py to avoid a warning.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 58b5362..49679ca 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -413,7 +413,6 @@
rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40000000
- clock_reset_export: []
clock_group: secure
clock_connections:
{
@@ -573,7 +572,6 @@
rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40010000
- clock_reset_export: []
clock_group: secure
clock_connections:
{
@@ -733,7 +731,6 @@
rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40020000
- clock_reset_export: []
clock_group: secure
clock_connections:
{
@@ -893,7 +890,6 @@
rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40030000
- clock_reset_export: []
clock_group: secure
clock_connections:
{
@@ -1054,7 +1050,6 @@
rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40040000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_peri
@@ -1123,7 +1118,6 @@
rst_ni: rstmgr_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40050000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_peri
@@ -1269,7 +1263,6 @@
rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40100000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_timers
@@ -1497,7 +1490,6 @@
rst_edn_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40130000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_timers
@@ -1830,7 +1822,6 @@
rst_ni: rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40140000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_timers
@@ -2296,7 +2287,6 @@
AccuCntDw: 16
LfsrSeed: 0x7FFFFFFF
}
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_timers
@@ -2468,7 +2458,6 @@
rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40160000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_timers
@@ -2594,7 +2583,6 @@
domain: Aon
base_addr: 0x40400000
generated: "true"
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_powerup
@@ -2799,7 +2787,6 @@
domain: Aon
base_addr: 0x40410000
generated: "true"
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_powerup
@@ -2945,7 +2932,6 @@
domain: Aon
base_addr: 0x40420000
generated: "true"
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_powerup
@@ -3120,7 +3106,6 @@
domain: Aon
base_addr: 0x40460000
generated: "true"
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_secure
@@ -3300,7 +3285,6 @@
domain: Aon
base_addr: 0x40470000
generated: "true"
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_secure
@@ -3754,7 +3738,6 @@
}
domain: Aon
base_addr: 0x40510000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_peri
@@ -3882,7 +3865,6 @@
}
base_addr: 0x41000000
generated: "true"
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_infra
@@ -4233,7 +4215,6 @@
}
base_addr: 0x41010000
generated: "true"
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_secure
@@ -4281,7 +4262,6 @@
rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41100000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_aes
@@ -4494,7 +4474,6 @@
rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41110000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_hmac
@@ -4594,7 +4573,6 @@
rst_edn_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41120000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_kmac
@@ -4766,7 +4744,6 @@
rst_edn_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41130000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_secure
@@ -5125,7 +5102,6 @@
rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41150000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_secure
@@ -5280,7 +5256,6 @@
rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41160000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_secure
@@ -5421,7 +5396,6 @@
rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41170000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_secure
@@ -5526,7 +5500,6 @@
rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41180000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_secure
@@ -5633,7 +5606,6 @@
rst_otp_ni: rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x411C0000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_secure
@@ -5759,7 +5731,6 @@
rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x411D0000
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_otbn
@@ -5894,7 +5865,6 @@
index: -1
}
]
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_infra
@@ -5943,7 +5913,6 @@
index: -1
}
]
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_infra
@@ -5993,7 +5962,6 @@
index: -1
}
]
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_io_div4_infra
@@ -6120,7 +6088,6 @@
index: -1
}
]
- clock_reset_export: []
clock_connections:
{
clk_i: clkmgr_clocks.clk_main_infra
@@ -6543,7 +6510,6 @@
rst_main_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
rst_fixed_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
- clock_reset_export: []
clock_connections:
{
clk_main_i: clkmgr_clocks.clk_main_infra
@@ -7265,7 +7231,6 @@
{
rst_peri_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
- clock_reset_export: []
clock_connections:
{
clk_peri_i: clkmgr_clocks.clk_io_div4_infra
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
index af5679a..4222728 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -20,7 +20,6 @@
rst_main_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
rst_fixed_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
- clock_reset_export: []
clock_connections:
{
clk_main_i: clkmgr_clocks.clk_main_infra
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
index e8dceae..4fabea0 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -18,7 +18,6 @@
{
rst_peri_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
- clock_reset_export: []
clock_connections:
{
clk_peri_i: clkmgr_clocks.clk_io_div4_infra
diff --git a/util/topgen/merge.py b/util/topgen/merge.py
index 9d6688f..9f0553c 100644
--- a/util/topgen/merge.py
+++ b/util/topgen/merge.py
@@ -546,15 +546,6 @@
return result
-# Check if the export field already exists
-# If yes, return it
-# If no, set a default and return that
-def check_clk_rst_export(module):
- if 'clock_reset_export' not in module:
- module['clock_reset_export'] = []
- return module['clock_reset_export']
-
-
def amend_clocks(top: OrderedDict):
"""Add a list of clocks to each clock group
Amend the clock connections of each entry to reflect the actual gated clock
@@ -587,7 +578,7 @@
clock_connections = OrderedDict()
# Ensure each module has a default case
- export_if = check_clk_rst_export(ep)
+ export_if = ep.get('clock_reset_export', [])
# if no clock group assigned, default is unique
ep['clock_group'] = 'secure' if 'clock_group' not in ep else ep[
@@ -682,7 +673,7 @@
# This code is here to ensure if amend_clocks/resets switched order
# everything would still work
- export_if = check_clk_rst_export(module)
+ export_if = module.get('clock_reset_export', [])
# There may be multiple export interfaces
for intf in export_if:
