commit | e0aa2c3bcccf785267e23f9da3be4b6984c85cc7 | [log] [tgz] |
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author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Tue Dec 07 17:23:56 2021 +0000 |
committer | Rupert Swarbrick <rswarbrick@gmail.com> | Wed Dec 08 10:39:44 2021 +0000 |
tree | eb0bc95de041462ad9e0c89099447fb8bebf35e6 | |
parent | ef1ebf5b6d939be94f832c993b8890367ae67349 [diff] |
[otbn,dv] Recoverable alert support This was a bit awkward to fit into the existing DV alert framework because running a binary will trigger a recoverable error if the code does something naughty (jumping to a bad address / overflowing a stack etc.). Unfortunately, we don't know ahead of time that this is going to happen, which makes the cip_base_scoreboard::set_exp_alert() function rather difficult to use. So we do things a bit differently, disabling the base class alert tracking and handling alerts ourselves. The basic idea is that if you want to prove expected alert <-> seen alert you can do it with two implications: expected alert -> seen alert seen alert -> expected alert The "expected alert" event happens when OTBN stops with a status of LOCKED (implying a fatal alert) or with a nonzero set of error bits (implying a recoverable alert). The "seen alert" event happens when we see an alert. In each case, we set some flags and then spawn a checker process that will wait a short time and then check that the other event has happened. For recoverable alerts, we also reset the flags to make sure that we can cope with subsequent recoverable alerts without having to see a reset in between. The scoreboard gets a phase_ready_to_end function that checks we don't accidentally stop the test while we're still waiting for an expected alert. In practice, I suspect this will never matter because of the drain time in the base monitor class, but it probably doesn't hurt to be careful. The final change is to simplify the otbn_imem_err sequence: now that the scoreboard handles alerts, there's much less of a dance required to get the timing right. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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