| commit | df662bf3dee4df9b99296054a139daee867153d5 | [log] [tgz] |
|---|---|---|
| author | Guillermo Maturana <maturana@google.com> | Wed Sep 28 21:44:38 2022 -0700 |
| committer | Matute <maturana@google.com> | Fri Oct 07 11:45:22 2022 -0700 |
| tree | a30b9d7fc8007c66e6331cea08bf5cfbc8f97222 | |
| parent | 3db50d206f0289eb1c9e0c2d36d67c8b85bf1bc5 [diff] |
[dv/pwrmgr] Fixes for recent RTL changes The change in handling of reset had a big impact on DV. Some test sequences need to be adjusted to stop during lc reset or clock stops, and reset handling needs to change. The pwrmgr_clk_ctrl_agent was out of sync with the counterpart in pwrmgr_base_vseq, so we are moving all functionality to the latter. This PR disables that agent and a subsequent one will remove it. Signed-off-by: Guillermo Maturana <maturana@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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