commit df49fb8b1e15941a5a30d318c5415af8559e9271
author Udi Jonnalagadda <udij@google.com> Tue Mar 17 11:05:17 2020 -0700
committer sriyerg <46467186+sriyerg@users.noreply.github.com> Mon Mar 23 10:30:05 2020 -0700
tree 721d41e363603fcdde15e289e97277594c0a7393
parent 2c9d0f444e5c11d650efe17b2b94891818c0da44

[dvsim] migrate testplanner into dvsim codebase

Signed-off-by: Udi Jonnalagadda <udij@google.com>

util/dvsim/SimCfg.py

diff --git a/util/dvsim/SimCfg.py b/util/dvsim/SimCfg.py
index 6cf16da..969263d 100644
--- a/util/dvsim/SimCfg.py
+++ b/util/dvsim/SimCfg.py
@@ -10,10 +10,10 @@
 
 from testplanner import class_defs, testplan_utils
 
-from .Deploy import *
-from .FlowCfg import FlowCfg
-from .Modes import *
-from .utils import *
+from Deploy import *
+from FlowCfg import FlowCfg
+from Modes import *
+from utils import *
 
 
 class SimCfg(FlowCfg):