commit df195f04653f44c8084efa6ae412cc299422366b
author Mark Branstad <mark.branstad@wdc.com> Wed Feb 03 13:29:54 2021 -0800
committer Philipp Wagner <mail@philipp-wagner.com> Thu Feb 04 09:59:08 2021 +0000
tree b1dafa403edcdb33ed679788f0c05866d84e4a9a
parent 58087d774e4c73a5d856c0458cc61530ba186078

[entropy_src/rtl] variation on fifo port add

Slight variation on the port order for the sync fifo.

Signed-off-by: Mark Branstad <mark.branstad@wdc.com>

hw/ip/entropy_src/rtl/entropy_src_core.sv

diff --git a/hw/ip/entropy_src/rtl/entropy_src_core.sv b/hw/ip/entropy_src/rtl/entropy_src_core.sv
index c3621a9..828aa74 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_core.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_core.sv
@@ -83,7 +83,7 @@
   logic                   sfifo_esrng_push;
   logic                   sfifo_esrng_pop;
   logic                   sfifo_esrng_clr;
-  logic                   sfifo_esrng_not_full;
+  logic                   sfifo_esrng_full;
   logic                   sfifo_esrng_not_empty;
   logic [2:0]             sfifo_esrng_err;
 
@@ -104,6 +104,7 @@
   logic                   sfifo_esfinal_pop;
   logic                   sfifo_esfinal_clr;
   logic                   sfifo_esfinal_not_full;
+  logic                   sfifo_esfinal_full;
   logic                   sfifo_esfinal_not_empty;
   logic [2:0]             sfifo_esfinal_err;
   logic [SeedLen-1:0]     esfinal_data;
@@ -469,12 +470,12 @@
     .clr_i      (sfifo_esrng_clr),
     .wvalid_i   (sfifo_esrng_push),
     .wdata_i    (sfifo_esrng_wdata),
-    .wready_o   (sfifo_esrng_not_full),
+    .wready_o   (),
     .rvalid_o   (sfifo_esrng_not_empty),
     .rdata_o    (sfifo_esrng_rdata),
     .rready_i   (sfifo_esrng_pop),
-    .depth_o    (),
-    .full_o     ()
+    .full_o     (sfifo_esrng_full),
+    .depth_o    ()
   );
 
   // fifo controls
@@ -491,7 +492,7 @@
   assign sfifo_esrng_err =
          {1'b0,
          (sfifo_esrng_pop && !sfifo_esrng_not_empty),
-         (!sfifo_esrng_not_full && !sfifo_esrng_not_empty)};
+         (sfifo_esrng_full && !sfifo_esrng_not_empty)};
 
 
   // pack esrng bus into signal bit packer
@@ -1263,8 +1264,8 @@
     .rvalid_o   (sfifo_precon_not_empty),
     .rdata_o    (sfifo_precon_rdata),
     .rready_i   (sfifo_precon_pop),
-    .depth_o    (sfifo_precon_depth),
-    .full_o     ()
+    .full_o     (),
+    .depth_o    (sfifo_precon_depth)
   );
 
 
@@ -1428,8 +1429,8 @@
     .rvalid_o       (sfifo_esfinal_not_empty),
     .rready_i       (sfifo_esfinal_pop),
     .rdata_o        (sfifo_esfinal_rdata),
-    .depth_o        (sfifo_esfinal_depth),
-    .full_o         ()
+    .full_o         (sfifo_esfinal_full),
+    .depth_o        (sfifo_esfinal_depth)
   );
 
   assign fips_compliance = !es_bypass_mode && es_enable_rng && !es_enable_lfsr && !rng_bit_en;
@@ -1445,9 +1446,9 @@
 
   // fifo err
   assign sfifo_esfinal_err =
-         {(sfifo_esfinal_push && !sfifo_esfinal_not_full),
+         {(sfifo_esfinal_push && sfifo_esfinal_full),
           (sfifo_esfinal_pop && !sfifo_esfinal_not_empty),
-          (!sfifo_esfinal_not_full && !sfifo_esfinal_not_empty)};
+          (sfifo_esfinal_full && !sfifo_esfinal_not_empty)};
 
   // drive out hw interface
   assign es_hw_if_req = entropy_src_hw_if_i.es_req;