| commit | 7c0c1ebcce7ddefdffd18dbedb514dda5ea674f5 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Fri Sep 11 12:12:55 2020 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Wed Sep 16 12:07:44 2020 +0100 |
| tree | 894c9242d475acad07377ddd3f3f5af7119692ce | |
| parent | d9a03a7426a496c1bc6d0ac4fcd52231472d37df [diff] |
[otbn] Make an explicit class to represent OTBN's dmem in the ISS
The main motivation here was to make sure we always dumped the right
number of bytes when dumping dmem from the stepped simulator. However,
this patch lets us clean up several other things:
- We no longer inherit from riscvmodel.State. We were doing that,
and then promptly overriding several attributes (and calling some
non-existant methods!). It turns out that we weren't actually
getting much from the subclass, so it makes more sense just to
inline it.
- As a result, we can call the thing representing DMEM by the name
"dmem" rather than "memory", which is nice.
- We now get to be explicit about how things are stored in
memory (as 256-bit unsigned integers). This matches how the wide
register file works, so should be a bit more efficient than what
we had.
- And, of course, everything now has mypy annotations, which makes
the linting check a bit stricter.
- In the spirit of being explicit, we get rid of pc_update and the
magic that was in State.__setattr__, instead defining pc_next.
This is either None or an integer; the latter meaning to redirect
the PC.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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